TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS AM (512K x 8 / 256K x 16) BIT CMOS FLASH MEMORY DESCRIPTION The TC58FVT400/B400 is a 4,194,304 - bits, 3.0 Volt-only Electrically Erasable and Programmable Flash memory organized as 524,288 words X 8 bits or 262,144 words X 16 bits. The TC58FVT400/B400 features commands for read, program and erase operations to allow easy interfacing to microprocessors. The commands are based on the JEDEC standard. The program and erase operations are automatically executed in the chip. The device has chip, block and multi - block erase capabilit The TC58FVT400/B400 is available in either a 44-pin plastic SOP or 48- pin TSOP package to suit a variety of design applications. FEATURES Power Supply Vpp = 2.7 V to 3.6V Organization 512K X 8bits / 256K x 16 bits @ Modes Auto Program, Auto Chip Erase Auto Block Erase, Auto Multiple Block Erase Erase Suspend/ Resume, Block Protection Data Polling / Toggle Bit Block Erase Architecture 1X 16K byte / 2 x 8K byte / 1 X 32K byte / 7 x 64K byte @ Boot Block Architecture TC58FVT400F/FT ---Top Boot Block TC58FVB400F/FT --- Bottom Boot Block PIN ASSIGNMENT (TOP VIEW) Mode Control Compatible with JEDEC - standard command e@ Erase /Program Cycles 105 Cycles Typ. @ Access Time 85 ns (Vpp = 3. 100 ns/120ns (Vpp = 2. Power Dissipation 0 3.6 V) OV 7V to 3.0V) st ct } 250 vA (Standby TTL level) 10 vA (Standby CMOS level) 30 mA (Read Operating) 40 mA (Program / Erase Operating) @ Package TCS58FVT400F/B400F : SOP44-P-600-1.27 (Weight : 1.9 g Typ.) TC58FVT400FT/B400FT : TSOP48 - P - 1220 - 0.50 (Weight : 0.58 g Typ.) NCd1 \/ 44h RESET ais d 4 a3 b ate PIN NAMES RDY/BSY g 2 430 WE Al4q 2 O 47 7 BYTE Al7 q3 420 A8 A13 9 3 46 F Vss AO to A17 | address Input A7 a4 41PA9 A1l2 q 4 45 8 DQI5/A-1 A b Al1q 5 44 Pp DQ? DQO to DQ14 | Data Input/Output 64 407 A10 A10 d 6 43 b DQ 14 QO to PQ14 | Data input/ Outpu A5q6 39PA11 AI ad 7 42 9 DQ6 pad? 3Bhai2 aad 8 41) DO13 DQ15/A-1 Output (Input) / Address Input A348 37PR A13 NC gq 9 40 p DQ5 CE ; ard 36H Ata Ne d 10 39 b pg 12 cE Chip Enable Input Aig 10 35PA15 = WEY 11 38 F DQ4 OE Output Enable Input RESET 4 12 37 6 Vpb Ad g 11 34H A16 Nc gd 13 36 BP DQ 11 _____ CE d 12 33PE BYTE Nc d 14 35 1 DO3 BYTE Word / Byte Select Input Vss 4 13 32F Vss RDY/BSY 4 15 34 B DQ 10 Wwe OE g 14 31 DQ 15/A-1 NC 4 16 33 A DQ2 WE Write Enable Input Ai7 q 17 32 6 DQY ___ DQ0q 15 307 DQ7 A7 d 18 31 4 DG 1 RDY/BSY Ready /Busy Output DQ8q 16 29P DQ 14 A6q 19 30 BP DQ8 __ DQ195 17 28F DQ6 A5 qd 20 29 PF DQO RESET Hardware Reset Input DQ90 18 277 DQ 13 A4q 21 28 B OE pQa2q0 19 269 DO5 a q 23 7 H us Nc No Connection DQ 10 4 20 25P DQ 12 q F DQ3421 24h DQ4 Al q 24 25 FAO Vpp Power Supply DQ 114 22 237 Vpp TC58FVT400FT / B400FT (TSOP) Vss Ground TC58FVT4O0F/B400F (SOP) 961001EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1997-07-15 1/28TOSHIBA BLOCK DIAGRAM TC58FVT400/B400F/FT-85,-10,-12 RDY/BSY Vpp 90 RDY /BSY DQO DQ15 Vss 9 > Buffer { sevceetaseetesveeee 1 > VO Buffer ] HT WE Control Auto Sequence Circuit Control Circuit BYTE o RESET o Command Register Program Erase Circuit Circuit Data Latch te CE, OE Control OE Circuit Column Decoder & Sense Amp. A0 o : A A qd _| d R d d oO r r w g e 5 3 D Memory Cell Array B Cc |G a d Al7o +4 ? e r h A-1 o am: Erase Block Decoder 1997-07-15 2/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 MODE SELECTION BYTE MODE | WORD MODE MODE CE | OF | WE | AQ | AB | AI AO | RESET | DQO to DQ71) | DQO to DQ15 Read L L H Ag A6 Al Ad H Dout Dout ID Read (Manufacturer Code) L L H Vip L L L H Code Code ID Read (Device Code) L L H Vip L L H H Code Code Standby H * * * * * * H High -Z High -Z Output Disable * H H * * * * * High - Z High - Z Write L H L AI Ab Al AO H Din Din Block Protect L Vip L Vip L H L H * * Verify Block Protect L L H Vip L H L H Code Code Temporary Block Unprotect * * * * * * * Vip * * Hardware Reset / Standby * * * * * * * L High -Z High -Z Notes : *: Vin or Vit 1) DQ8 to DQ15 is High-Z at Byte Mode ID CODE TABLE TYPE A18 to A12 A6 Al AO CODE (HEX) 1) Manufacturer Code * VIL VIL Vib 0098h Device TC58FVT400 * Vit Vit Vin 00CDh Code TC58FVB400 * Vi Vi Vin 004Ch Verfy Block Protect BA 2) VIL Vin VIL Data 3) Notes: *: Viqor Vii 1) DQ8 to DQ15 is High-Z at Byte Mode 2) BA: Block Address 3) 0001h Protected Block 0000h - Unprotected Block BYTE=Vj, for BYTE MODE BYTE=Vi4 for WORD MODE 1997-07-15 3/28TOSHIBA COMMAND SEQUENCE TC58FVT400/B400F/FT-85,-10,-12 COMMAND Waive FIRST BUS SECOND BUS THIRD BUS FOURTH BUS FIFTH BUS SIXTH BUS SEQUENCE CYCLES WRITE CYCLE WRITE CYCLE WRITE CYCLE | READAWRITE CYCLE] WRITE CYCLE WRITE CYCLE REQD | Addr. | Data | Addr. | Data | Addr. | Data | Addr. Data Addr. | Data | Addr. | Data Read / Reset 1 XXXXh | FOh Read / Reset Word 3 5555h | AAh | 2AAAh | 55h | 5555h | FOR RA? RD2 Byte AAAAh 5555h AAAAh ID Read / Word 3 5555h | AAh | 2AAAh | 55h | 5555h | 90h IA ID Verify Block Protect Byte AAAAh 5555h AAAAh Auto Word 4 5555h | adh | 2AAAh | 55h | 5555h | adh PA PD Pp rogram Byte AAAAh 5555h AAAAh Auto Word 6 5555h | AAh | 2AAAh | 55H | 5555h | goh | 5555h AAh 2AAAh | 55h | 5555h | 10h hip E Chip Erase Byte AAAAh 5555h AAAA AAAAh 5555h AAAAh Auto Word 6 5555h | AAh | 2AAAh | 55h | 5555h | goh | 5555h AAh 2AAAN | 55h BA? 30h Block E oc rase Byte AAAAN 5555h AAAAh AAAAN 5555h Block Word 6 5555h | AAh | 2AAAN | 55h | 5555h | 9Ah | 5555h AAh 2AAAh | 55h | 5555h | 9Ah P rotect Byte AAAAh 5555h AAAAh AAAAh 5555h AAAAh Block Erase Suspend Addr: Vi or Vi, Data: BOh Block Erase Resume Addr: Vi or Vi_, Data: 30h Notes :The system should generate the following address patterns ; 4) ID : ID Data Word mode : 5555h or 2AAAh to addresses A14 to AO. 0098h - Manuafcturer Code Byte mode : AAAAh or 5555h to addresses A14 to A-1. OOCDh - Device Code (TC58FVT400) 004Ch - Device Code (TC58FVB400) DQ8 to DQ15 are ignored at Word mode. Q Q 9 0001h - Protected Block 1) RA: Read Adress 0000h - Unproteted Block 2) RD: Read Data 5) PA: Proram Address 3) IA: ID Adderss (A6, A1, AO) 6) PD: Program Data 00h = Manuafcturer Code 7) BA: Block Address O1h=Device Cade 02h = Verify Block Protect (A17 to A12 = Block Address) The Address range is A17: A-1 in if Byte Mode (BYTE = Vj.) The Address range is A17: AO in if Word Mode (BYTE = Vjy) HARDWARE STATUS FLAGS STATUS DQ7 DQ6 DQ5 DQ3_| RDY/BSY Auto Programming DQ7 Toggle 0 0 0 In Progress Auto Erase (Erase Hold Time) 0 Toggle 0 0 0 Auto Erase 0 Toggle 0 1 0 Execeeded Auto Programming DQ7 Toggle 1 1 0 Time Limits Auto Erase 0 Toggle 1 1 0 Notes :1. DQ outputsa cell data and RDY/BSY outputs '1' when the operation has completed. 2. DQO, DQ1, DQ2 are reserved for future use. 3. DQ8 to DQ15 Output '0' or '1' at word mode. 4. DQO toDQ2, DQ4: Output '0'. 1997-07-15 4/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 BLOCK ERASE ADDRESS TABLES TC58FVT400 (Top Boot Block) BLOCK # Al7 | A116 | A15 | Al4 | A13 | A12 BYTE MODE WORD MODE ADDRESS RANGE SIZE ADDRESS RANGE SIZE BAO L L L * * * 00000h to OFFFFh | 64K byte | 00000h to O7FFFh | 32K word BA1 L L H * * * 10000h to 1FFFFh | 64K byte | 08000h to OFFFFh | 32K word BA2 L H L * * * 20000h to 2FFFFh | 64K byte | 10000h to 17FFFh | 32K word BA3 L H H * * * 30000h to 3FFFFh | 64K byte | 18000h to 1FFFFh | 32K word BA4 H L L * * * 40000h to 4FFFFh | 64K byte | 20000h to 27FFFh | 32K word BAS H L H * * * 50000h to 5FFFFh | 64K byte | 28000h to 2FFFFh | 32K word BA6 H H L * * * 60000h to 6FFFFh | 64K byte | 30000h to 37FFFh | 32K word BA7 H H H L * * 70000h to 77FFFh | 32K byte | 38000h to 3BFFFh | 16K word BA8& H H H H L L 78000h to 79FFFh | 8K byte | 3C000h to 3CFFFh | 4K word BAY H H H H L H |7A000h to 7BFFFh| 8K byte | 3D000h to 3DFFFh | 4K word BA10 H H H H H * 7C000h to 7FFFFh | 16K byte | 3E000h to 3FFFFh | 8K ward * ot Vin or Vip TC58FVB400 (Bottom Boot Block) BLOCK # A17 | A1l6 | A15 | Al4 | Al3 | A12 BYTE MODE WORD MODE ADDRESS RANGE SIZE ADDRESS RANGE SIZE BAO L L L L L * 00000h toO3FFFh | 16K byte | 00000h to O1FFFh | 8K word BA1 L L L L H L 04000h to OSFFFh | 8K byte | 02000h to O2FFFh | 4K ward BA2 L L L L H H | 06000h to O7FFFh | 8K byte | 03000h to O3FFFh | 4K word BA3 L L L H * * 08000h to OFFFFh | 32K byte | 04000h to O7FFFh | 16K word BA4 L L H * * * 10000h to 1FFFFh | 64K byte | 08000h to OFFFFh | 32K word BAS L H L * * * 20000h to 2FFFFh | 64K byte | 10000h to 17FFFh | 32 K word BA6 L H H * * * 30000h to 3FFFFh | 64K byte | 18000h to 1FFFFh | 32K word BA7 H L L * * * 40000h to 4FFFFh | 64K byte | 20000h to 27FFFh | 32K word BA8& H L H * * * 50000h to 5FFFFh | 64K byte | 28000h to 2FFFFh | 32K word BA9 H H L * * * 60000h to 6FFFFh | 64K byte | 30000h to 37FFFh | 32K word BA10 H H H * * * 70000h to 7FFFFh | 64K byte | 38000h to 3FFFFh | 32K word * o> Vin or Vit The Address range is A17:A-1 in if Byte Mode (BYTE = V\) The Address range is A17: AO in if Word Mode (BYTE =Vjy) 1997-07-15 5/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RANGE UNIT Vpp Vpp Supply Voltage -0.6 to 4.6 Vv VIN Input Voltage -0.6 toVpp + 0.5($4.6) Vv Vpaq Input/Output Voltage -0.6 to Vpp + 0.5(5 4.6) Vv Pp Power Dissipation 0.6 Ww Tso_DEeR Soldering Temperature (10s) 260 C Tstg Strage Temperature -55 to 150 C Topr Operating Temperature -40 to 85 C New Erase/ Program Cycling Capability 100,000 Cycle VipH Input High Voltage 1) 13.0 Vv losHort Output Short Circuit Current 2) 100 mA 1) Vipy supply over 10 second is not recommended. The device might be damaged. 2) Output shorted for no more than one second. No more than one output shorted at a time. CAPPACITANCE (Ta =25C, f = 1MHz) SYMBOL PARAMETER CONDITION TYP MAX UNIT Cin Input Pin Capacitance Vin = OV 4 8 pF Cout Output Pin Capacitance Vout = OV 10 12 pF Cin Control Pin Capacitance Vin = OV 8 10 pF This parameter is periodically sampled and is not 100% tested. DC and OPERATING CHARACTERISTICS (Ta= -40 to 85C) SYMBOL PARAMETER MIN MAX UNIT Vpp Vpp Supply Voltage 2.7 3.6 Vin Input High Level Voltage 2.0 Vpp + 0.5 V Vit Input Low Level Voltage -0.31) 0.8 Vip Voltage for ID Read and Block Protect 2) 11.4 12.6 1) -2V (Pulse width of 20ns Max.) 2) Vipy supply over 10 second is not recommended. The device might be damaged. 1997-07-15 6/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 DC CHARACTERISTICS (Ta = -40 to 85C, Vpp = 2.7 to 3.6V) SYMBOL PARAMETER CONDITION MIN. MAX. UNIT lu Input Leakage Current OV = Vin S Vop - +1 A v2 lLo Output Leakage Current OV = Vout = Vpp - +1 Von 1 Output High Voltage (TTL) lon = -0.4mA 2.4 - lou = -0.1mA Vop -0.4 - Vou2 Output High Voltage (CMOS) Vv lou = -2.5mA 0.85 x Vpp - VoL Output Low Voltage lo, = 4.0mA - 0.4 Vin=Vin/ Vit | =OmA Ippo 1 Vpp Average Read Current IN Iq IL /OUT - 30 teycLe = tac (Min) mA Ippo2 Vpp Average Program Current Vin = Vin / Vig lout = OMA - 40 Ippo3 Vpp Average Erase Current Vin= Vin / Vit. lout = OMA - 40 Ipps1 Vpp Standby Current (TTL) CE = RESET = Viy or RESET = Vi. - 250 CE = RESET = Vpp + 0.2V Ipps2 Vpp Standby Current (CMOS __ - 10 pbs pp y (CMOS) or RESET = Vss + 0.2V pA lip High Veltage Input Current 1.4V = Vip 212.6 1) - 200 VLKO Low Vpp Lock - out Voltage - - 2.5 Vv 1) Less than 10 seconds AC TEST CONDITIONS PARAMETER CONDITION Input Pulse Level 2.4V/0.4V Input Pulse Rise and Fall Time (10% to 90%) 5ns Timing Measurement Reference Level (Input) 1.5V/1.5V Timing Measurement Reference Level (Output) 15V/15V Output Load C_ (100 pF) + 1 TTL Gate 1997-07-15 7/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 AC CHARACTERISTICS -85 - 10 -12 SYMBOL PARAMETER Ta = 0 to 70C Ta = = 40 to 8'C UNIT Vopp = 3.0 to 3.6V Vpp = 2.7 to 3.6V MIN MAX MIN MAX MIN MAX tre Read Cycle Time 85 - 100 - 120 - ns tacc Address Access Time - 85 - 100 - 120 ns tee CE Access Time - 85 - 100 - 120 ns toe OE Access Time - 35 - 40 - 50 ns tcEE CE to Output Low Z 0 - a) - 0 - ns tore | OE to Output Low Z 0 = 0 - 0 - ns tory | OE Hold Time (Read) 0 - 0 - 0 - ns tov Output Data Hold Time 0 - 0 - 0 - ns tori CE to Output High Z - 30 - 30 - 30 ns tpr2 OE to Output High Z - 30 - 30 - 30 ns temp Command Write Cycle Time 85 - 100 - 120 - ns tas Address Setup Time 0 - 0 - 0 - ns tan Address Hold Time 45 - 50 - 50 - ns tps Data Setup Time 45 - 50 - 60 - ns toy Data Hold Time 0 - 0 - 0 - ns tweLtH | WE Low Level Hold Time * 45 - 50 - 50 - ns tweHH [| WE High Level Hold Time * 20 = 20 = 20 = ns tees CE Setup Time to WE Active * 0 - 0) - 0 - ns tcen | CE Hold Time from WE High Level * 0 - 0 - 0 - ns toes OE Setup to WE Active 0 = 0 = 0 = ns toeHp | OE Hold Time (Toggle/ Data Polling) 10 - 10 - 10 - ns tocHt | OE High Level Hold Time (Toggle) 20 - 20 - 20 - ns tppw Auto Program Time 16 ** - 16 ** - 16 ** - ps tpcew | Auto Chip Erase Time 15 ** - 15 ** - 15 ** - s tppew | Auto Block Erase Time 1.5 ** - 1.5 ** - 1.5 ** - s typs Vpp Setup Time 500 - 500 - 500 - 3 tausy | Program/Erase Valid to RDY/BSY Delay 35 - 40 - 50 - ns trp RESET Low Level Hold Time 500 - 500 - 500 - ns treapy | RESET Low Level to Read Mode - 20 - 20 - 20 us trp RDY/BSY Recovery Time 0 - 0 - 0 - ns try RESET Recovery Time 500 - 500 - 500 - ns tcests | CE Setup time BYTE Transition 5 - 5 - 5 - ns tetp _ | BYTE to Output High Z - 30 - 30 - 30 ns typt Vip Transition Time 4 - 4 - 4 - us typs Vip Setup Time 4 - 4 - 4 - is typH GE Hold Time (Block Protect) 8 - 8 - 8 - us tppLH WE Low Level Hold Time (Block Protect) 100 - 100 - 100 - ts teas Protect Address Setup Time 0 - 0 - 0 - ns tpay Protect Address Hold Time 0 - 0 - 0 - ns tcesp _]| CE Setup Time (Block Protect) 4 - 4 - 4 - us tceHp | CE Hold Time (Block Protect) 8 - 8 - 8 - ps * : WE Control ** > Typ. 1997-07-15 8/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 OPERATING MODE Read Mode When the device is set to the Read Mode, it acts as an asynchronous ROM with an access time of 85/100/120 ns. The device is set to the Read Mode after power-on or Auto - Program / Erase completed. Hither software or hardware reset needs to be input to return to the Read Mode when Auto - Program / Erase operation fails. Standby Mode The TC58FVT400/B400 has a low power Standby Mode controlled by either CE or RESET pin. The Standby current is less than 10 A at CMOS voltage levels (CE = RESET = Vpp + 0.2 V or RESET = Vsg + 0.2 V) or 250 vA at TTL levels (CE = RESET = Vyy or RESET = Vy,). The RESET controls not only the power but all command mode such as Auto - Program / Erase, ID - Read, etc., beside the CE controls the power. The I/O pins are in high impedance at Standby Mode. Command Write The TC58FVT400/B400 utilizes the JEDEC command control standrized for single power supply E2PROM. The Command is executed by inputting address and data into the command register. The Command is entered by WE control write (WE pulse at CE = Vj; and OF = Vyq) or CE control write (CE pulse at WE = Viz, and OF = Vyq). The Address is latched at falling edge of either WE or CE. The Data is latched at rising edge of either WE or CE. The I/O0 to7 are valid for data input and the TV/O8 to 15 are ignored. The Command is reset by inputting the Reset Command and then the device goes into the Read Mode. When the undefined command is input, the Command Register is reset and the device goes into the Read Mode. RESET (Software Reset) The device does not go into the read mode automatically when the command mode such as Auto- Program / Erase and ID - Read Operations are not correctly executed (for example; Program fail, Erase fail). The Reset or Read Command is needed for returning to the Read Mode. The Reset and Read Command are also needed for resetting the Command Register. RESET (Hardware Reset) The hardware reset is used for aborting the auto mode operation such as Auto-Program/Erase and for resetting the Operation Mode. The device goes into the Read Mode at 20s after inputting 500 ns low level pulse to RESET pin. The data might be corrupted when the device is reset during the auto mode operation. The device goes into the Read Mode at RESET = Vip or the Standby Mode at RESET = Vj, after the hardware reset. The I/O pins are in high impedance state at RESET = Viz. The Read Operation and the Command Input are allowed after the device goes into the Read Mode. 1997-07-15 9/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 ID - Read Mode The ID Read Mode is utilized to identify the device type. The ID Read Mode is set by either the command mode by inputting "90h" command or the EPROM mode by applying Vjp to the AQ pin. The data at address AO/A1/A6 = Vy, is the manufacturer code (0098h) while the data at address AO = Vin, Al/A6 = Viz is the device code (TC58FVT400 = CDh / TC58FVB400 = 4Ch). The access time of an ID read is the same as normal read operation. The I/O8 to 15 are in high impedance state at Byte Mode. Auto Program Mode The TC58FVT400/B400 can be programmed by either byte or word unit. The Auto Program Mode is set by entering the Program Command. The program address is latched at the falling edge of the WE signal and the data is latched at the rising edge in the fourth bus cycle. The auto programming starts at the rising edge of the WE signal in the forth bus cycle. The Program and Program Verify is automatically excuted by he chip. The device status in programming is determined by the hardware sequence flag. The programming to the protected block is ignored. The device goes to the read mode 3 us after rising edge of the WE signal in the fouth bus cycle when the auto program is addressed to the protected block. The device allows the programming of "0" data into "1" memory cells. The programming of "1" data into "0" cell will fail. Erasure is necessary to turn "0" cell to "1" cell. If the Auto Program Operation fails, the device keeps the programming state and does not return to the Read Mode. This device status is determined by the hardware sequence flag. Either Reset Command or hardware reset is necessary to turn the device into the Read Mode when fail. Auto Chip Erase Mode The Auto Chip Erase mode is set by entering the Chip Erase Command. The Auto Chip Erase operation starts at the rising edge of the WE in the sixth bus cycle. All memory cells are automatically preprogrammed to "0", erased and verified for erasure by the chip. This device status is determined by the hardware sequence flag. The command input is ignored during an Auto Chip Erase. The hardware reset enables to interrupt the Auto Chip Erase Operation. The Auto Chip Erase Operation is not correctly completed when interrupted, therefore, the re - erase operation is necessary to erase. The erasing to the protected block is ignored. If all blocks are protected, the Auto Erase Operation is not excuted and the device turns to the Read Mode 100 vs after rising edge of the WE signal in the sixth bus cycle. If the Auto Chip Erase Operation fails, the device keeps the erasing state and does not return to the Read Mode. This device status is determined by the hardware sequence flag. Either reset command or hardware reset is necessary to turn the device into the Read Mode when fail. 1997-07-15 10/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 Auto Block /Multi Block Erase Mode The Auto Block / Multi Block Erase Mode are set by entering the Block Erase Command. The Block Address is latched at the falling edge of the WE signal in the sixth bus cycle. The block erase starts at the hold time from the rising edge of the WE signal. All memory cells in the selected block are automatically preprogrammed to "0", erased and verified for erasure by the chip. The Multi Block Erase Operation enables to erase the multiple blocks. Additional block addresses and the Multi Block Erase Command must be input during the erase hold time of 50 us after each rising edge of the WE signal. The device status is determined by the hardware sequence flag. Commands (except erase suspend) are ignored during the Block/Multi Block Erase Operation. The operation is aborted by the hardware reset. The Auto Erase Operation is not correctly completed when aborted, therefore, the re - erase operation is necessary to erase. The erasing to the protected block is ignored. If all blocks of selected block are protected, the Auto Erase Operation is not excuted and the device turns to the Read Mode 100 ws after rising edge of the WE signal in the last bus cycle. If the Auto Erase Operation fails, the device keeps the erasing state and does not return to the Read Mode. This device status is determined by the hardware sequence flag. Either reset command or hardware reset is necessary to turn the device into the Read Mode when fail. Erase Suspend / Resume Mode The Erase Suspend mode is used to read a data from the block not selected for erasure. The Erase Suspend command is allowed during block erase operation or block erase hold time; it is ignored for other operation modes, The Block Erase Operation is also suspended if the suspend command is input during the Block Erase Hold Time. The device is reset if any other commands than suspend are input. The suspended device allows only read or Resume Command. The device goes to the suspend mode 15 ws after the Erase Suspend Command is input and the device goes to a Pseudo Read Mode. The data can be read out from an unselected block but the data is invalid if the address is set to a selected block for erasure. The device status can be determined by the hardware sequence flag. DQ6 (Toggle bit) stops toggling and RDY/BSY outputs "1" once the device is set the Pseudo Read Mode. The host processor must track the current device mode since there is no identification whether the device is in Pseudo or Normal Read Mode. The Pseudo Read Status is held when the Suspend Command is input during Suspend. The device restarts the Block Erase Operation after receiving a Resume Command. The device returns to the status of which a suspend command is input. DQ6 outputs the toggle signal and RDY/BSY outputs "0". 1997-07-15 11/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 Block Protect The TC58FVT400/B400 has a block Protection feature to prevent program and erasure for protected block. Block protection is enabled by either hardware protection (1) or software command mode (2). The initial device is shipped unprotected. (1) A block protected when; A9 = OK = Vjp, CE = Vy,, A0/A6 = Vy,, Al = Vin and the block address set using Al2 to A17. The Block Protect Data is programmed during the tppiy of WE signal. (2) A block can also be protected by using software command. The block protection is excuted by inputting the WE pulse of tpppy at CE = Vyz, A12 to Al7 = Block Address after command input in the sixth bus cycle. Block protection is verified by the Verify Block Protect. Temporary Block Protect The TC58FVT400/B400 has a Temporary Block Unprotect feature which disables block protection for all protected blocks. The unprotection is enabled by applying Vip to the RESET pin. The device can be programmed or erased for any block under this condition. The device returns to the previous condition after Vip removed from the RESET pin. That is, previously protected blocks are protected again. Verify Block Protect The Verify Block Protect is used to verify either block protected or unprotected. Verify Block Protect is enabled either through hardware (1) or software command (2). The data outputs '0001h' when protected and "0000h" when unprotected in word mode. I/O 8 to 15 are in high impedance at byte mode. (1) A Verify Block Protection is enabled when; A9 = Vyip, A0/A6 = Vj,, Al = Vin, A12 to A1l7 = Block Address. (2) A Verify Block Protection can also be enabled by using software command. 1997-07-15 12/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 HARDWARE SEQUENCE FLAG The TC58FVT400/B400 has a Hardware Sequence flag to determine the device status during auto operation. The output data is read out with the same timing as Read Mode at CE = OK = Vj. RDY/BSY outputs either high or low level. The device turns to the Read Mode automatically after auto operation has finished successfully. The device status is read out by hardware sequence flag and the operation result is verified by comparing a read-out data to an original data. DQ7 (DATA Polling) The device status can be determined by the data polling function during auto program or auto erase operation. DATA Polling begins from the rising edge of WE in the last bus cycle. In auto program operation, the DQ7 outputs an inverted data during the programming operation and outputs a true data after programming has finished. In auto erase operation, the DQ7 outputs "0" during the erasing operation and outputs "1" when the erase operation has finished. DQ7 outputs the same result as a data during auto operation if the operation has failed. The latched address is reset after an operation has finished. The polling data is asynchronous with the OE signal. DQ6 (Toggle Bit) The device status can be determined by the Toggle Bit function during Auto Program or Auto Erase Operation. Toggle Bit begins from the rising edge of WE in the last bus cycle in Program operation and begins at Erase Hold Time after the rising edge of WE in the last bus cycle. DQ6 outputs an alternating "0" and "1" for each attempt (OE access) at CE = Vyz, while the device is busy. When the internal operation is completed, toggling stops and valid memory cell data can be read on subsequent read. DQ6 outputs a toggling data if the operation has failed. DQ6 toggles for around 3 us when the Auto Program Operation is addressed to the protected block and then stops toggling. DQ6 toggles for around 100 ~s when the Auto Erase Operation is addressed to the protected block and then stops toggling. After toggling stops, the device turns into the Read Mode. DQ5 (Internal Time Out) DQ5 outputs "1" when the Internal Timer has timed out during Program or Erase Operation. This indicates that the Operation has not completed within the allotted time. The programming of "1" data into "0" cell will fail (See Auto Program Mode). DQ5 outputs "1" in this case. Either hardware reset or software reset command is necessary to turn the device into the Read Mode. 1997-07-15 13/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 DQ3 (Block Erase Timer) The Block Erase operation starts 50 ~s (Erase Hold Time) after the rising edge of WE in the last command cycle. DQ38 outputs "0" during the Block Erase Hold Time and "1" when the Erase Operation starts. Additional Block Erase Command can only be accepted during this Block Erase Hold Time. Each Block Erase Command given within this Hold Time resets the timer so that additional blocks can be marked for erasure. DQ3 outputs "1" if the device fails in Program or Erase Operation. RDY/BSY (READY/BUSY) TC58FVT400/B400 has a RDY/BSY signal to indicate the device status to the host processor. A "0" (busy state) indicates that Auto Program or Auto Erase Operation is in progress. A "1" (ready state) indicates that the operation has finished and the device can accept a new command, RDY/BSY outputs "0" when the operation has failed. RDY/BSY outputs "0" data after the rising edge of WE in the last command cycle in Program Operation or in the Erase Hold Time after the last command cycle in Erase Operation. During Auto Block Erase Operation, commands other than Erase Suspend will be ignored. RDY/BSY outputs "1" during Erase Suspend. The output buffer of the RDY/BSY pin is an open drain type circuit enabling a wired -or connection. A pullup resistor needs to be tied between Vpp and the RDY/BSY pin. DATA PROTECTION The TC58FVT400/B400 utilizes a JEDEC standard command sequence which protects data against inadvertent operation due to noise. Vee Lock Out Voltage The device is reset when Vpp is less than VLKo to protect memory cell data against Vpp noise or during power up and down. The Auto Program or Erase Operation stops when Vpp goes down below VLKO. The Erase Suspend is reset and the Erase Operation stops when the device is in Suspend mode. The Operation will not be correctly finished when interrupted by Vpp Lock Out. WE Glitch Pulse Glitches must be suppressed (less than 5 ns) for proper operation. Protection for Power On The device is reset and goes into the Read Mode after power on. A command is not accepted at the rising edge of WE if Vpp rises from 0 V to the operating voltage under the condition of CE = WE = Vj, OE = Vin. 1997-07-15 14/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 TIMING DIAGRAM Read/ID Read Operation Address toeH High - Z Dout Dout Valid ID Read Operation (Hardware) AO Al A6 High -Z 00CDh Dout /004Ch Notes: 0098h - Manufacturer Code O0CDh - Device Code (TC58FVT400) 004Ch - Device Code (TC58FVB400) 1997-07-15 15/28Address Y TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 Auto Program Operation (WE Contorl) tces tos toy (2 }{ ( DQ7X Dout v, Notes: Word mode address shown PA : Program Address PD : Program Data Auto Chip Erase / Auto Block Erase Operation (WE Control) Din Vpp AAAAE toes | tweLH tWeHH tps | tou T Notes: Word mode address shown BA: Block Address at Auto Block Erase Operation 1997-07-15 16/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 DATA Polling during Program /Erase Opeation Address Command Address CE OE WE tppw/ tecew/ tppew Din Dout 7 DQ? Dout 0 to 6 Invalid Notes : PA : Program Address BA : Block Address Toggle Bit during Program /Erase Operation Last Address Command PA/BA Address * Up, kX. / toEHT toeHP \_/ toe : Last Din Command 5 * tap Dout 6 Toggle Toggle ( vat) * Dout 6 stops toggling when the last command has completed. Notes : PA : Program Address BA : Block Address 1997-07-15 17/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 RDY/BSY during Auto Program / Erase Operation \ / Command Input Sequence jf] During Operation RDY/BSY \ teusy Hardware Reset Operation RESET \ tre TREADY RDY / BSY \ Read after RESET Address RESET Dout Data Valid 1997-07-15 18/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 BYTE for Read Operation CE tcEBTS OE BYTE tetp DQO0toDQ7 Output Data Output DQ8to DQ 14 outru : DQ 15/A-1 Address Input BYTE for Write Operation 7 \SV\S XS AS BYTE 1997-07-15 19/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 Block Protect Operation (Hardware) Block Protect | Verify Block Protect Al7to A12 AO Al AG Dout 0001h* BA: Block Address * : 000th indicates that block is protected. 1997-07-15 20/28Address Din Dout TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 Block Protect (Software) Block Protect Setup | Black Protect Verify Block Protect 6th Command Cycle tcesp >t tceHP he toe 9Ah BA: Block Address * . 000th indicates that block is protected. 1997-07-15 21/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 FLOW_ CHART Auto Program Auto Program Command Sequence (see below) DATA Polling or Toggle Bit Last Address? Yes Increment Address Auto Program Completed Auto Program Command Sequence (Address / Command) 5555h/ AAh 2AAAN/ 55h 5555h/AOh Program Address /Program Data Note : Word mode command sequenceis shown. 1997-07-15 22/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 Auto Erase Auto Erase Command Sequence (see below) DATA Polling or Toggle Bit Vv Auto Erase Completed Auto Chip Erase Command Sequence Auto Block/ Multiple Block (Address / Command) Erase Command Sequence (Address / Command) 5555h/ AAh 5555h/ AAh 2AAAh / 55h 2AAAh / 55h 5555h/80h 5555h/ 80h 5555h/ AAh 5555h/ AAh 2AAAh / 55h 2AAAh / 55h 5555h/ 10h Block Address / 30h Block Address / 30h Additional Block Erase commands are optional Block Address / 30h Note : Word mode command sequence is shown. 1997-07-15 23/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 DQ7 DATA Polling VA Note DQ 6 Toggle Bit VA Note Read Byte (DQ0 to DQ 7) Addr. = VA Vv. y DQ7 = Data? Read Byte (DQ0 to DQ 7) Addr. = VA DQ7 = Data? No | Fail | | v Pass Byte address for programming. Any of the addresses within the block being erased during a block erase operation. Don't care during chip erase. 1) DQ7 must be rechecked even if DQ5= 1 because DQ7 may change simultaneously with DQ5. Read Byte (DQ0 to DQ 7) Addr. = VA DQ6 = Toggle? Yes Ne 005 = 12 Yes () Read Byte (DQ0 to DQ 7) Addr. = VA DQ6 = Toggle ? Yes v | Fail | | Vv. Pass Byte address for programming. Any of the addresses within the block being erased during a block erase operation. Don't care during chip erase. Any address not within the block in the process of an Erase Suspend operation. 1) DQ6 must be rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time that DQ5 changes to 1. 1997-07-15 24/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 Setup Block Address Addr. = BA y PLSCNT = 1 t OE = AI = Vip, CE = Vi A6, Ail, AO = 0, 1, 0 Y Active WE Pulse Time Out 100 us AQ = Vip WE = Vy, CE = OF = Vy Increment PLSCNT Y Read from Block Address = BA; A6,A1, A0 = 0,1,0 Block Protect (Hardware) v A No Dat = 01h3 on Yes Yes Protect another Block? Device Failed No Remove Vip from A9 Block Protect Complete BA: Block Address 1997-07-15 25/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 ->} PLSCNT = 1 | Write Block Protect Command Sequence = Vin, OE = Vin, WE = Vin t Setup Block Address Address = BA Block Protect (Software) A ml Y | CE = Vin, OF = Vin, WE = Vin | Increment PLSCNT z | Time Out 4 us | t | Write ID Read Command Sequence | y | Write Reset Command Sequence | Read from Block Address = BA; A6, A1, A0 = 0, 1,0 No Yes Yes | Write Reset Command Sequence | Protect another Block? No Device Failed | Block Protect Complete | BA : Block Address 1997-07-15 26/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 PACKAGE DIMENSIONS @ Plastic SOP SOP44P6001.27 EASRRERRRRRRRERRRRRRRE HOGER POH H BE b oN ; 28.7MAX ,; 28,2+0.2 | 3.1MAX 9A5 Obs 0.1940.1 || 2.740.2 0.1] 1997-07-15 27/28TOSHIBA TC58FVT400/B400F/FT-85,-10,-12 PACKAGE DIMENSIONS @ Plastic TSOP TSOP I 48 -P12200.50 Unit : mm 1 = J 48 wo O : a = a = N rl = t = xf oo = S| F | Ml al yr IL A Cy Cy Cy Cy 24 cl ' x 25 + . 18.440.1 . 6 1.00.1 | |, 0.140.05 20.040.2 oS 1.2MAX } Ww Ww o. Q Ww << = Qo o 1997-07-15 28/28