High Performance, 145 MHz
Fast
FET™ Op Amps
AD8065/AD8066
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
FET input amplifier
1 pA input bias current
Low cost
High speed: 145 MHz, −3 dB bandwidth (G = +1)
180 V/µs slew rate (G = +2)
Low noise
7 nV/√Hz (f = 10 kHz)
0.6 fA/√Hz (f = 10 kHz)
Wide supply voltage range: 5 V to 24 V
Single-supply and rail-to-rail output
Low offset voltage 1.5 mV max
High common-mode rejection ratio: −100 dB
Excellent distortion specifications
SFDR −88 dB @ 1 MHz
Low power: 6.4 mA/amplifier typical supply current
No phase reversal
Small packaging: SOIC-8, SOT-23-5, and MSOP
APPLICATIONS
Instrumentation
Photodiode preamps
Filters
A/D drivers
Level shifting
Buffering
CONNECTION DIAGRAMS
1
2
3
5
4
1
4
3
5
27
8
6
8
7
6
5
1
2
3
4
V
OUT
V
OUT1
V
OUT2
V
OUT
–V
S
–V
S
–V
S
+IN
+V
S
+V
S
+V
S
–IN
–IN1
+IN1 –IN2
+IN2
NC
–IN
+IN
NC
NC
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
AD8065
AD8066
AD8065
02916-E-001
Figure 1.
GENERAL DESCRIPTION
The AD8065/AD80661 FastFET amplifiers are voltage feedback
amplifiers with FET inputs offering high performance and ease
of use. The AD8065 is a single amplifier, and the AD8066 is a
dual amplifier. These amplifiers are developed in the Analog
Devices, Inc. proprietary XFCB process and allow exceptionally
low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as
very high input impedance.
With a wide supply voltage range from 5 V to 24 V, the ability to
operate on single supplies, and a bandwidth of 145 MHz, the
AD8065/AD8066 are designed to work in a variety of
applications. For added versatility, the amplifiers also contain
rail-to-rail outputs.
Despite the low cost, the amplifiers provide excellent overall
performance. The differential gain and phase errors of 0.02%
and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz,
make these amplifiers ideal for video applications. Additionally,
they offer a high slew rate of 180 V/µs, excellent distortion
(SFDR of −88 dB @ 1 MHz), extremely high common-mode
rejection of −100 dB, and a low input offset voltage of 1.5 mV
maximum under warmed up conditions. The AD8065/AD8066
operate using only a 6.4 mA/amplifier typical supply current
and are capable of delivering up to 30 mA of load current.
The AD8065/AD8066 are high performance, high speed,
FET input amplifiers available in small packages: SOIC-8,
MSOP-8, and SOT-23-5. They are rated to work over the
industrial temperature range of −40°C to +85°C.
–6
–3
0
3
6
9
12
15
18
21
24
GAIN (dB)
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-002
G = +10 V
O
= 200mV p-p
G = +5
G = +2
G = +1
Figure 2. Small Signal Frequency Response
1Protected by U. S. Patent No. 6,262,633.
AD8065/AD8066
Rev. E | Page 2 of 28
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Maximum Power Dissipation..................................................... 7
Output Short Circuit.................................................................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 15
Theory of Operation...................................................................... 18
Closed-Loop Frequency Response........................................... 18
Noninverting Closed-Loop Frequency Response.................. 18
Inverting Closed-Loop Frequency Response ......................... 18
Wideband Operation ................................................................. 19
Input Protection.......................................................................... 19
Thermal Considerations............................................................ 20
Input and Output Overload Behavior...................................... 20
Layout, Grounding, and Bypassing Considerations................... 21
Power Supply Bypassing............................................................ 21
Grounding ................................................................................... 21
Leakage Currents........................................................................ 22
Input Capacitance....................................................................... 22
Output Capacitance ...................................................................22
Input-to-Output Coupling ........................................................ 23
Wideband Photodiode Preamp................................................ 23
High Speed JFET Input Instrumentation Amplifier.............. 24
Video Buffer................................................................................ 24
Outline Dimensions....................................................................... 25
Ordering Guide........................................................................... 26
REVISION HISTORY
2/04—Data Sheet Changed from Rev. D to Rev. E.
Updated Format.................................................................Universal
Updated Figure 56.........................................................................21
Updated Outline Dimensions......................................................25
Updated Ordering Guide..............................................................26
11/03—Data Sheet changed from Rev. C to Rev. D.
Changes to Features ........................................................................ 1
Changes to Connection Diagrams................................................ 1
Updated Ordering Guide................................................................ 5
Updated Outline Dimensions......................................................22
4/03—Data Sheet changed from Rev. B to Rev. C.
Added SOIC-8 (R) for the AD8065............................................... 4
2/03—Data Sheet changed from Rev. A to Rev. B.
Changes to Absolute Maximum Ratings...................................... 4
Changes to Test Circuit 10 ...........................................................14
Changes to Test Circuit 11 ...........................................................15
Changes to Noninverting Closed-Loop Frequency Response 16
Changes to Inverting Closed-Loop Frequency Response .......16
Updated Figure 6 .......................................................................... 18
Changes to Figure 7.......................................................................19
Changes to Figures 10...................................................................21
Changes to Figure 11.....................................................................22
Changes to High Speed JFET Instrumentation Amplifier....... 22
Changes to Video Buffer...............................................................22
8/02—Data Sheet changed from Rev. 0 to Rev. A.
Added AD8066 ..................................................................Universal
Added SOIC-8 (R) and MSOP-8 (RM) ........................................1
Edits to General Description .........................................................1
Edits to Specifications..................................................................... 2
New Figure 2 .................................................................................... 5
Changes to Ordering Guide........................................................... 5
Edits to TPCs 18, 25, and 28........................................................... 8
New TPC 36 ................................................................................... 11
Added Test Circuits 10 and 11..................................................... 14
MSOP (RM-8) added....................................................................23
AD8065/AD8066
Rev. E | Page 3 of 28
SPECIFICATIONS
@ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 100 145 MHz
G = +1, VO = 0.2 V p-p (AD8066) 100 120 MHz
G = +2, VO = 0.2 V p-p 50 MHz
G = +2, VO = 2 V p-p 42 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz
Input Overdrive Recovery Time G = +1, −5.5 V to +5.5 V 175 ns
Output Recovery Time G = −1, −5.5 V to +5.5 V 170 ns
Slew Rate G = +2, VO = 4 V Step 130 180 V/µs
Settling Time to 0.1% G = +2, VO = 2 V Step 55 ns
G = +2, VO = 8 V Step 205 ns
NOISE/HARMONIC PERFORMANCE
SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −88 dBc
f
C = 5 MHz, G = +2, VO = 2 V p-p −67 dBc
f
C = 1 MHz, G = +2, VO = 8 V p-p −73 dBc
Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm
Input Voltage Noise f = 10 kHz 7 nV/√Hz
Input Current Noise f = 10 kHz 0.6 fA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.02 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.02 Degree
DC PERFORMANCE
Input Offset Voltage VCM = 0 V, SOIC Package 0.4 1.5 mV
Input Offset Voltage Drift 1 17 µV/°C
Input Bias Current SOIC Package 2 6 pA
T
MIN to TMAX 25 pA
Input Offset Current 1 10 pA
T
MIN to TMAX 1 pA
Open-Loop Gain VO = ±3 V, RL = 1 kΩ 100 113 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000 || 2.1 GΩ || pF
Differential Input Impedance 1000 || 4.5 GΩ || pF
Input Common-Mode Voltage Range
FET Input Range −5 to +1.7 −5.0 to +2.4 V
Usable Range See the Theory of Operation section −5.0 to +5.0 V
Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB
V
CM = −1 V to +1 V (SOT-23) −82 −91 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ −4.88 to +4.90 −4.94 to +4.95 V
R
L = 150 Ω −4.8 to +4.7 V
Output Current VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA
Short-Circuit Current 90 mA
Capacitive Load Drive 30% Overshoot G = +1 20 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current per Amplifier 6.4 7.2 mA
Power Supply Rejection Ratio ±PSRR −85 −100 dB
AD8065/AD8066
Rev. E | Page 4 of 28
@ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE MHz
−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 100 145 MHz
G = +1, VO = 0.2 V p-p (AD8066) 100 115 MHz
G = +2, VO = 0.2 V p-p 50 MHz
G = +2, VO = 2 V p-p 40 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz
Input Overdrive Recovery G = +1, −12.5 V to +12.5 V 175 ns
Output Overdrive Recovery G = −1, −12.5 V to +12.5 V 170 ns
Slew Rate G = +2, VO = 4 V Step 130 180 V/µs
Settling Time to 0.1% G = +2, VO = 2 V Step 55 ns
G = +2, VO = 10 V Step 250 ns
NOISE/HARMONIC PERFORMANCE
SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −100 dBc
f
C = 5 MHz, G = +2, VO = 2 V p-p −67 dBc
f
C = 1 MHz, G = +2, VO = 10 V p-p −85 dBc
Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm
Input Voltage Noise f = 10 kHz 7 nV/√Hz
Input Current Noise f = 10 kHz 1 fA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.04 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.03 Degree
DC PERFORMANCE
Input Offset Voltage VCM = 0 V, SOIC Package 0.4 1.5 mV
Input Offset Voltage Drift 1 17 µV/°C
Input Bias Current SOIC Package 3 7 pA
T
MIN to TMAX 25 pA
Input Offset Current 2 10 pA
T
MIN to TMAX 2 pA
Open-Loop Gain VO = ±10 V, RL = 1 kΩ 103 114 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000 || 2.1 GΩ || pF
Differential Input Impedance 1000 || 4.5 GΩ || pF
Input Common-Mode Voltage Range
FET Input Range −12 to +8.5 −12.0 to +9.5 V
Usable Range See the Theory of Operation section −12.0 to +12.0 V
Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB
V
CM = −1 V to +1 V (SOT-23) −82 −91 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ −11.8 to +11.8 −11.9 to +11.9 V
R
L = 350 Ω −11.25 to +11.5 V
Output Current VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 30 mA
Short-Circuit Current 120 mA
Capacitive Load Drive 30% Overshoot G = +1 25 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current per Amplifier 6.6 7.4 mA
Power Supply Rejection Ratio ±PSRR −84 −93 dB
AD8065/AD8066
Rev. E | Page 5 of 28
@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 125 155 MHz
G = +1, VO = 0.2 V p-p (AD8066) 110 130 MHz
G = +2, VO = 0.2 V p-p 50 MHz
G = +2, VO = 2 V p-p 43 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 6 MHz
Input Overdrive Recovery Time G = +1, −0.5 V to +5.5 V 175 ns
Output Recovery Time G = −1, −0.5 V to +5.5 V 170 ns
Slew Rate G = +2, VO = 2 V Step 105 160 V/µs
Settling Time to 0.1% G = +2, VO = 2 V Step 60 ns
NOISE/HARMONIC PERFORMANCE
SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −65 dBc
f
C = 5 MHz, G = +2, VO = 2 V p-p −50 dBc
Third-Order Intercept fC = 10 MHz, RL = 100 Ω 22 dBm
Input Voltage Noise f = 10 kHz 7 nV/√Hz
Input Current Noise f = 10 kHz 0.6 fA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.13 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.16 Degree
DC PERFORMANCE
Input Offset Voltage VCM = 1.0 V, SOIC Package 0.4 1.5 mV
Input Offset Voltage Drift 1 17 µV/ºC
Input Bias Current SOIC Package 1 5 pA
T
MIN to TMAX 25 pA
Input Offset Current 1 5 pA
T
MIN to TMAX 1 pA
Open-Loop Gain VO = 1 V to 4 V (AD8065) 100 113 dB
V
O = 1 V to 4 V (AD8066) 90 103 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000 || 2.1 GΩ || pF
Differential Input Impedance 1000 || 4.5 GΩ || pF
Input Common-Mode Voltage Range
FET Input Range 0 to 1.7 0 to 2.4 V
Usable Range See the Theory of Operation section 0 to 5.0 V
Common-Mode Rejection Ratio VCM = 1 V to 4 V −74 −100 dB
V
CM = 1 V to 2 V (SOT-23) −78 −91 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ 0.1 to 4.85 0.03 to 4.95 V
R
L = 150 Ω 0.07 to 4.83 V
Output Current VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA
Short-Circuit Current 75 mA
Capacitive Load Drive 30% Overshoot G = +1 5 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current per Amplifier 5.8 6.4 7.0 mA
Power Supply Rejection Ratio ±PSRR −78 −100 dB
AD8065/AD8066
Rev. E | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 26.4 V
Power Dissipation See Figure 3
Common-Mode Input Voltage VEE − 0.5 V to VCC + 0.5 V
Differential Input Voltage 1.8 V
Storage Temperature −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature Range
(Soldering, 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8065/AD8066
Rev. E | Page 7 of 28
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction
temperature (TJ) on the die. The plastic encapsulating the die
will locally reach the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic will
change its properties. Even temporarily exceeding this
temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8065/AD8066. Exceeding a junction
temperature of 175°C for an extended period of time can result
in changes in the silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and total power dissipated in the
package (PD) determine the junction temperature of the die. The
junction temperature can be calculated as
(
)
JA
D
A
JPTT θ×+=
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS /2 × IOUT, some of
which is dissipated in the package and some in the load (VOUT ×
IOUT). The difference between the total drive power and the load
power is the drive power dissipated in the package.
(
)
PowerLoadPowerDriveTotalPowerQuiescentPD−+=
()
L
OUT
L
OUT
S
SS
DR
V
R
VV
IVP
2
2−
⎟
⎠
⎞
⎜
⎝
⎛×+×=
RMS output voltages should be considered. If RL is referenced to
VS−, as in single-supply operation, then the total drive power is
VS × IOUT.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply.
()
()
L
S
SS
DR
V
IVP
2
4/
+×=
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
MAXIMUM POWER DISSIPATION (W)
0
0.5
1.0
1.5
2.0
200–40 –20–60 40 60 80 100
AMBIENT TEMPERATURE (°C)
02916-E-003
MSOP-8
SOIC-8
SOT-23-5
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps as
discussed in the Layout, Grounding, and Bypassing
Considerations section.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC
(125°C/W), SOT-23 (180°C/W), and MSOP (150°C/W)
packages on a JEDEC standard 4-layer board. θJA values are
approximations.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8065/AD8066 will likely cause catastrophic failure.
AD8065/AD8066
Rev. E | Page 8 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: ±5 V, CL = 5 pF, RL = 1 kΩ, VOUT = 2 V p-p, Temperature = 25°C.
–6
–3
0
3
6
9
12
15
18
21
24
GAIN (dB)
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-004
G = +10 V
O
= 200mV p-p
G = +5
G = +2
G = +1
Figure 4. Small Signal Frequency Response for Various Gains
–6
–4
–2
0
2
4
6
GAIN (dB)
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-005
V
O
= 200mV p-p
G = +1
V
S
= +5V
V
S
= ±12V
V
S
= ±5V
Figure 5. Small Signal Frequency Response for Various Supplies (See Figure 42)
–5
–4
–3
–2
–1
0
1
2
GAIN (dB)
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-006
V
O
= 2V p-p
G = +1
V
S
= ±12V
V
S
= ±5V
Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 42)
5.9
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
GAIN (dB)
FREQUENCY (MHz)
0.1 101 100
02916-E-007
R
L
= 150Ω
G = +2 V
OUT
= 0.2V p-p
V
OUT
= 0.7V p-p
V
OUT
= 1.4V p-p
Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43)
3
4
5
6
7
8
9
GAIN (dB)
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-008
V
O
= 200mV p-p
G = +2
V
S
= ±12V
V
S
= ±5V
V
S
= +5V
Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 43)
0
1
2
3
4
5
GAIN (dB)
6
7
8
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-009
G = +2
V
S
= ±12V
V
S
= ±5V
V
S
= +5V
Figure 9. Large Signal Frequency Response for Various Supplies (See Figure 43)
AD8065/AD8066
Rev. E | Page 9 of 28
–9
–6
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-010
G = +1 C
L
= 25pF
C
L
= 25pF
R
SNUB
= 20
Ω
C
L
= 20pF
C
L
= 5pF
V
O
= 200mV p-p
Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42)
–8
–6
–4
–2
0
2
GAIN (dB)
4
6
8
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-011
G = +2
V
OUT
= 0.2V p-p
V
OUT
= 2V p-p
V
OUT
= 4V p-p
Figure 11. Frequency Response for Various Output Amplitudes (See Figure 43)
–4
–2
0
2
4
6
8
10
12
14
GAIN (dB)
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-012
G = +2
R
F
= R
G
= 1k
Ω
,
R
S
= 500
Ω
R
F
= R
G
= 500
Ω
,
R
S
= 250
Ω
R
F
= R
G
= 500
Ω
,
R
S
= 250
Ω
,
C
F
= 2.2pF
R
F
= R
G
= 1k
Ω
,
R
S
= 500
Ω
,
C
F
= 3.3pF
V
O
= 200mV p-p
Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43)
–8
–6
–4
–2
0
2
GAIN (dB)
4
6
8
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-013
C
L
= 25pF
C
L
= 55pF
C
L
= 5pF
V
O
= 200mV p-p
G = +2
Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43)
0
1
2
3
4
5
GAIN (dB)
6
7
8
FREQUENCY (MHz)
10.1 10 100 1000
02916-E-014
R
L
= 100
Ω
R
L
= 1k
Ω
V
O
= 200mV p-p
G = +2
Figure 14. Small Signal Frequency Response for Various RLOAD (See Figure 43)
–180
–120
–60
0
60
120
PHASE (DEGREES)
–20
0
20
40
60
80
OPEN-LOOP GAIN (dB)
0.01 0.1 1 10 100 1000
FREQUENCY (MHz)
02916-E-015
PHASE
GAIN
Figure 15. Open-Loop Response
AD8065/AD8066
Rev. E | Page 10 of 28
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
DISTORTION (dBc)
FREQUENCY (MHz)
0.1 101 100
02916-E-016
HD3 R
L
= 150
Ω
HD2 R
L
= 150
Ω
HD3 R
L
= 1k
Ω
HD2 R
L
= 1k
Ω
G = +2
Figure 16. Harmonic Distortion vs. Frequency for Various Loads (See Figure 43)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
DISTORTION (dBc)
01234 6 105 789 1211 1413 15
OUTPUT AMPLITUDE (V p-p)
02916-E-017
HD3 R
L
= 150
Ω
HD2 R
L
= 150
Ω
HD3 R
L
= 300
Ω
HD2 R
L
= 300
Ω
G = +2
V
S
= ±12V
F = 1MHz
Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = ±12 V
(See Figure 43)
15
20
25
30
35
40
45
50
INTERCEPT POINT (dBm)
FREQUENCY (MHz)
110
02916-E-018
V
S
= ±12V R
L
= 100
Ω
V
S
= ±5V
V
S
= +5V
Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage
–110
–100
–90
–80
–70
–60
–50
–40
DISTORTION (dBc)
FREQUENCY (MHz)
0.1 101 100
02916-E-019
HD2 G = +2
HD3 G = +2
HD2 G = +1
HD3 G = +1
Figure 19. Harmonic Distortion vs. Frequency for Various Gains
(See Figure 42 and Figure 43)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
DISTORTION (dBc)
FREQUENCY (MHz)
0.1 1.0 10.0
02916-E-020
HD2 V
O
= 20V p-p
HD3 V
O
= 20V p-p
HD2 V
O
= 10V p-p
HD3 V
O
= 10V p-p
HD2 V
O
= 2V p-p
HD3 V
O
= 2V p-p
V
S
= ±12V
G = +2
Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes
(See Figure 42 and Figure 43)
NOISE (nV/ Hz)
1
10
100
100k10k100 1k10 1M 10M 100M 1G
FREQUENCY (Hz)
02916-E-021
Figure 21. Voltage Noise
AD8065/AD8066
Rev. E | Page 11 of 28
02916-E-022
G = +1
50mV/DIV 20ns/DIV
Figure 22. Small Signal Transient Response 5 V Supply (See Figure 52)
02916-E-023
G = +1
2V/DIV 80ns/DIV
V
S
= ±12V
V
OUT
= 2V p-p
V
OUT
= 4V p-p
V
OUT
= 10V p-p
Figure 23. Large Signal Transient Response (See Figure 42)
02916-E-024
1.5V/DIV 100ns/DIV
–IN OUT
G = –1
V
S
= ±5V
Figure 24. Output Overdrive Recovery (See Figure 44)
02916-E-025
G = +1
50mV/DIV 20ns/DIV
C
L
= 20pF
C
L
= 5pF
Figure 25. Small Signal Transient Response ±5 V (See Figure 42)
02916-E-026
5µs
G = +2
2V/DIV 80ns/DIV
V
S
= ±12V
V
OUT
= 10V p-p
V
OUT
= 2V p-p
Figure 26. Large Signal Transient Response (See Figure 43)
02916-E-027
1.5V/DIV 100ns/DIV
IN
OUT
G = +1
V
S
= ±5V
Figure 27. Input Overdrive Recovery (See Figure 42)
AD8065/AD8066
Rev. E | Page 12 of 28
02916-E-028
t = 0
64
µ
s/DIV
2mV/DIV
+0.1%
–0.1%
V
IN
= 140mV/DIV
V
OUT
– 2V
IN
Figure 28. Long-Term Settling Time (See Figure 49)
–30
–25
–20
–15
–10
–5
0
INPUT BIAS CURRENT (pA)
45 5525 35 65 75 85
TEMPERATURE (°C)
02916-E-029
–I
b
+I
b
Figure 29. Input Bias Current vs. Temperature
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
OFFSET VOLTAGE (mV)
–14 –10–12 –8–6–4 0 8–2 2 4 6 10 12 14
COMMON-MODE VOLTAGE (V)
02916-E-030
V
S
= ±12V
V
S
= ±5V
V
S
= +5V
Figure 30. Input Offset Voltage vs. Common-Mode Voltage
02916-E-031
+0.1%
2mV/DIV 10ns/DIV
–0.1% t = 0
V
OUT
– 2V
IN
V
IN
= 500mV/DIV
Figure 31. 0.1% Short-Term Settling Time (See Figure 49)
02916-E-032
0
I
b
(
µ
A)
36
30
24
18
12
6
–5
–15
–25
–30
0
I
b
(pA)
–12 8–2–10 0
–8 2–6 4–4 6
COMMON-MODEVOLTAGE (V)
10 12
42
–Ib
+Ib
–Ib
+Ib
FET INPUT STAGE BJT INPUT STAGE
–20
–10
5
10
Figure 32. Input Bias Current vs. Common-Mode Voltage Range
(see the Input and Output Overload Behavior section)
02916-E-033
INPUT OFFSET VOLTAGE (mV)
35
15
0
–2.0 2.0–1.5 –1.0 –0.5 0 0.5 1.0 1.5
30
20
10
5
40
25
N = 299
SD = 0.388
MEAN = –0.069
Figure 33. Input Offset Voltage
AD8065/AD8066
Rev. E | Page 13 of 28
–100
–90
–80
–70
–60
–50
–40
–30
CMRR (dB)
FREQUENCY (MHz)
0.1 101 100
02916-E-034
V
S
= ±12V
V
S
= ±5V
Figure 34. CMRR vs. Frequency (See Figure 46)
0
0.05
0.10
0.15
0.20
0.25
0.30
OUTPUT SATURATION VOLTAGE (V)
I
LOAD
(mA)
100203040
02916-E-035
V
CC
– V
OH
V
OL
– V
EE
Figure 35. Output Saturation Voltage vs. Output Load Current
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
0.01 0.1 1 10 100 1000
FREQUENCY (MHz)
02916-E-036
–PSRR
+PSRR
Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50)
0
0.01
0.1
1
10
100
OUTPUT IMPEDANCE (
Ω
)
10k 100k100 1k 1M 10M 100M
FREQUENCY (Hz)
02916-E-037
G = +2
G = +1
Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47)
30
40
50
60
70
80
OUTPUT SATURATION VOLTAGE (mV)
45 5525 35 65 75 85
TEMPERATURE (°C)
02916-E-038
V
CC
– V
OH
V
OL
– V
EE
Figure 38. Output Saturation Voltage vs. Temperature
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
CROSSTALK (dB)
FREQUENCY (MHz)
0.1 101 100
02916-E-039
V
IN
= 2V p-p
G = +1
B TO A
A TO B
Figure 39. Crosstalk vs. Frequency (See Figure 51)
AD8065/AD8066
Rev. E | Page 14 of 28
6.25
6.30
6.35
6.40
6.45
6.50
6.55
6.60
SUPPLY CURRENT (mA)
020–40 –20 40 60 80
TEMPERATURE (°C)
02916-E-040
V
S
= ±12V
V
S
= +5V
V
S
= ±5V
Figure 40. Quiescent Supply Current vs. Temperature for Various Supply Voltages
80
85
90
95
100
105
110
115
120
125
OPEN-LOOP GAIN (dB)
I
LOAD
(mA)
100203040
02916-E-041
V
S
= ±12V
V
S
= +5V
V
S
= ±5V
Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages
AD8065/AD8066
Rev. E | Page 15 of 28
TEST CIRCUITS
SOIC-8 Pinout
AD8065
+V
CC
V
IN
–V
EE
4.7µF
0.1µF
24.9Ω
R
SNUB
0.1µF
4.7µF
C
LOAD
FET PROBE
49.9Ω1kΩ
02916-E-042
Figure 42. G = +1
02916-E-043
AD8065
+VCC
VIN
–VEE
4.7µF
0.1µF
2.2pF
RSNUB
0.1µF
4.7µF
49.9Ω
499Ω499Ω
249ΩCLOAD
FET PROBE
1kΩ
Figure 43. G = +2
V
IN
49.9Ω
AD8065
+V
CC
–V
EE
4.7µF
0.1µF
2.2pF
0.1µF
4.7µF
499Ω499Ω
249Ω
FET PROBE
1kΩ
02916-E-044
Figure 44. G = −1
AD8065
+V
CC
–V
EE
4.7µF
0.1µF
24.9Ω
0.1µF
4.7µF
NETWORK ANALYZER S22
02916-E-045
Figure 45. Output Impedance G = +1
AD8065/AD8066
Rev. E | Page 16 of 28
V
IN
49.9Ω
AD8065
+V
CC
–V
EE
4.7µF
0.1µF
0.1µF
4.7µF
499Ω499Ω
FET PROBE
1kΩ
499Ω499Ω
02916-E-046
Figure 46. CMRR
AD8065
+V
CC
–V
EE
0.1µF
4.7µF
499Ω499Ω
249ΩNETWORK ANALYZER
S22
4.7µF
0.1µF
02916-E-047
Figure 47. Output Impedance G = +2
AD8065
–V
EE
24.9Ω
0.1µF
4.7µF
+V
CC
FET PROBE
1kΩ
V
IN
1V p-p
49.9Ω
02916-E-048
Figure 48. Positive PSRR
AD8065
+V
CC
V
IN
–V
EE
4.7µF
0.1µF
2.2pF
976Ω
0.1µF
4.7µF
499Ω499Ω
249Ω
TO SCOPE
49.9Ω49.9Ω
02916-E-049
Figure 49. Settling Time
AD8065/AD8066
Rev. E | Page 17 of 28
AD8065
+V
CC
–V
EE
4.7µF
0.1µF
FET PROBE
49.9Ω
24.9Ω
V
IN
1V p-p
1kΩ
02916-E-050
Figure 50. Negative PSRR
24.9Ω
49.9Ω
24.9Ω
1kΩ
0.1µF
4.7µF
V
IN
+5V
–5V
1kΩ
DRIVE SIDE
RECEIVE SIDE
AD8066
AD8066
0.1µF
4.7µF
FET PROBE
02916-E-051
Figure 51. Crosstalk—AD8066
249Ω
0.1µF
V
IN
1.5V
1.5V
1.5V
4.7µF
499Ω
499Ω
5V
49.9Ω
2.2pF
1kΩ
FET PROBE
AD8065
02916-E-052
Figure 52. Single Supply
AD8065/AD8066
Rev. E | Page 18 of 28
THEORY OF OPERATION
The AD8065/AD8066 are voltage feedback operational
amplifiers that combine a laser-trimmed JFET input stage with
the Analog Devices eXtra Fast Complementary Bipolar (XFCB)
process, resulting in an outstanding combination of precision
and speed. The supply voltage range is from 5 V to 24 V. The
amplifiers feature a patented rail-to-rail output stage capable of
driving within 0.5 V of either power supply while sourcing or
sinking up to 30 mA. Also featured is a single-supply input stage
that handles common-mode signals from below the negative
supply to within 3 V of the positive rail. Operation beyond the
JFET input range is possible because of an auxiliary bipolar
input stage that functions with input voltages up to the positive
supply. The amplifiers operate as if they have a rail-to-rail input
and exhibit no phase reversal behavior for common-mode
voltages within the power supply.
With voltage noise of 7 nV/√Hz and −88 dBc distortion for
1 MHz 2 V p-p signals, the AD8065/AD8066 are a great choice
for high resolution data acquisition systems. Their low noise,
sub-pA input current, precision offset, and high speed make
them superb preamps for fast photodiode applications. The
speed and output drive capability of the AD8065/AD8066 also
make them useful in video applications.
CLOSED-LOOP FREQUENCY RESPONSE
The AD8065/AD8066 are classic voltage feedback amplifiers
with an open-loop frequency response that can be approx-
imated as the integrator response shown in Figure 53. Basic
closed-loop frequency response for inverting and noninverting
configurations can be derived from the schematics shown.
NONINVERTING CLOSED-LOOP FREQUENCY
RESPONSE
Solving for the transfer function
(
)
()
G
crossover
G
F
F
G
crossover
I
O
RfsRR
RRf
V
V
××π++
+
×
π
=2
2
where fcrossover is the frequency where the amplifier’s open-loop
gain equals 0 db
At dc
G
G
F
I
O
R
RR
V
V
+
=
Closed-loop −3 dB frequency
G
F
G
crossover
3dB RR
R
ff +
×=
−
INVERTING CLOSED-LOOP FREQUENCY
RESPONSE
()
G
crossover
G
F
F
crossover
I
O
RfRRs
Rf
V
V
××π++
×
×
π
−
=2
2
At dc
G
F
I
O
R
R
V
V−=
Closed-loop −3 dB frequency
G
F
G
crossover
3dB RR
R
ff +
×=
−
R
F
A
V
O
R
G
V
I
V
E
FREQUENCY (MHz)
80
60
0.01 100
OPEN-LOOP GAIN (A) (dB)
0.1 101
40
20
0
f
crossover
= 65MHz
A = (2π×
f
crossover
)/s
R
F
V
E
A
V
O
R
G
V
I
02916-E-053
Figure 53. Open-Loop Gain vs. Frequency and Basic Connections
AD8065/AD8066
Rev. E | Page 19 of 28
The closed-loop bandwidth is inversely proportional to the
noise gain of the op amp circuit, (RF + RG )/RG. This simple
model is accurate for noise gains above 2. The actual bandwidth
of circuits with noise gains at or below 2 will be higher than
those predicted with this model due to the influence of other
poles in the frequency response of the real op amp.
V
O
R
F
A
R
G
V
I
I
b
–
R
S
I
b
+
+V
OS
–
02916-E-054
Figure 54. Voltage Feedback Amplifier DC Errors
Figure 54 shows a voltage feedback amplifier’s dc errors. For
both inverting and noninverting configurations
()
⎟
⎠
⎞
⎜
⎝
⎛+
+×−
⎟
⎠
⎞
⎜
⎝
⎛+
×= −+
G
F
G
OS
F
b
G
F
G
S
b
OR
RR
VRI
R
RR
RIerrorV
The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG
(though with the AD8065 input currents at less than 20 pA over
temperature, this is likely not a concern). To include common-
mode and power supply rejection effects, total VOS can be
modeled as
CMR
V
PSR
V
VV CMS
nom
OSOS
ΔΔ ++=
nom
OS
V is the offset voltage specified at nominal conditions,
∆VS is the change in power supply from nominal conditions,
PSR is the power supply rejection, ∆VCM is the change in
common-mode voltage from nominal conditions, and CMR
is the common-mode rejection.
WIDEBAND OPERATION
Figure 42 through Figure 44 show the circuits used for
wideband characterization for gains of +1, +2, and −1. Source
impedance at the summing junction (RF || RG) will form a pole
in the amplifier’s loop response with the amplifier’s input
capacitance of 6.6 pF. This can cause peaking and ringing if the
time constant formed is too low. Feedback resistances of 300 Ω
to 1 kΩ are recommended, since they will not unduly load
down the amplifier and the time constant formed will not be
too low. Peaking in the frequency response can be compensated
for with a small capacitor (CF) in parallel with the feedback
resistor, as illustrated in Figure 12. This shows the effect of
different feedback capacitances on the peaking and bandwidth
for a noninverting G = +2 amplifier.
For the best settling times and the best distortion, the
impedances at the AD8065/AD8066 input terminals should be
matched. This minimizes nonlinear common-mode capacitive
effects that can degrade ac performance.
Actual distortion performance depends on a number of
variables:
• The closed-loop gain of the application
• Whether it is inverting or noninverting
• Amplifier loading
• Signal frequency and amplitude
• Board layout
Also see Figure 16 to Figure 20. The lowest distortion will be
obtained with the AD8065 used in low gain inverting appli-
cations, since this eliminates common-mode effects. Higher
closed-loop gains result in worse distortion performance.
INPUT PROTECTION
The inputs of the AD8065/AD8066 are protected with back-to-
back diodes between the input terminals as well as ESD diodes
to either power supply. This results in an input stage with
picoamps of input current that can withstand up to 1500 V ESD
events (human body model) with no degradation.
Excessive power dissipation through the protection devices will
destroy or degrade the performance of the amplifier. Differ-
ential voltages greater than 0.7 V will result in an input current
of approximately (|V+ − V−| 0.7 V)/RI, where RI is the resistance
in series with the inputs. For input voltages beyond the positive
supply, the input current will be approximately (VI − VCC −
0.7)/RI. Beyond the negative supply, the input current will be
about (VI − VEE + 0.7)/RI. If the inputs of the amplifier are to be
subjected to sustained differential voltages greater than 0.7 V or
to input voltages beyond the amplifier power supply, input
current should be limited to 30 mA by an appropriately sized
input resistor (RI) as shown in Figure 55.
R
I
V
I
V
O
AD8065
R
I
>(| V+–V
–
| – 0.7V)
30mA
FOR LARGE | V
+
–V
–
|
R
I
>(V
I
–V
EE
– 0.7V)
30mA
R
I
>(V
I
–V
EE
+ 0.7V)
30mA
FOR V
I
BEYOND
SUPPLY VOLTAGES
02916-E-055
Figure 55. Current Limiting Resistor
AD8065/AD8066
Rev. E | Page 20 of 28
THERMAL CONSIDERATIONS
With 24 V power supplies and 6.5 mA quiescent current, the
AD8065 dissipates 156 mW with no load. The AD8066
dissipates 312 mW. This can lead to noticeable thermal effects,
especially in the small SOT-23-5 (thermal resistance of
160°C/W). VOS temperature drift is trimmed to guarantee a
maximum drift of 17 µV/°C, so it can change up to 0.425 mV
due to warm-up effects for an AD8065/AD8066 in a SOT-23-5
package on 24 V.
Ib increases by a factor of 1.7 for every 10°C rise in temperature.
Ib will be close to 5 times higher at 24 V supplies as opposed to a
single 5 V supply.
Heavy loads will increase power dissipation and raise the chip
junction temperature as described in the Maximum Power
Dissipation section. Care should be taken to not exceed the
rated power dissipation of the package.
INPUT AND OUTPUT OVERLOAD BEHAVIOR
The AD8065/AD8066 have internal circuitry to guard against
phase reversal due to overdriving the input stage. A simplified
schematic of the input stage, including the input-protection
diodes and antiphase reversal circuitry, is shown in Figure 56.
The circuit is arranged such that when the input common-
mode voltage exceeds a certain threshold, the input JFET pair’s
bias current will turn OFF, and the bias current of an auxiliary
NPN pair will turn ON, taking over control of the amplifier.
When the input common-mode voltage returns to a viable
operating value, the FET stage turns back ON, the NPN stage
turns OFF, and normal operation resumes.
The NPN pair can sustain operation with the input voltage up
to the positive supply, so this is a pseudo rail-to-rail input stage.
For operation beyond the FET stage’s common-mode limit, the
amplifier’s VOS will change to the NPN pair’s offset (mean of
160 µV, standard deviation of 820 µV), and Ib will increase to the
NPN pair’s base current up to 45 µA (see Figure 32).
Switchback, or recovery time, is about 100 ns, see Figure 27.
The output transistors of the rail-to-rail output stage have
circuitry to limit the extent of their saturation when the output
is overdriven. This helps output recovery time. Output recovery
from a 0.5 V output overdrive on a ±5 V supply is shown in
Figure 24.
AD8065/AD8066
Rev. E | Page 21 of 28
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
POWER SUPPLY BYPASSING
Power supply pins are actually inputs and care must be taken so
that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise.
Decoupling schemes are designed to minimize the bypassing
impedance at all frequencies with a parallel combination of
capacitors. 0.1 µF (X7R or NPO) chip capacitors are critical
and should be as close as possible to the amplifier package.
The 4.7 µF tantalum capacitor is less critical for high frequency
bypassing, and, in most cases, only one is needed per board, at
the supply inputs.
GROUNDING
A ground plane layer is important in densely packed PC boards
to spread the current minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and therefore the high
frequency impedance of the path. High speed currents in an
inductive ground return will create an unwanted voltage noise.
V
THRESHOLD
VBIAS
S
V
P
TO REST OF AMP
V
CC
S
V
N
R1
Q2 Q5
Q3
Q1 Q6
Q7
Q4
R5
D1 R6
R3
R4
R2 R8
R7
D2
D3 D4
–V
EE
I
T1
I
T2
02916-E-056
Figure 56. Simplified Input Stage
AD8065/AD8066
Rev. E | Page 22 of 28
The length of the high frequency bypass capacitor leads is most
critical. A parasitic inductance in the bypass grounding will
work against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents flow from the supplies
as well, the ground for the load impedance should be at the
same physical location as the bypass capacitor grounds. For the
larger value capacitors, which are effective at lower frequencies,
the current return path distance is less critical.
LEAKAGE CURRENTS
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the AD8065/AD8066. Any voltage
differential between the inputs and nearby runs will set up
leakage currents through the PC board insulator, for example,
1 V/100 GΩ = 10 pA. Similarly, any contaminants on the board
can create significant leakage (skin oils are a common problem).
To significantly reduce leakage, put a guard ring (shield) around
the inputs and input leads that are driven to the same voltage
potential as the inputs. This way there is no voltage potential
between the inputs and surrounding area to set up any leakage
currents. For the guard ring to be completely effective, it must
be driven by a relatively low impedance source and should
completely surround the input leads on all sides, above and
below, using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard ring
will help to reduce the absorption. Also, low absorption
materials, such as Teflon® or ceramic, could be necessary in
some instances.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and
ground. A few pF of capacitance will reduce the input imped-
ance at high frequencies, in turn increasing the amplifier’s gain,
causing peaking of the frequency response or even oscillations,
if severe enough. It is recommended that the external passive
components connected to the input pins be placed as close as
possible to the inputs to avoid parasitic capacitance. The ground
and power planes must be kept at a small distance from the
input pins on all layers of the board.
OUTPUT CAPACITANCE
To a lesser extent, parasitic capacitances on the output can cause
peaking and ringing of the frequency response. There are two
methods to effectively minimize their effect.
• As shown in Figure 57, put a small value resistor (RS) in
series with the output to isolate the load capacitor from the
amp’s output stage. A good value to choose is 20 Ω (see
Figure 10).
• Increase the phase margin with higher noise gains or add a
pole with a parallel resistor and capacitor from −IN to the
output.
R
S
= 20Ω
V
I
AD8065
C
L
V
O
02916-E-057
Figure 57. Output Isolation Resistor
RSH = 1011Ω
VO
RF
CF
CM
RF
CM
CD
CF+C
S
CS
VB
IPHOTO
02916-E-058
Figure 58. Wideband Photodiode Preamp
AD8065/AD8066
Rev. E | Page 23 of 28
INPUT-TO-OUTPUT COUPLING
In order to minimize capacitive coupling between the inputs
and output, the output signal traces should not be parallel with
the inputs.
WIDEBAND PHOTODIODE PREAMP
Figure 58 shows an I/V converter with an electrical model of a
photodiode. The basic transfer function is where
FF
F
PHOTO
OUT RsC
RI
V+
×
=1
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF set the signal bandwidth.
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the amplifier’s summing junction, including CS
and the amplifier input capacitance. RF and the total capacitance
produce a pole in the amplifier’s loop transmission that can
result in peaking and instability. Adding CF creates a 0 in the
loop transmission, which compensates for the pole’s effect and
reduces the signal bandwidth. It can be shown that the signal
bandwidth resulting in a 45° phase margin (f(45)) is defined by
the expression
()
S
F
CR
CR
f
f××π
=2
45
where fCR is the amplifier crossover frequency, RF is the feedback
resistor, and CS is the total capacitance at the amplifier summing
junction (amplifier + photodiode + board parasitics).
The value of CF that produces f(45) can be shown to be
CRF
S
FfR
C
C××π
=2
The frequency response in this case will show about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half will result in a flat frequency response, with
about 5% transient overshoot.
The preamp’s output noise over frequency is shown in Figure 59.
FREQUENCY (Hz)
VOLTAGE NOISE (nV/ Hz)
2πR
F
C
F
2πR
F
(C
F
+C
S
+C
M
+2C
D
)
(C
S
+C
M
+2C
D
+C
F
)/C
F
R
F
NOISE
VEN (C
F
+C
S
+C
M
+ 2C
D
)/C
F
f
3
f
2
f
3
=
VEN
f
1
f
2
=
f
1
=1
1
f
CR
NOISE DUE TO AMPLIFIER
02916-E-059
Figure 59. Photodiode Voltage Noise Contributions
The pole in the loop transmission translates to a 0 in the
amplifier’s noise gain, leading to an amplification of the input
voltage noise over frequency. The loop transmission 0
introduced by CF limits the amplification. The noise gain
bandwidth extends past the preamp signal bandwidth and is
eventually rolled off by the decreasing loop gain of the
amplifier. Keeping the input terminal impedances matched is
recommended to eliminate common-mode noise peaking
effects, which will add to the output noise.
Integrating the square of the output voltage noise spectral
density over frequency and then taking the square root allows
users to obtain the total rms output noise of the preamp. Table 5
summarizes approximations for the amplifier and feedback and
source resistances. Noise components for an example preamp
with RF = 50 kΩ, CS = 15 pF, and CF = 2 pF (bandwidth of about
1.6 MHz) are also listed.
Table 5. RMS Noise Contributions of Photodiode Preamp
Contributor Expression
RMS Noise with RF = 50 kΩ,
CS = 15 pF, CS = 15 pF
RF (×2) 57142 .fRkT 2
F×××× 64.5 µV
Amp to f1 1
fVEN × 2.4 µV
Amp (f2 – f1)
12
F
DFM
Sff
C
CCCC
VEN −×
+++
×2
31 µV
Amp to (past f2) 57.1
2××
+++
×3
F
FDM
Sf
C
CCCC
VEN
260 µV
270 µV (Total)
AD8065/AD8066
Rev. E | Page 24 of 28
V
CC
V
EE
1/2
AD8066
4.7µF
0.1µF
R
S1
4.7µF
0.1µF
V
N
2.2pF
500Ω
R2
V
P
1/2
AD8066
4.7µF
0.1µF
4.7µF
0.1µF
AD8065
4.7µF
0.1µF
4.7µF
0.1µF
V
O
R
G
V
CC
V
EE
V
CC
V
EE
500Ω
R4
R
S2
500Ω
R1
500Ω
R3
R
F
= 500Ω
2.2pF
R
F
= 500Ω
02916-E-060
Figure 60. High Speed Instrumentation Amplifier
HIGH SPEED JFET INPUT INSTRUMENTATION
AMPLIFIER
Figure 60 shows an example of a high speed instrumentation
amplifier with high input impedance using the
AD8065/AD8066. The dc transfer function is
()
⎟
⎠
⎞
⎜
⎝
⎛+
−=
G
PN
OUT R
VVV 10001
For G = +1, it is recommended that the feedback resistors for
the two preamps be set to a low value (for instance 50 Ω for 50
Ω source impedance). The bandwidth for G = +1 will be 50
MHz. For higher gains, the bandwidth will be set by the preamp,
equaling
(
)
(
)
F
GCR
3dB RRfInamp ××=
−2/
Common-mode rejection of the inamp will be primarily
determined by the match of the resistor ratios R1:R2 to R3:R4. It
can be estimated
()
()
211
21
δδ+
δ−δ
=
CM
O
V
V
The summing junction impedance for the preamps is equal to
RF || 0.5(RG). This is the value to be used for matching purposes.
VIDEO BUFFER
The output current capability and speed of the AD8065 make it
useful as a video buffer, shown in Figure 61.
The G = +2 configuration compensates for the voltage division
of the signal due to the signal termination. This buffer
maintains 0.1 dB flatness for signals up to 7 MHz, from low
amplitudes up to 2 V p-p (Figure 7). Differential gain and phase
have been measured to be 0.02% and 0.028° at ±5 V supplies.
+VS
–VS
4.7µF
0.1µF
2.2pF
499Ω
249Ω
75Ω
499Ω
VIAD8065
4.7µF
0.1µF75ΩVO
+
–+
–
02916-E-061
Figure 61. Video Buffer
AD8065/AD8066
Rev. E | Page 25 of 28
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARIT
Y
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 62. 8-Lead Standard Small Outline Package Narrow Body [SOIC]
(R-8)
Dimensions shown in millimeters (inches)
PIN 1
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
1
3
4 5
2
0.22
0.08 10°
5°
0°
0.50
0.30
0.15 MAX SEATING
PLANE
1.45 MAX
1.30
1.15
0.90
2.90 BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 63. 5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
0.80
0.60
0.40
8°
0°
4
85
4.90
BSC
PIN 1 0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 64. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD8065/AD8066
Rev. E | Page 26 of 28
ORDERING GUIDE
Model Temperature Range Package Description Package Outline Branding
AD8065AR −40°C to +85°C 8-Lead SOIC R-8
AD8065AR-REEL −40°C to +85°C 8-Lead SOIC R-8
AD8065AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8
AD8065ART-REEL −40°C to +85°C 5-Lead SOT-23 RT-5 HRA
AD8065ART-R2 −40°C to +85°C 5-Lead SOT-23 RT-5 HRA
AD8065ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RT-5 HRA
AD8066AR −40°C to +85°C 8-Lead SOIC R-8
AD8066AR-REEL −40°C to +85°C 8-Lead SOIC R-8
AD8066AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8
AD8066ARZ1 −40°C to +85°C 8-Lead SOIC R-8
AD8066ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8
AD8066ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8
AD8066ARM −40°C to +85°C 8-Lead MSOP RM-8 HIB
AD8066ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 HIB
AD8066ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 HIB
1 Z = Pb-free part.
AD8065/AD8066
Rev. E | Page 27 of 28
NOTES
AD8065/AD8066
Rev. E | Page 28 of 28
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02916-0-2/04(E)
