PIC18F6525/6621/8525/8621 Data Sheet 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D 2005 Microchip Technology Inc. DS39612B Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39612B-page ii 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D High Performance RISC CPU: * * * * * * * * External Memory Interface (PIC18F8525/8621 Devices Only): Linear program memory addressing to 64 Kbytes Linear data memory addressing to 4 Kbytes 1 Kbyte of data EEPROM Up to 10 MIPs operation: - DC - 40 MHz osc./clock input - 4 MHz - 10 MHz osc./clock input with PLL active 16-bit wide instructions, 8-bit wide data path Priority levels for interrupts 31-level, software accessible hardware stack 8 x 8 Single-cycle Hardware Multiplier * Address capability of up to 2 Mbytes * 16-bit interface Analog Features: * 10-bit, up to 16-channel Analog-to-Digital Converter (A/D): - Auto-Acquisition - Conversion available during Sleep * Programmable 16-level Low-Voltage Detection (LVD) module: - Supports interrupt on Low-Voltage Detection * Programmable Brown-out Reset (BOR) * Dual analog comparators: - Programmable input/output configuration Peripheral Features: * * * * * * * * * * * * * High current sink/source 25 mA/25 mA Four external interrupt pins Timer0 module: 8-bit/16-bit timer/counter Timer1 module: 16-bit timer/counter Timer2 module: 8-bit timer/counter Timer3 module: 16-bit timer/counter Timer4 module: 8-bit timer/counter Secondary oscillator clock option - Timer1/Timer3 Two Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max. resolution 6.25 ns (TCY/16) - Compare is 16-bit, max. resolution 100 ns (TCY) - PWM output: 1 to 10-bit PWM resolution Three Enhanced Capture/Compare/PWM (ECCP) modules: - Same Capture/Compare features as CCP - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown on external event - Auto-Restart Master Synchronous Serial Port (MSSP) module with two modes of operation: - 2/3/4-wire SPITM (supports all 4 SPI modes) - I2CTM Master and Slave mode Two Enhanced USART modules: - Supports RS-485, RS-232 and LIN 1.2 - Auto-Wake-up on Start bit - Auto-Baud Rate Detect Parallel Slave Port (PSP) module Program Memory Device Special Microcontroller Features: * 100,000 erase/write cycle Enhanced Flash program memory typical * 1,000,000 erase/write cycle Data EEPROM memory typical * 1 second programming time * Flash/Data EEPROM Retention: > 100 years * Self-reprogrammable under software control * Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation * Programmable code protection * Power-saving Sleep mode * Selectable oscillator options including: - 4x Phase Lock Loop (PLL) - of primary oscillator - Secondary Oscillator (32 kHz) clock input * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * MPLAB(R) In-Circuit Debug (ICD 2) via two pins CMOS Technology: * * * * Data Memory # Single-Word SRAM EEPROM I/O Bytes Instructions (bytes) (bytes) 10-bit A/D (ch) Low power, high-speed Flash technology Fully static design Wide operating voltage range (2.0V to 5.5V) Industrial and Extended temperature ranges CCP/ MSSP/SPITM/ Timers ECCP PWM Master I2CTM EUSART 8-bit/16-bit EMI PIC18F6525 48K 24576 3840 1024 53 12 2/3 14 Y 2 2/3 N PIC18F6621 64K 32768 3840 1024 53 12 2/3 14 Y 2 2/3 N PIC18F8525 48K 24576 3840 1024 70 16 2/3 14 Y 2 2/3 Y PIC18F8621 64K 32768 3840 1024 70 16 2/3 14 Y 2 2/3 Y 2005 Microchip Technology Inc. DS39612B-page 1 PIC18F6525/6621/8525/8621 Pin Diagrams RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RD3/PSP3 RD2/PSP2 RD1/PSP1 VSS VDD RE7/ECCP2(1)/P2A(1) RD0/PSP0 RE6/P1B RE5/P1C RE4/P3B RE3/P3C RE2/CS/P2B 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR/P2C RE0/RD/P2D 1 48 47 46 45 RF4/AN9 2 3 4 5 6 7 8 9 10 11 12 13 14 RF3/AN8 RF2/AN7/C1OUT 15 16 RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D MCLR/VPP/RG5(2) RG4/CCP5/P1D VSS VDD RF7/SS RF6/AN11 RF5/AN10/CVREF 44 43 42 41 40 PIC18F6525 PIC18F6621 39 38 37 36 35 34 33 RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/ECCP1/P1A Note 1: 2: DS39612B-page 2 RC7/RX1/DT1 RC6/TX1/CK1 RC0/T1OSO/T13CKI RA4/T0CKI RC1/T1OSI/ECCP2(1)/P2A(1) VDD RA5/AN4/LVDIN VSS RA0/AN0 RA1/AN1 RA2/AN2/VREF- AVSS RA3/AN3/VREF+ AVDD RF0/AN5 RF1/AN6/C2OUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set. RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Pin Diagrams (Cont.'d) RJ1/OE RJ0/ALE RD7/AD7/PSP7 RD6/AD6/PSP6 RD5/AD5/PSP5 RD4/AD4/PSP4 RD3/AD3/PSP3 RD2/AD2/PSP2 RD1/AD1/PSP1 VSS VDD RD0/AD0/PSP0 RE7/AD15/ECCP2(1)/P2A(1) RE6/AD14/P1B(2) RE5/AD13/P1C(2) RE4/AD12/P3B(2) RE2/AD10/CS/P2B RE3/AD11/P3C(2) RH0/A16 RH1/A17 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/A18 RH3/A19 RE1/AD9/WR/P2C RE0/AD8/RD/P2D RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D MCLR/VPP/RG5(3) RG4/CCP5/P1D VSS VDD RF7/SS RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT RH7/AN15/P1B(2) RH6/AN14/P1C(2) 1 60 2 59 58 57 56 55 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 53 52 51 50 PIC18F8525 PIC18F8621 49 48 47 46 45 44 43 42 41 17 18 19 20 RJ2/WRL RJ3/WRH RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3/INT3/ECCP2(1)/P2A(1) RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/ECCP1/P1A RJ7/UB RJ6/LB Note 1: 2: 3: RJ5/CE RJ4/BA0 RC7/RX1/DT1 RC6/TX1/CK1 RC0/T1OSO/T13CKI RA4/T0CKI RC1/T1OSI/ECCP2(1)/P2A(1) RA5/AN4/LVDIN VDD VSS RA0/AN0 RA1/AN1 RA2/AN2/VREF- AVSS RA3/AN3/VREF+ AVDD RF0/AN5 RF1/AN6/C2OUT RH4/AN12/P3C(2) RH5/AN13/P3B(2) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is configured in Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes. P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is not set. RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. DS39612B-page 3 PIC18F6525/6621/8525/8621 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 21 3.0 Reset .......................................................................................................................................................................................... 29 4.0 Memory Organization ................................................................................................................................................................. 39 5.0 Flash Program Memory .............................................................................................................................................................. 61 6.0 External Memory Interface ......................................................................................................................................................... 71 7.0 Data EEPROM Memory ............................................................................................................................................................. 79 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 85 9.0 Interrupts .................................................................................................................................................................................... 87 10.0 I/O Ports ................................................................................................................................................................................... 103 11.0 Timer0 Module ......................................................................................................................................................................... 131 12.0 Timer1 Module ......................................................................................................................................................................... 135 13.0 Timer2 Module ......................................................................................................................................................................... 141 14.0 Timer3 Module ......................................................................................................................................................................... 143 15.0 Timer4 Module ......................................................................................................................................................................... 147 16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 149 17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 157 18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 173 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 213 20.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 233 21.0 Comparator Module.................................................................................................................................................................. 243 22.0 Comparator Voltage Reference Module ................................................................................................................................... 249 23.0 Low-Voltage Detect .................................................................................................................................................................. 253 24.0 Special Features of the CPU .................................................................................................................................................... 259 25.0 Instruction Set Summary .......................................................................................................................................................... 275 26.0 Development Support............................................................................................................................................................... 317 27.0 Electrical Characteristics .......................................................................................................................................................... 323 28.0 DC and AC Characteristics Graphs And Tables ...................................................................................................................... 357 29.0 Packaging Information.............................................................................................................................................................. 373 Appendix A: Revision History............................................................................................................................................................. 377 Appendix B: Device Differences......................................................................................................................................................... 377 Appendix C: Conversion Considerations ........................................................................................................................................... 378 Appendix D: Migration From Mid-Range to Enhanced Devices......................................................................................................... 378 Appendix E: Migration From High-End to Enhanced Devices............................................................................................................ 379 Index .................................................................................................................................................................................................. 381 On-Line Support................................................................................................................................................................................. 391 Systems Information and Upgrade Hot Line ...................................................................................................................................... 391 Reader Response .............................................................................................................................................................................. 392 PIC18F6525/6621/8525/8621 Product Identification System ............................................................................................................ 393 DS39612B-page 4 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. 2005 Microchip Technology Inc. DS39612B-page 5 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 6 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: * * * * PIC18F6525 PIC18F6621 PIC18F8525 PIC18F8621 This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high-endurance Enhanced Flash program memory. The PIC18F6525/6621/8525/8621 family also provides an enhanced range of program memory options and versatile analog features that make it ideal for complex, high performance applications. 1.1 1.1.1 Key Features EXPANDED MEMORY The PIC18F6525/6621/8525/8621 family provides ample room for application code and includes members with 48 Kbytes or 64 Kbytes of code space. Other memory features are: * Data RAM and Data EEPROM: The PIC18F6525/ 6621/8525/8621 family also provides plenty of room for application data. The devices have 3840 bytes of data RAM, as well as 1024 bytes of data EEPROM for long term retention of nonvolatile data. * Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. 1.1.2 EXTERNAL MEMORY INTERFACE In the unlikely event that 64 Kbytes of program memory is inadequate for an application, the PIC18F8525/8621 members of the family also implement an external memory interface. This allows the controller's internal program counter to address a memory space of up to 2 MBytes, permitting a level of data access that few 8-bit devices can claim. 2005 Microchip Technology Inc. With the addition of new operating modes, the external memory interface offers many new options, including: * Operating the microcontroller entirely from external memory * Using combinations of on-chip and external memory, up to the 2-Mbyte limit * Using external Flash memory for reprogrammable application code or large data tables * Using external RAM devices for storing large amounts of variable data 1.1.3 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between the 64-pin members, between the 80-pin members, or even Jumping From 64-pin To 80-pin Devices. 1.1.4 OTHER SPECIAL FEATURES * Communications: The PIC18F6525/6621/8525/ 8621 family incorporates a range of serial communication peripherals, including 2 independent Enhanced USARTs and a Master SSP module capable of both SPI and I2C (Master and Slave) modes of operation. Also, for PIC18F6525/6621/8525/8621 devices, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor to processor communications. * CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and three Enhanced CCP (ECCP) modules to maximize flexibility in control applications. Up to four different time bases may be used to perform several different operations at once. Each of the three ECCPs offer up to four PWM outputs, allowing for a total of 12 PWMs. The ECCPs also offer many beneficial features, including polarity selection, Programmable Dead Time, Auto-Shutdown and Restart and Half-Bridge and Full-Bridge Output modes. * Analog Features: All devices in the family feature 10-bit A/D converters with up to 16 input channels, as well as the ability to perform conversions during Sleep mode and auto-acquisition conversions. Also included are dual analog comparators with programmable input and output configuration, a programmable Low-Voltage Detect module and a Programmable Brown-out Reset module. * Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected boot block at the top of program memory, it becomes possible to create an application that can update itself in the field. DS39612B-page 7 PIC18F6525/6621/8525/8621 1.2 Details on Individual Family Members The PIC18F6525/6621/8525/8621 devices are available in 64-pin (PIC18F6525/6621) and 80-pin (PIC18F8525/8621) packages. They are differentiated from each other in four ways: 1. 2. Flash program memory (48 Kbytes for PIC18F6525/8525 devices; 64 Kbytes for PIC18F6621/8621 devices). A/D channels (12 for PIC18F6525/6621 devices; 16 for PIC18F8525/8621 devices). TABLE 1-1: 3. I/O ports (7 on PIC18F6525/6621 devices; 9 on PIC18F8525/8621 devices). External program memory interface (present only on PIC18F8525/8621 devices) 4. All other features for devices in the PIC18F6525/6621/ 8525/8621 family are identical. These are summarized in Table 1-1. Block diagrams of the PIC18F6525/6621 and PIC18F8525/8621 devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2. PIC18F6525/6621/8525/8621 DEVICE FEATURES Features PIC18F6525 PIC18F6621 PIC18F8525 PIC18F8621 Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz 48K 64K 48K 64K Program Memory (Instructions) 24576 32768 24576 32768 Data Memory (Bytes) 3840 3840 3840 3840 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 No No Yes Yes 17 17 Program Memory (Bytes) External Memory Interface Interrupt Sources 17 17 Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Timers 5 5 5 5 Capture/Compare/PWM Modules 2 2 2 2 Enhanced Capture/Compare/ PWM Module 3 3 3 3 MSSP, Addressable EUSART (2) MSSP, Addressable EUSART (2) MSSP, Addressable EUSART (2) MSSP, Addressable EUSART (2) I/O Ports Serial Communications Parallel Communications Ports A, B, C, D, E, Ports A, B, C, D, E, F, G, H, J F, G, H, J PSP PSP PSP PSP 10-bit Analog-to-Digital Module 12 input channels 12 input channels 16 input channels 16 input channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Package DS39612B-page 8 Yes Yes Yes Yes Yes Yes Yes Yes 77 Instructions 77 Instructions 77 Instructions 77 Instructions 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 1-1: PIC18F6525/6621 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/LVDIN OSC2/CLKO/RA6 Data Latch Data RAM (3.8 Kbytes) inc/dec logic Address Latch 20 PCLATU PCLATH 12 PCU PCH PCL Program Counter Program Memory (48/64 Kbytes) RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD 12 4 BSR Address Latch PORTB Address<12> 31 Level Stack 4 FSR0 Bank 0, F FSR1 FSR2 12 Data Latch Decode Table Latch inc/dec logic PORTC RC0/T1OSO/T13CKI RC1/T1OSI/ECCP2(1)/P2A(1) RC2/ECCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 8 16 ROM Latch IR PORTD 8 RD7/PSP7 :RD0/PSP0 PRODH PRODL Instruction Decode and Control OSC2/CLKO OSC1/CLKI VDD, VSS Data EEPROM Comparator ECCP1 Note Timer0 ECCP2 Timer1 ECCP3 W 8 8 8 ALU<8> Power-on Reset Watchdog Timer Brown-out Reset Test Mode Select Precision Band Gap Reference PORTF RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF RF6/AN11 RF7/SS 8 MCLR(2) Timer2 CCP4 RE0/RD/P2D RE1/WR/P2C RE2/CS/P2B RE3/P3C RE4/P3B RE5/P1C RE6/P1B RE7/ECCP2(1)/P2A(1) 8 BITOP 8 Power-up Timer Oscillator Start-up Timer Timing Generation BOR LVD PORTE 8 x 8 Multiply 3 CCP5 PORTG Timer3 MSSP Timer4 10-bit ADC EUSART1 EUSART2 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set. 2: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D RG4/CCP5/P1D MCLR/VPP/RG5(2) DS39612B-page 9 PIC18F6525/6621/8525/8621 FIGURE 1-2: PIC18F8525/8621 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer<21> Data RAM (3.8 Kbytes) inc/dec logic PORTB Address Latch System Bus Interface 20 PCLATU PCLATH PCU PCH PCL Program Counter Address Latch Program Memory (48/64 Kbytes) RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/LVDIN OSC2/CLKO/RA6 Data Latch 8 8 21 PORTA RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3/INT3/ECCP2(1)/P2A(1) RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD 12 Address<12> 4 BSR 31 Level Stack 12 4 Bank0, F FSR0 FSR1 FSR2 12 PORTC RC0/T1OSO/T13CKI RC1/T1OSI/ECCP2(1)/P2A(1) RC2/ECCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 Data Latch Decode Table Latch inc/dec logic 8 16 ROM Latch PORTD IR RD7/AD7/PSP7: RD0/AD0/PSP0(4) AD15:AD0, A19:16(4) 8 PORTE PRODH PRODL Instruction Decode and Control OSC2/CLKO OSC1/CLKI 8 x 8 Multiply 8 ALU<8> 8 Watchdog Timer Brown-out Reset Test Mode Select VDD, VSS 8 PORTF Oscillator Start-up Timer Power-on Reset Precision Band Gap Reference W 8 BITOP 8 Power-up Timer Timing Generation 8 3 PORTG MCLR(3) PORTH Data EEPROM BOR LVD Timer0 Timer1 Timer2 Timer3 Timer4 10-bit ADC RE0/AD8/RD/P2D(4) RE1/AD9/WR/P2C(4) RE2/AD10/CS/P2B(4) RE3/AD11/P3C(2,4) RE4/AD12/P3B(2,4) RE5/AD13/P1C(2,4) RE6/AD14/P1B(2,4) RE7/AD15/ECCP2(1)/P2A(1,4) RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF RF6/AN11 RF7/SS RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D RG4/CCP5/P1D MCLR/VPP/RG5(3) RH0/A16:RH3/A19(4) RH4/AN12/P3C(2) RH5/AN13/P3B(2) RH6/AN14/P1C(2) RH7/AN15/P1B(2) PORTJ Comparator Note 1: 2: 3: 4: ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP EUSART1 EUSART2 RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is configured in Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes. P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is not set. RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. External memory interface pins are multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16). DS39612B-page 10 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18F6X2X PIC18F8X2X 7 9 MCLR/VPP/RG5(9) Pin Type Buffer Type MCLR I ST VPP RG5 P I -- ST I CMOS/ST I CMOS O -- CLKO O -- RA6 I/O TTL OSC1/CLKI OSC1 39 49 CLKI OSC2/CLKO/RA6 OSC2 40 50 Description Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. DS39612B-page 11 PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 28 30 RA6 27 TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. I/O ST/OD I ST Digital I/O - Open-drain when configured as output. Timer0 external clock input. I/O I I TTL Analog Analog 29 28 27 34 T0CKI RA5/AN4/LVDIN RA5 AN4 LVDIN I/O I 33 Digital I/O. Analog input 4. Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. DS39612B-page 12 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 RB0 INT0 FLT0 48 RB1/INT1 RB1 INT1 47 RB2/INT2 RB2 INT2 46 RB3/INT3/ECCP2/P2A RB3 INT3 ECCP2(1) 45 58 44 RB5/KBI1/PGM RB5 KBI1 PGM 43 RB6/KBI2/PGC RB6 KBI2 PGC 42 RB7/KBI3/PGD RB7 KBI3 PGD 37 TTL ST ST Digital I/O. External interrupt 0. PWM Fault input for ECCP1. I/O I TTL ST Digital I/O. External interrupt 1. I/O I TTL ST Digital I/O. External interrupt 2. I/O I/O I/O TTL ST ST O -- Digital I/O. External interrupt 3. Enhanced Capture 2 input, Compare 2 output, PWM2 output. ECCP2 output P2A. I/O I TTL ST Digital I/O. Interrupt-on-change pin. I/O I I/O TTL ST ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPTM programming enable pin. I/O I I/O TTL ST ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock. I/O I I/O TTL ST ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data. 57 56 55 P2A(1) RB4/KBI0 RB4 KBI0 I/O I I 54 53 52 47 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. DS39612B-page 13 PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(2) 29 36 33 34 35 RC5/SDO RC5 SDO 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 I/O I I/O ST CMOS ST O -- I/O I/O ST ST O -- I/O I/O ST ST I/O ST I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. USART1 asynchronous transmit. USART1 synchronous clock (see RX1/DT1). I/O I I/O ST ST ST Digital I/O. USART1 asynchronous receive. USART1 synchronous data (see TX1/CK1). Digital I/O. Timer1 oscillator input. Enhanced Capture 2 input, Compare 2 output, PWM 2 output. ECCP2 output P2A. Digital I/O. Enhanced Capture 1 input, Compare 1 output, PWM 1 output. ECCP1 output P1A. 44 SCL RC4/SDI/SDA RC4 SDI SDA Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. 43 P1A RC3/SCK/SCL RC3 SCK ST -- ST 35 P2A(2) RC2/ECCP1/P1A RC2 ECCP1 I/O O I Digital I/O. Synchronous serial clock input/output for SPITM mode. Synchronous serial clock input/output for I2CTM mode. 45 46 37 38 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. DS39612B-page 14 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/AD0/PSP0 RD0 AD0(3) PSP0 58 RD1/AD1/PSP1 RD1 AD1(3) PSP1 55 RD2/AD2/PSP2 RD2 AD2(3) PSP2 54 RD3/AD3/PSP3 RD3 AD3(3) PSP3 53 RD4/AD4/PSP4 RD4 AD4(3) PSP4 52 RD5/AD5/PSP5 RD5 AD5(3) PSP5 51 RD6/AD6/PSP6 RD6 AD6(3) PSP6 50 RD7/AD7/PSP7 RD7 AD7(3) PSP7 49 72 I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 0. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 1. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 2. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 3. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 4. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 5. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 6. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 7. Parallel Slave Port data. 69 68 67 66 65 64 63 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. DS39612B-page 15 PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/AD8/RD/P2D RE0 AD8(3) RD P2D 2 RE1/AD9/WR/P2C RE1 AD9(3) WR P2C 1 RE2/AD10/CS/P2B RE2 AD10(3) CS P2B 64 RE3/AD11/P3C RE3 AD11(3) P3C(4) 63 RE4/AD12/P3B RE4 AD12(3) P3B(4) 62 RE5/AD13/P1C RE5 AD13(3) P1C(4) 61 RE6/AD14/P1B RE6 AD14(3) P1B(4) 60 RE7/AD15/ECCP2/P2A RE7 AD15(3) ECCP2(5) 59 P2A(5) 4 I/O I/O I O ST TTL TTL -- Digital I/O. External memory address/data 8. Read control for Parallel Slave Port. ECCP2 output P2D. I/O I/O I O ST TTL TTL ST Digital I/O. External memory address/data 9. Write control for Parallel Slave Port. ECCP2 output P2C. I/O I/O I O ST TTL TTL -- Digital I/O. External memory address/data 10. Chip select control for Parallel Slave Port. ECCP2 output P2B. I/O I/O O ST TTL -- Digital I/O. External memory address/data 11. ECCP3 output P3C. I/O I/O O ST TTL -- Digital I/O. External memory address/data 12. ECCP3 output P3B. I/O I/O O ST TTL -- Digital I/O. External memory address/data 13. ECCP1 output P1C. I/O I/O O ST TTL -- Digital I/O. External memory address/data 14. ECCP1 output P1B. I/O I/O I/O ST TTL ST O -- Digital I/O. External memory address/data 15. Enhanced Capture 2 input, Compare 2 output, PWM 2 output. ECCP2 output P2A. 3 78 77 76 75 74 73 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. DS39612B-page 16 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 18 RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF1 AN8 15 RF4/AN9 RF1 AN9 14 RF5/AN10/CVREF RF1 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS RF7 SS 11 24 I/O I ST Analog Digital I/O. Analog input 5. I/O I O ST Analog ST Digital I/O. Analog input 6. Comparator 2 output. I/O I O ST Analog ST Digital I/O. Analog input 7. Comparator 1 output. I/O I ST Analog Digital I/O. Analog input 8. I/O I ST Analog Digital I/O. Analog input 9. I/O I O ST Analog Analog Digital I/O. Analog input 10. Comparator VREF output. I/O I ST Analog Digital I/O. Analog input 11. I/O I ST TTL 23 18 17 16 15 14 13 Digital I/O. SPITM slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. DS39612B-page 17 PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 3 5 P3A RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2 RG2 RX2 DT2 5 RG3/CCP4/P3D RG3 CCP4 6 8 7 Digital I/O. Enhanced Capture 3 input, Compare 3 output, PWM 3 output. ECCP3 output P3A. O -- I/O O I/O ST -- ST Digital I/O. USART2 asynchronous transmit. USART2 synchronous clock (see RX2/DT2). I/O I I/O ST ST ST Digital I/O. USART2 asynchronous receive. USART2 synchronous data (see TX2/CK2). I/O I/O ST ST O -- Digital I/O. Capture 4 input, Compare 4 output, PWM 4 output. ECCP3 output P3D. I/O I/O ST ST 7 8 10 P1D RG5 ST ST 6 P3D RG4/CCP5/P1D RG4 CCP5 I/O I/O 9 O -- -- -- Digital I/O. Capture 5 input, Compare 5 output, PWM 5 output. ECCP1 output P1D. See MCLR/VPP/RG5 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. DS39612B-page 18 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTH is a bidirectional I/O port(6). RH0/A16 RH0 A16 -- RH1/A17 RH1 A17 -- RH2/A18 RH2 A18 -- RH3/A19 RH3 A19 -- RH4/AN12/P3C RH4 AN12 P3C(7) -- RH5/AN13/P3B RH5 AN13 P3B(7) -- RH6/AN14/P1C RH6 AN14 P1C(7) -- RH7/AN15/P1B RH7 AN15 P1B(7) -- 79 I/O O ST TTL Digital I/O. External memory address 16. I/O O ST TTL Digital I/O. External memory address 17. I/O O ST TTL Digital I/O. External memory address 18. I/O O ST TTL Digital I/O. External memory address 19. I/O I O ST Analog -- Digital I/O. Analog input 12. ECCP3 output P3C. I/O I O ST Analog -- Digital I/O. Analog input 13. ECCP3 output P3B. I/O I O ST Analog -- Digital I/O. Analog input 14. ECCP1 output P1C. I/O I O ST Analog -- Digital I/O. Analog input 15. ECCP1 output P1B. 80 1 2 22 21 20 19 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. DS39612B-page 19 PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTJ is a bidirectional I/O port(6). RJ0/ALE RJ0 ALE -- RJ1/OE RJ1 OE -- RJ2/WRL RJ2 WRL -- RJ3/WRH RJ3 WRH -- RJ4/BA0 RJ4 BA0 -- RJ5/CE RJ5 CE -- RJ6/LB RJ6 LB -- RJ7/UB RJ7 UB -- 62 I/O O ST TTL Digital I/O. External memory address latch enable. I/O O ST TTL Digital I/O. External memory output enable. I/O O ST TTL Digital I/O. External memory write low control. I/O O ST TTL Digital I/O. External memory write high control. I/O O ST TTL Digital I/O. System bus byte address 0 control. I/O O ST TTL Digital I/O External memory access indicator. I/O O ST TTL Digital I/O. External memory low byte select. I/O O ST TTL Digital I/O. External memory high byte select. 61 60 59 39 40 41 42 VSS 9, 25, 41, 56 11, 31, 51, 70 P -- Ground reference for logic and I/O pins. VDD 10, 26, 38, 57 12, 32, 48, 71 P -- Positive supply for logic and I/O pins. AVSS(8) 20 26 P -- Ground reference for analog modules. AVDD(8) 19 25 P -- Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller). 2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices). 3: External memory interface functions are only available on PIC18F8525/8621 devices. 4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for all PIC18F6525/6621 devices. 5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode). 6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices. 7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set. 8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSPTM modes. See parameter D001 for details. 9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. DS39612B-page 20 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F6525/6621/8525/8621 devices can be operated in twelve different oscillator modes. The user can program four configuration bits (FOSC3, FOSC2, FOSC1 and FOSC0) to select one of these eight modes: 1. 2. 3. 4. 5. 6. LP XT HS RC EC ECIO Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator External Resistor/Capacitor External Clock External Clock with I/O pin enabled 7. HS+PLL High-Speed Crystal/Resonator with PLL enabled 8. RCIO External Resistor/Capacitor with I/O pin enabled 9. ECIO+SPLL External Clock with software controlled PLL 10. ECIO+PLL External Clock with PLL and I/O pin enabled 11. HS+SPLL High-Speed Crystal/Resonator with software control 12. RCIO External Resistor/Capacitor with I/O pin enabled 2.2 Crystal Oscillator/Ceramic Resonators In XT, LP, HS, HS+PLL or HS+SPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The PIC18F6525/6621/8525/8621 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. FIGURE 2-1: C1(1) CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP CONFIGURATION) OSC1 XTAL To Internal Logic RF(3) Sleep RS(2) C2(1) Note 1: 2: 3: OSC2 PIC18F6X2X/8X2X See Table 2-1 and Table 2-2 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the oscillator mode chosen. TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Ranges Tested: Mode Freq C1 C2 XT 455 kHz 2.0 MHz 4.0 MHz 68-100 pF 15-68 pF 15-68 pF 68-100 pF 15-68 pF 15-68 pF HS 8.0 MHz 16.0 MHz 10-68 pF 10-22 pF 10-68 pF 10-22 pF These values are for design guidance only. See notes following this table. Resonators Used: 2 kHz 8 MHz 4 MHz 16 MHz Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use high gain HS mode, try a lower frequency resonator or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components or verify oscillator performance. 2005 Microchip Technology Inc. DS39612B-page 21 PIC18F6525/6621/8525/8621 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested: Mode Freq C1 C2 LP 32.0 kHz 33 pF 33 pF XT HS 200 kHz 47-68 pF 47-68 pF 1.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 25.0 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes following this table. Crystals Used 32 kHz 4 MHz 200 kHz 8 MHz 1 MHz 20 MHz 2.3 RC Oscillator For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 2-3 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. FIGURE 2-3: RC OSCILLATOR MODE VDD Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. REXT 2: RS (see Figure 2-1) may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. CEXT 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components or verify oscillator performance. Recommended values: An external clock source may also be connected to the OSC1 pin in the HS, XT and LP modes as shown in Figure 2-2. FIGURE 2-2: Internal Clock OSC1 PIC18F6X2X/8X2X VSS FOSC/4 OSC2/CLKO 3 k REXT 100 k CEXT > 20 pF The RCIO Oscillator mode functions like the RC mode except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSCILLATOR CONFIGURATION) OSC1 Clock from Ext. System PIC18F6X2X/8X2X Open DS39612B-page 22 OSC2 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2.4 External Clock Input 2.5 The EC, ECIO, EC+PLL and EC+SPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is a maximum 1.5 s start-up required after a Power-on Reset or wake-up from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1 Clock from Ext. System PIC18F6X2X/8X2X OSC2 FOSC/4 The ECIO Oscillator mode functions like the EC mode except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode. FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1 Clock from Ext. System A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming oscillator signal by 4. For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz. This is useful for customers who are concerned with EMI due to high-frequency crystals. The PLL can only be enabled when the oscillator configuration bits are programmed for High-Speed Oscillator or External Clock mode. If they are programmed for any other mode, the PLL is not enabled and the system clock will come directly from OSC1. There are two types of PLL modes: Software Controlled PLL and Configuration Bits Controlled PLL. In Software Controlled PLL mode, PIC18F6525/6621/ 8525/8621 executes at regular clock frequency after all Reset conditions. During execution, the application can enable PLL and switch to 4x clock frequency operation by setting the PLLEN bit in the OSCCON register. In Configuration Bits Controlled PLL, the PLL operation cannot be changed "on-the-fly". To enable or disable it, the controller must either cycle through a Power-on Reset, or switch the clock source from the main oscillator to the Timer1 oscillator and back again (see Section 2.6 "Oscillator Switching Feature" for details). The type of PLL is selected by programming FOSC<3:0> configuration bits in the CONFIG1H Configuration register. The oscillator mode is specified during device programming. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out that is called TPLL. PIC18F6X2X/8X2X I/O (OSC2) RA6 FIGURE 2-6: Phase Locked Loop (PLL) PLL BLOCK DIAGRAM PLL Enable Phase Comparator FIN Loop Filter VCO MUX FOUT SYSCLK Divide by 4 2005 Microchip Technology Inc. DS39612B-page 23 PIC18F6525/6621/8525/8621 2.6 Oscillator Switching Feature The PIC18F6525/6621/8525/8621 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For the PIC18F6525/6621/ 8525/8621 devices, this alternate clock source is the Timer1 oscillator. If a low-frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a low-power execution mode. FIGURE 2-7: Figure 2-7 shows a block diagram of the system clock sources. The clock switching feature is enabled by programming the Oscillator Switching Enable (OSCSEN) bit in the CONFIG1H Configuration register to a `0'. Clock switching is disabled in an erased device. See Section 12.0 "Timer1 Module" for further details of the Timer1 oscillator. See Section 24.0 "Special Features of the CPU" for Configuration register details. DEVICE CLOCK SOURCES PIC18F6X2X/8X2X Main Oscillator OSC2 Sleep TOSC/4 Timer1 Oscillator T1OSO MUX TOSC OSC1 T1OSI 4 x PLL TSCLK T T 1P T1OSCEN Enable Oscillator Clock Source Clock Source Option for Other Modules DS39612B-page 24 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2.6.1 SYSTEM CLOCK SWITCH BIT Note: The system clock source switching is performed under software control. The system clock switch bits, SCS1:SCS0 (OSCCON<1:0>), control the clock switching. When the SCS0 bit is `0', the system clock source comes from the main oscillator that is selected by the FOSC configuration bits in the CONFIG1H Configuration register. When the SCS0 bit is set, the system clock source will come from the Timer1 oscillator. The SCS0 bit is cleared on all forms of Reset. The Timer1 oscillator must be enabled and operating to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON). If the Timer1 oscillator is not enabled, then any write to the SCS0 bit will be ignored (SCS0 bit forced cleared) and the main oscillator will continue to be the system clock source. When the FOSC bits are programmed for Software PLL mode, the SCS1 bit can be used to select between primary oscillator/clock and PLL output. The SCS1 bit will only have an effect on the system clock if the PLL is enabled (PLLEN = 1) and locked (LOCK = 1), else it will be forced cleared. When programmed with Configuration Controlled PLL, the SCS1 bit will be forced clear. REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- LOCK PLLEN(1) SCS1 SCS0(2) bit 7 bit 0 bit 7-4 Unimplemented: Read as `0' bit 3 LOCK: Phase Lock Loop Lock Status bit 1 = Phase Lock Loop output is stable as system clock 0 = Phase Lock Loop output is not stable and output cannot be used as system clock bit 2 PLLEN: Phase Lock Loop Enable bit(1) 1 = Enable Phase Lock Loop output as system clock 0 = Disable Phase Lock Loop bit 1 SCS1: System Clock Switch bit 1 When PLLEN and LOCK bits are set: 1 = Use PLL output 0 = Use primary oscillator/clock input pin When PLLEN or LOCK bit is cleared: Bit is forced clear. bit 0 SCS0: System Clock Switch bit 0(2) When OSCSEN configuration bit = 0 and T1OSCEN bit = 1: 1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin When OSCSEN and T1OSCEN are in other states: Bit is forced clear. Note 1: PLLEN bit is forced set when configured for ECIO+PLL and HS+PLL modes. This bit is writable for ECIO+SPLL and HS+SPLL modes only; forced cleared for all other oscillator modes. 2: The setting of SCS0 = 1 supersedes SCS1 = 1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 25 PIC18F6525/6621/8525/8621 2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-8. The Timer1 oscillator is assumed to be running all the time. After the SCS0 bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles. PIC18F6525/6621/8525/8621 devices contain circuitry to prevent "glitches" when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 Q2 Q3 Q4 Q1 1 T1OSI Q1 TT1P 2 3 4 5 6 7 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 8 TSCS OSC1 Internal System Clock TOSC TDLY SCS (OSCCON<0>) Program Counter Note: PC PC + 4 PC + 2 TDLY is the delay from SCS high to first count of transition circuit. The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place. FIGURE 2-9: If the main oscillator is configured for an external crystal (HS, XT, LP), then the transition will take place after an oscillator start-up time (TOST) has occurred. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes, is shown in Figure 2-9. TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP) Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 TT1P T1OSI OSC1 1 TOST 2 3 4 5 6 7 8 TSCS TOSC Internal System Clock SCS (OSCCON<0>) Program Counter Note: PC PC + 2 PC + 6 TOST = 1024 TOSC (drawing not to scale). DS39612B-page 26 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 If the main oscillator is configured for HS mode with PLL active, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL timeout is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS+PLL mode, is shown in Figure 2-10. FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL ACTIVE, SCS1 = 1) Q4 TT1P Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST TPLL TOSC PLL Clock Input TSCS 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 4 PC + 2 Note: TOST = 1024 TOSC (drawing not to scale). If the main oscillator is configured for EC mode with PLL active, only PLL time-out (TPLL) will occur. The PLL timeout is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for EC with PLL active, is shown in Figure 2-11. FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (EC WITH PLL ACTIVE, SCS1 = 1) Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TT1P Q1 T1OSI OSC1 TPLL TOSC PLL Clock Input 1 2 3 TSCS 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) Program Counter PC 2005 Microchip Technology Inc. PC + 2 PC + 4 DS39612B-page 27 PIC18F6525/6621/8525/8621 If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure 2-12. FIGURE 2-12: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TT1P T1OSI TOSC OSC1 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) TSCS Program Counter Note: 2.7 PC + 2 PC PC + 4 RC Oscillator mode assumed. Effects of Sleep Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the onchip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor TABLE 2-3: switching currents have been removed, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The user can wake from Sleep through external Reset, Watchdog Timer Reset, or through an interrupt. OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin RC Floating, external resistor should pull high At logic low RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating Configured as PORTA, bit 6 EC Floating At logic low LP, XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: 2.8 See Table 3-1 in Section 3.0 "Reset" for time-outs due to Sleep and MCLR Reset. Power-up Delays Power-up delays are controlled by two timers so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply and clock are stable. For additional information on Reset operation, see Section 3.0 "Reset". The first timer is the Power-up Timer (PWRT) which optionally provides a fixed delay of 72 ms (nominal) on power-up only (POR and BOR). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. DS39612B-page 28 With the PLL enabled (HS+PLL and EC+PLL oscillator mode), the time-out sequence following a Power-on Reset is different from other oscillator modes. The time-out sequence is as follows: First, the PWRT timeout is invoked after a POR time delay has expired. Then, the Oscillator Start-up Timer (OST) is invoked. However, this is still not a sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional fixed 2 ms (nominal) time-out to allow the PLL ample time to lock to the incoming clock frequency. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 3.0 RESET The PIC18F6525/6621/8525/8621 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations as indicated in Table 3-2. These bits are used in software to determine the nature of the Reset. See Table 3-3 for a full description of the Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" on Power-on Reset, MCLR, WDT Reset, Brownout Reset, MCLR Reset during Sleep and by the RESET instruction. FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Pointer Stack Full/Underflow Reset External Reset WDT Time-out Reset MCLR WDT Module Sleep VDD Rise Power-on Reset Detect VDD Brown-out Reset BOR S 10-bit Ripple Counter R OST/PWRT OST Chip_Reset Q OSC1 PWRT On-chip RC OSC(1) 10-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: 2: This is a separate oscillator from the RC oscillator of the CLKI pin. See Table 3-1 for time-out situations. 2005 Microchip Technology Inc. DS39612B-page 29 PIC18F6525/6621/8525/8621 3.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, tie the MCLR pin through a 1 k to 10 k resistor to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. FIGURE 3-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) R R1 MCLR C Note 1: 2: 3: 3.2 PIC18F6X2X/8X2X External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. R1 = 1 k to 10 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Power-up Timer (PWRT) The Power-up Timer provides a fixed nominal time-out (parameter 33) only on power-up from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See DC parameter 33 for details. Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delays after the PWRT delay is over (parameter 32). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset, or wake-up from Sleep. 3.4 PLL Lock Time-out With the PLL enabled, the time-out sequence following a Power-on Reset is different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 3.5 VDD D 3.3 Brown-out Reset (BOR) A configuration bit, BOR, can disable (if clear/ programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below parameter D005 for greater than parameter 35, the brown-out situation will reset the chip. A Reset may not occur if VDD falls below parameter D005 for less than parameter 35. The chip will remain in Brown-out Reset until VDD rises above BVDD. If the Power-up Timer is enabled, it will be invoked after VDD rises above BVDD; it then will keep the chip in Reset for an additional time delay (parameter 33). If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute the additional time delay. 3.6 Time-out Sequence On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after the POR time delay has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, the time-outs will expire if MCLR is kept low long enough. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18F6525/6621/8525/ 8621 device operating in parallel. Table 3-2 shows the Reset conditions for some Special Function Registers, while Table 3-3 shows the Reset conditions for all of the registers. DS39612B-page 30 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Oscillator Configuration Wake-up from Sleep or Oscillator Switch Brown-out PWRTE = 0 PWRTE = 1 HS with PLL enabled(1) 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC + 2 ms HS, XT, LP EC External RC Note 1: 2: 3: 1.5 s 72 ms 72 ms 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC -- 1024 TOSC 72 ms (2) 1.5 s(3) 72 ms (2) -- 2 ms is the nominal time required for the 4x PLL to lock. 72 ms is the nominal power-up timer delay, if implemented. 1.5 s is the recovery time from Sleep. There is no recovery time from oscillator switch. RCON REGISTER BITS AND POSITIONS(1) REGISTER 3-1: R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 IPEN -- -- RI TO PD POR BOR bit 7 bit 0 Note 1: Refer to Section 4.14 "RCON Register" for bit definitions. TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 0 0 u u MCLR Reset during normal operation 0000h u u u u u u u Software Reset during normal operation 0000h 0 u u u u u u Condition Stack Full Reset during normal operation 0000h u u u u u u 1 Stack Underflow Reset during normal operation 0000h u u u u u 1 u MCLR Reset during Sleep 0000h u 1 0 u u u u WDT Reset 0000h 1 0 1 u u u u WDT Wake-up PC + 2 u 0 0 u u u u Brown-out Reset 0000h 1 1 1 1 0 u u u 1 0 u u u u Interrupt Wake-up from Sleep PC + 2 (1) Legend: u = unchanged, x = unknown Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0008h or 0018h). 2005 Microchip Technology Inc. DS39612B-page 31 PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets TOSU PIC18F6X2X PIC18F8X2X ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F6X2X PIC18F8X2X 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F6X2X PIC18F8X2X ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu PCL PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F6X2X PIC18F8X2X 0000 000x 0000 000u uuuu uuuu(1) INTCON2 PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 PIC18F6X2X PIC18F8X2X 1100 0000 1100 0000 uuuu uuuu(1) INDF0 PIC18F6X2X PIC18F8X2X N/A N/A N/A POSTINC0 PIC18F6X2X PIC18F8X2X N/A N/A N/A Register Wake-up via WDT or Interrupt POSTDEC0 PIC18F6X2X PIC18F8X2X N/A N/A N/A PREINC0 PIC18F6X2X PIC18F8X2X N/A N/A N/A PLUSW0 PIC18F6X2X PIC18F8X2X N/A N/A N/A FSR0H PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu FSR0L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F6X2X PIC18F8X2X N/A N/A N/A POSTINC1 PIC18F6X2X PIC18F8X2X N/A N/A N/A POSTDEC1 PIC18F6X2X PIC18F8X2X N/A N/A N/A PREINC1 PIC18F6X2X PIC18F8X2X N/A N/A N/A PLUSW1 PIC18F6X2X PIC18F8X2X N/A N/A N/A FSR1H PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'. 7: If MCLR function is disabled, PORTG<5> is a read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all `0's when the device is in Microcontroller mode. DS39612B-page 32 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6X2X PIC18F8X2X N/A N/A N/A POSTINC2 PIC18F6X2X PIC18F8X2X N/A N/A N/A Register POSTDEC2 PIC18F6X2X PIC18F8X2X N/A N/A N/A PREINC2 PIC18F6X2X PIC18F8X2X N/A N/A N/A PLUSW2 PIC18F6X2X PIC18F8X2X N/A N/A N/A FSR2H PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu FSR2L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F6X2X PIC18F8X2X ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6X2X PIC18F8X2X 0000 0000 uuuu uuuu uuuu uuuu TMR0L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu LVDCON PIC18F6X2X PIC18F8X2X --00 0101 --00 0101 --uu uuuu WDTCON PIC18F6X2X PIC18F8X2X ---- ---0 ---- ---0 ---- ---u (4) RCON PIC18F6X2X PIC18F8X2X 0--1 11qq 0--1 qquu u--1 qquu TMR1H PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6X2X PIC18F8X2X 0-00 0000 u-uu uuuu u-uu uuuu TMR2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu T2CON PIC18F6X2X PIC18F8X2X -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'. 7: If MCLR function is disabled, PORTG<5> is a read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all `0's when the device is in Microcontroller mode. 2005 Microchip Technology Inc. DS39612B-page 33 PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADCON0 PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu ADCON1 PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6X2X PIC18F8X2X 0-00 0000 0-00 0000 u-uu uuuu CCPR1H PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu CCPR3H PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu ECCP1AS PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TMR3H PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F6X2X PIC18F8X2X 0000 0000 uuuu uuuu uuuu uuuu PIC18F6X2X PIC18F8X2X 0000 ---- 0000 ---- uuuu ---- PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TXSTA1 PIC18F6X2X PIC18F8X2X 0000 0010 0000 0010 uuuu uuuu RCSTA1 PIC18F6X2X PIC18F8X2X 0000 000x 0000 000x uuuu uuuu EEADRH PIC18F6X2X PIC18F8X2X ---- --00 ---- --00 ---- --uu EEADR PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu EEDATA PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu EECON2 PIC18F6X2X PIC18F8X2X ---- ---- ---- ---- ---- ---- EECON1 PIC18F6X2X PIC18F8X2X xx-0 x000 uu-0 u000 uu-u u000 Register PSPCON SPBRG1 (8) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'. 7: If MCLR function is disabled, PORTG<5> is a read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all `0's when the device is in Microcontroller mode. DS39612B-page 34 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR3 PIC18F6X2X PIC18F8X2X --11 1111 --11 1111 --uu uuuu PIR3 PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu PIE3 PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu IPR2 PIC18F6X2X PIC18F8X2X -1-1 1111 -1-1 1111 -u-u uuuu PIR2 PIC18F6X2X PIC18F8X2X -0-0 0000 -0-0 0000 -u-u uuuu(1) PIE2 PIC18F6X2X PIC18F8X2X -0-0 0000 -0-0 0000 -u-u uuuu IPR1 PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu(1) PIE1 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu MEMCON(9) PIC18F6X2X PIC18F8X2X 0-00 --00 0-00 --00 u-uu --uu TRISJ PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu TRISH PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu TRISG PIC18F6X2X PIC18F8X2X ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu TRISE PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu TRISD PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu Register (5,6) 1111(5) 1111(5) -uuu uuuu(5) TRISA PIC18F6X2X PIC18F8X2X -111 LATJ PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu LATH PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu LATG PIC18F6X2X PIC18F8X2X ---x xxxx ---u uuuu ---u uuuu LATF PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu LATE PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu LATD PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu LATA(5,6) PIC18F6X2X PIC18F8X2X -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) PORTJ PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu PORTH PIC18F6X2X PIC18F8X2X 0000 xxxx 0000 uuuu uuuu uuuu -111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'. 7: If MCLR function is disabled, PORTG<5> is a read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all `0's when the device is in Microcontroller mode. 2005 Microchip Technology Inc. DS39612B-page 35 PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt PORTG(7) PIC18F6X2X PIC18F8X2X --xx xxxx --uu uuuu --uu uuuu PORTF PIC18F6X2X PIC18F8X2X x000 0000 u000 0000 uuuu uuuu PORTE PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu PORTD PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu Register (5,6) 0000(5) PORTA PIC18F6X2X PIC18F8X2X -x0x SPBRGH1 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu BAUDCON1 PIC18F6X2X PIC18F8X2X -1-0 0-00 -1-0 0-00 -u-u u-uu SPBRGH2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu BAUDCON2 PIC18F6X2X PIC18F8X2X -1-0 0-00 -1-0 0-00 -u-1 u-uu ECCP1DEL PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TMR4 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu PR4 PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu T4CON PIC18F6X2X PIC18F8X2X -000 0000 -000 0000 -uuu uuuu CCPR4H PIC18F6X2X PIC18F8X2X xxxx xxxx xxxx xxxx uuuu uuuu CCPR4L PIC18F6X2X PIC18F8X2X xxxx xxxx xxxx xxxx uuuu uuuu CCP4CON PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu CCPR5H PIC18F6X2X PIC18F8X2X xxxx xxxx xxxx xxxx uuuu uuuu CCPR5L PIC18F6X2X PIC18F8X2X xxxx xxxx xxxx xxxx uuuu uuuu CCP5CON PIC18F6X2X PIC18F8X2X --00 0000 --00 0000 --uu uuuu SPBRG2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TXSTA2 PIC18F6X2X PIC18F8X2X 0000 0010 0000 0010 uuuu uuuu RCSTA2 PIC18F6X2X PIC18F8X2X 0000 000x 0000 000x uuuu uuuu ECCP3AS PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu ECCP3DEL PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu ECCP2AS PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu ECCP2DEL PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu -u0u 0000(5) -uuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'. 7: If MCLR function is disabled, PORTG<5> is a read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all `0's when the device is in Microcontroller mode. DS39612B-page 36 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2005 Microchip Technology Inc. DS39612B-page 37 PIC18F6525/6621/8525/8621 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 k RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD VIA 1 k RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. DS39612B-page 38 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 4.0 MEMORY ORGANIZATION There are three memory blocks in PIC18F6525/6621/ 8525/8621 devices. They are: * Program Memory * Data RAM * Data EEPROM Data and program memory use separate busses which allow for concurrent access of these blocks. Additional detailed information for Flash program memory and data EEPROM is provided in Section 5.0 "Flash Program Memory" and Section 7.0 "Data EEPROM Memory", respectively. In addition to on-chip Flash, the PIC18F8525/8621 devices are also capable of accessing external program memory through an external memory bus. Depending on the selected operating mode (discussed in Section 4.1.1 "PIC18F6525/6621/8525/8621 Program Memory Modes"), the controllers may access either internal or external program memory exclusively, or both internal and external memory in selected blocks. Additional information on the external memory interface is provided in Section 6.0 "External Memory Interface". 4.1 Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all `0's (a NOP instruction). The PIC18F6525 and PIC18F8525 each have 48 Kbytes of on-chip Flash memory, while the PIC18F6621 and PIC18F8621 have 64 Kbytes of Flash. This means that PIC18FX525 devices can store internally up to 24,576 single-word instructions and PIC18FX621 devices can store up to 32,768 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Figure 4-1 shows the program memory map for PIC18FX525 devices, while Figure 4-2 shows the program memory map for PIC18FX621 devices. 4.1.1 PIC18F6525/6621/8525/8621 PROGRAM MEMORY MODES PIC18F8525/8621 devices differ significantly from their PIC18 predecessors in their utilization of program memory. In addition to available on-chip Flash program memory, these controllers can also address up to 2 Mbytes of external program memory through the external memory interface. There are four distinct operating modes available to the controllers: * * * * Microprocessor (MP) Microprocessor with Boot Block (MPBB) Extended Microcontroller (EMC) Microcontroller (MC) The Program Memory mode is determined by setting the two Least Significant bits of the CONFIG3L Configuration Byte register as shown in Register 4-1 (see Section 24.1 "Configuration Bits" for additional details on the device configuration bits). The Program Memory modes operate as follows: * The Microprocessor Mode permits access only to external program memory; the contents of the on-chip Flash memory are ignored. The 21-bit program counter permits access to a 2-Mbyte linear program memory space. * The Microprocessor with Boot Block Mode accesses on-chip Flash memory from addresses 000000h to 0007FFh. Above this, external program memory is accessed all the way up to the 2-Mbyte limit. Program execution automatically switches between the two memories as required. * The Microcontroller Mode accesses only on-chip Flash memory. Attempts to read above the physical limit of the on-chip Flash (BFFFh for the PIC18FX525, FFFFh for the PIC18FX621) causes a read of all `0's (a NOP instruction). The Microcontroller mode is also the only operating mode available to PIC18F6525/6621 devices. * The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip Flash memory; above this, the device accesses external program memory up to the 2-Mbyte program space limit. As with Boot Block mode, execution automatically switches between the two memories as required. In all modes, the microcontroller has complete access to data RAM and EEPROM. Figure 4-3 compares the memory maps of the different program memory modes. The differences between on-chip and external memory access limitations are more fully explained in Table 4-1. 2005 Microchip Technology Inc. DS39612B-page 39 PIC18F6525/6621/8525/8621 FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FX525 FIGURE 4-2: PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FX621 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 * * * * * * Stack Level 31 Stack Level 31 000000h Reset Vector Reset Vector 000000h High Priority Interrupt Vector 000008h High Priority Interrupt Vector 000008h Low Priority Interrupt Vector 000018h Low Priority Interrupt Vector 000018h On-Chip Flash Program Memory User Memory Space On-Chip Flash Program Memory Read `0' 00FFFFh 010000h User Memory Space 00BFFFh 00C000h Read `0' 1FFFFFh 200000h 1FFFFFh 200000h TABLE 4-1: MEMORY ACCESS FOR PIC18F8525/8621 PROGRAM MEMORY MODES Internal Program Memory Operating Mode External Program Memory Execution From Table Read From Table Write To Microprocessor No Access No Access No Access Microprocessor w/Boot Block Yes Yes Yes Microcontroller Yes Yes Yes Extended Microcontroller Yes Yes Yes DS39612B-page 40 Execution From Table Read From Table Write To Yes Yes Yes Yes Yes Yes No Access No Access No Access Yes Yes Yes 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 4-1: CONFIG3L: CONFIGURATION REGISTER 3 LOW R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT -- -- -- -- -- PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable, device will not wait 0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as `0' bit 1-0 PM1:PM0: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode(1) 01 = Microcontroller with Boot Block mode(1) 00 = Extended Microcontroller mode(1) Note 1: This mode is available only on PIC18F8525/8621 devices. Legend: FIGURE 4-3: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' -n = Value after erase `1' = Bit is set 000000h On-Chip Program Memory (No Program Space Execution access) Microprocessor with Boot Block Mode(3) 000000h 0007FFh 000800h 00BFFFh(1) 00FFFFh(2) 00C000h(1) 010000h(2) 1FFFFFh On-Chip Flash 000000h On-Chip Program Memory 1FFFFFh External Memory Extended Microcontroller Mode(3) On-Chip Flash On-Chip Program Memory 00BFFFh(1) 00FFFFh(2) 00C000h(1) 010000h(2) Reads `0's External Program Memory 1FFFFFh External Memory Microcontroller Mode 000000h On-Chip Program Memory External Program Memory 1: 2: 3: x = Bit is unknown MEMORY MAPS FOR PIC18F6525/6621/8525/8621 PROGRAM MEMORY MODES Microprocessor Mode(3) Note `0' = Bit is cleared External Program Memory 1FFFFFh On-Chip Flash External Memory On-Chip Flash PIC18F8525 and PIC18F6525. PIC18F8621 and PIC18F6621. This mode is available only on PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 41 PIC18F6525/6621/8525/8621 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, with the Stack Pointer initialized to 00000b after all Resets. There is no RAM associated with Stack Pointer 00000b. This is only a Reset value. During a CALL type instruction causing a push onto the stack, the Stack Pointer is first incremented and the RAM location pointed to by the Stack Pointer is written with the contents of the PC. During a RETURN type instruction causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR register are transferred to the PC and then the Stack Pointer is decremented. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through SFR registers. Data can also be pushed to, or popped from the stack using the Top-ofStack SFRs. Status bits indicate if the Stack Pointer is at or beyond the 31 levels provided. 4.2.1 TOP-OF-STACK ACCESS The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, hold the contents of the stack location pointed to by the STKPTR register. This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations. DS39612B-page 42 4.2.2 RETURN STACK POINTER (STKPTR) The STKPTR register contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. Register 4-2 shows the STKPTR register. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments when values are pushed onto the stack and decrements when values are popped off the stack. At Reset, the Stack Pointer value will be `0'. The user may read and write the Stack Pointer value. This feature can be used by a real-time operating system for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit can only be cleared in software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. Refer to Section 25.0 "Instruction Set Summary" for a description of the device configuration bits. If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to `0'. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at `0'. The STKUNF bit will remain set until cleared in software or a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 4-2: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- SP4 SP3 SP2 SP1 SP0 STKFUL(1) STKUNF(1) bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as `0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR. Legend: FIGURE 4-4: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU 0x00 TOSH 0x1A Top-of-Stack 4.2.3 STKPTR<4:0> 00010 TOSL 0x34 PUSH AND POP INSTRUCTIONS Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place a return address on the stack. 00011 0x001A34 00010 0x000D58 00001 00000 4.2.4 STACK FULL/UNDERFLOW RESETS These Resets are enabled by programming the STVREN configuration bit. When the STVREN bit is disabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. When the STVREN bit is enabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. The STKFUL or STKUNF bits are only cleared by the user software or a Power-on Reset. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 2005 Microchip Technology Inc. DS39612B-page 43 PIC18F6525/6621/8525/8621 4.3 Fast Register Stack 4.4 A "fast interrupt return" option is available for interrupts. A fast register stack is provided for the STATUS, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers if the FAST RETURN instruction is used to return from the interrupt. The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide. The low byte is called the PCL register; this register is readable and writable. The high byte is called the PCH register. This register contains the PC<15:8> bits and is not directly readable or writable; updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable; updates to the PCU register may be performed through the PCLATU register. A low or high priority interrupt source will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of the PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in software during a low priority interrupt. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a FAST CALL instruction must be executed. The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 4.8.1 "Computed GOTO"). Example 4-1 shows a source code example that uses the fast register stack. EXAMPLE 4-1: FAST REGISTER STACK CODE EXAMPLE CALL SUB1, FAST 4.5 ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK SUB1 FIGURE 4-5: Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the Instruction Register (IR) in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-5. * * * * * RETURN FAST PCL, PCLATH and PCLATU ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC OSC2/CLKO (RC mode) DS39612B-page 44 PC Execute INST (PC - 2) Fetch INST (PC) PC + 2 Execute INST (PC) Fetch INST (PC + 2) PC + 4 Execute INST (PC + 2) Fetch INST (PC + 4) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 4.6 Instruction Flow/Pipelining A fetch cycle begins with the Program Counter (PC) incrementing in Q1. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 4-2). EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW 1. MOVLW 55h TCY0 TCY1 Fetch 1 Execute 1 Fetch 2 2. MOVWF PORTB TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 3. BRA SUB_1 4. BSF In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). Execute 3 Fetch 4 PORTA, BIT3 (Forced NOP) Flush (NOP) Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 All instructions are single-cycle except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed. 4.7 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 4-6 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0' (see Section 4.4 "PCL, PCLATH and PCLATU"). word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1> which accesses the desired byte address in program memory. Instruction #2 in Figure 4-6 shows how the instruction "GOTO 000006h" is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 25.0 "Instruction Set Summary" provides further details of the instruction set. The CALL and GOTO instructions have an absolute program memory address embedded into the instruction. Since instructions are always stored on FIGURE 4-6: INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations Instruction 1: Instruction 2: MOVLW GOTO 055h 000006h Instruction 3: MOVFF 123h, 456h 2005 Microchip Technology Inc. Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h DS39612B-page 45 PIC18F6525/6621/8525/8621 4.7.1 TWO-WORD INSTRUCTIONS The PIC18F6525/6621/8525/8621 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to `1's and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. EXAMPLE 4-3: If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that changes the PC. A program example that demonstrates this concept is shown in Example 4-3. Refer to Section 25.0 "Instruction Set Summary" for further details of the instruction set. TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction ADDWF REG3 1111 0100 0101 0110 ; is RAM location 0? ; 2nd operand holds address of REG2 0010 0100 0000 0000 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes ADDWF REG3 1111 0100 0101 0110 ; 2nd operand becomes NOP 0010 0100 0000 0000 4.8 ; is RAM location 0? Look-up Tables ; continue code Look-up tables are implemented two ways. These are: routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function. * Computed GOTO * Table Reads The offset value (value in WREG) specifies the number of bytes that the program counter should advance. 4.8.1 In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called EXAMPLE 4-4: MAIN: Note: The ADDWF PCL instruction does not update PCLATH and PCLATU. A read operation on PCL must be performed to update PCLATH and PCLATU. COMPUTED GOTO USING AN OFFSET VALUE ORG 0x0000 MOVLW 0x00 CALL TABLE ... TABLE ORG MOVF RLNCF ADDWF RETLW RETLW RETLW RETLW RETLW END DS39612B-page 46 0x8000 PCL, F W, W PCL `A' `B' `C' `D' `E' ; A simple read of PCL will update PCLATH, PCLATU ; Multiply by 2 to get correct offset in table ; Add the modified offset to force jump into table 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 4.8.2 TABLE READS/TABLE WRITES A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. Look-up table data may be stored 2 bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) specifies the byte address and the Table Latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time. A description of the table read/table write operation is shown in Section 5.0 "Flash Program Memory". 4.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-7 shows the data memory organization for the PIC18F6525/6621/8525/8621 devices. The data memory map is divided into 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user's application. The SFRs start at the last location of Bank 15 (0FFFh) and extend downwards. Any remaining space beyond the SFRs in the bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as `0's. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit address value that can be used to access any location in the data memory map without banking. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 "Access Bank" provides a detailed description of the Access RAM. 4.9.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indirectly. Indirect addressing operates using a File Select Register and corresponding Indirect File Operand. The operation of indirect addressing is shown in Section 4.12 "Indirect Addressing, INDF and FSR Registers". Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Data RAM is available for use as General Purpose Registers by all instructions. The top section of Bank 15 (F60h to FFFh) contains SFRs. All other banks of data memory contain GPRs, starting with Bank 0. 4.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 4-2 and Table 4-3. The SFRs can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations are unimplemented and read as `0's. The addresses for the SFRs are listed in Table 4-2. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. 2005 Microchip Technology Inc. DS39612B-page 47 PIC18F6525/6621/8525/8621 FIGURE 4-7: DATA MEMORY MAP FOR PIC18F6525/6621/8525/8621 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 Data Memory Map 00h Access RAM FFh 00h GPRs Bank 0 GPRs Bank 1 FFh 00h Bank 2 1FFh 200h GPRs 2FFh 300h FFh 00h Bank 3 GPRs FFh = 0100 000h 05Fh 060h 0FFh 100h Bank 4 3FFh 400h GPRs Access Bank 4FFh 500h Bank 5 to Bank 13 = 1110 = 1111 00h 5Fh Access RAM high 60h (SFRs) FFh Access RAM low GPRs DFFh E00h 00h Bank 14 GPRs FFh 00h Unused FFh SFRs Bank 15 EFFh F00h F5Fh F60h FFFh When `a' = 0, the BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When `a' = 1, the BSR is used to specify the RAM location that the instruction uses. DS39612B-page 48 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 4-2: Address SPECIAL FUNCTION REGISTER MAP Name Address Name (3) Address Name Address Name FFFh TOSU FDFh FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch MEMCON(2) FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh --(1) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(2) FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH(2) FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD FF4h PRODH FD4h --(1) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(2) FB0h PSPCON(4) F90h LATH(2) FF0h INTCON3 FEFh INDF0(3) INDF2 FD0h RCON FCFh TMR1H FAFh SPBRG1 F8Fh LATG FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG1 F8Eh LATF FEDh POSTDEC0(3) FCDh T1CON FADh TXREG1 F8Dh LATE FECh PREINC0(3) FCCh TMR2 FACh TXSTA1 F8Ch LATD FEBh PLUSW0(3) FCBh PR2 FABh RCSTA1 F8Bh LATC FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h PORTJ(2) FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2 F87h PORTH(2) FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h PORTG FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h PORTF FE4h PREINC1(3) FC4h ADRESH FA4h PIR3 F84h PORTE FE3h PLUSW1(3) FC3h ADRESL FA3h PIE3 F83h PORTD FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: 2: 3: 4: Unimplemented registers are read as `0'. This register is not available on PIC18F6525/6621 devices and reads as `0'. This is not a physical register. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 49 PIC18F6525/6621/8525/8621 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name F7Fh SPBRGH1 Address F5Fh Name (1) -- (1) Address F3Fh Name Address Name (1) F1Fh --(1) (1) -- F7Eh BAUDCON1 F5Eh -- F3Eh -- F1Eh --(1) F7Dh SPBRGH2 F5Dh --(1) F3Dh --(1) F1Dh --(1) F7Ch F5Ch --(1) F3Ch --(1) F1Ch --(1) F7Bh BAUDCON2 --(1) F5Bh -- (1) F3Bh -- (1) F1Bh --(1) F7Ah --(1) F5Ah --(1) F3Ah --(1) F1Ah --(1) (1) (1) F79h ECCP1DEL F59h -- F39h -- F19h --(1) F78h TMR4 F58h --(1) F38h --(1) F18h --(1) F77h PR4 F57h --(1) F37h --(1) F17h --(1) (1) (1) F76h T4CON F56h -- F36h -- F16h --(1) F75h CCPR4H F55h --(1) F35h --(1) F15h --(1) F34h --(1) F14h --(1) F74h CCPR4L F54h --(1) F73h CCP4CON F53h --(1) F33h --(1) F13h --(1) F72h CCPR5H F52h --(1) F32h --(1) F12h --(1) F31h --(1) F11h --(1) F71h CCPR5L F51h --(1) F70h CCP5CON F50h --(1) F30h --(1) F10h --(1) F2Fh --(1) F0Fh --(1) F6Fh SPBRG2 F4Fh --(1) F6Eh RCREG2 F4Eh --(1) F2Eh --(1) F0Eh --(1) F6Dh TXREG2 F4Dh --(1) F2Dh --(1) F0Dh --(1) F2Ch --(1) F0Ch --(1) F6Ch TXSTA2 F4Ch --(1) F6Bh RCSTA2 F4Bh --(1) F2Bh --(1) F0Bh --(1) F2Ah --(1) F0Ah --(1) F6Ah ECCP3AS F4Ah --(1) F69h ECCP3DEL F49h --(1) F29h --(1) F09h --(1) F68h ECCP2AS F48h --(1) F28h --(1) F08h --(1) F27h --(1) F07h --(1) F67h ECCP2DEL F47h --(1) F66h --(1) F46h --(1) F26h --(1) F06h --(1) F65h --(1) F45h --(1) F25h --(1) F05h --(1) F64h --(1) F44h --(1) F24h --(1) F04h --(1) F63h --(1) F43h --(1) F23h --(1) F03h --(1) F62h --(1) F42h --(1) F22h --(1) F02h --(1) F61h --(1) F41h --(1) F21h --(1) F01h --(1) F60h --(1) F40h --(1) F20h --(1) F00h --(1) Note 1: 2: 3: 4: Unimplemented registers are read as `0'. This register is not available on PIC18F6525/6621 devices and reads as `0'. This is not a physical register. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 50 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 4-3: File Name TOSU REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 -- -- -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 32, 42 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 32, 42 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 32, 42 STKPTR PCLATU Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR STKFUL STKUNF -- Return Stack Pointer 00-0 0000 32, 43 -- -- -- Holding Register for PC<20:16> ---0 0000 32, 44 PCLATH Holding Register for PC<15:8> 0000 0000 32, 44 PCL PC Low Byte (PC<7:0>) 0000 0000 32, 44 --00 0000 32, 69 TBLPTRU -- -- bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 32, 69 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 32, 69 TABLAT Program Memory Table Latch 0000 0000 32, 69 PRODH Product Register High Byte xxxx xxxx 32, 85 PRODL Product Register Low Byte xxxx xxxx 32, 85 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 32, 89 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 32, 90 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 32, 91 INTCON3 INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) N/A 56 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) N/A 56 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) N/A 56 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) N/A 56 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by value in WREG N/A 56 FSR0H Indirect Data Memory Address Pointer 0 High Byte ---- 0000 32, 56 FSR0L Indirect Data Memory Address Pointer 0 Low Byte -- -- -- -- xxxx xxxx 32, 56 WREG Working Register xxxx xxxx 32 INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) N/A 56 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) N/A 56 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) N/A 56 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) N/A 56 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by value in WREG N/A 56 FSR1H -- FSR1L -- -- -- Indirect Data Memory Address Pointer 1 High Byte ---- 0000 32, 56 xxxx xxxx 33, 56 ---- 0000 33, 55 Indirect Data Memory Address Pointer 1 Low Byte BSR -- INDF2 -- -- -- Bank Select Register N/A 56 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) N/A 56 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) N/A 56 Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read `0' in all other oscillator modes. Bit 21 of the TBLPTRU allows access to the device configuration bits. These registers are unused on PIC18F6525/6621 devices and read as `0'. RG5 is available only if MCLR function is disabled in configuration. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 51 PIC18F6525/6621/8525/8621 TABLE 4-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) N/A 56 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by value in WREG N/A 56 -- FSR2H FSR2L -- -- -- Indirect Data Memory Address Pointer 2 High Byte ---- 0000 33, 56 xxxx xxxx 33, 56 Indirect Data Memory Address Pointer 2 Low Byte STATUS -- -- TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte -- N OV Z DC C ---x xxxx 33, 58 0000 0000 33, 133 xxxx xxxx 33, 133 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 33, 131 OSCCON -- -- -- -- LOCK PLLEN SCS1 SCS0 ---- 0000 25, 33 LVDCON -- -- IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 33, 255 -- -- -- -- -- -- -- SWDTEN ---- ---0 33, 267 IPEN -- -- RI TO PD POR BOR 0--1 11qq 33, 59, 101 T0CON WDTCON RCON TMR1H Timer1 Register High Byte xxxx xxxx 33, 139 TMR1L Timer1 Register Low Byte xxxx xxxx 33, 139 0-00 0000 33, 139 T1CON RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TMR2 Timer2 Register 0000 0000 33, 142 PR2 Timer2 Period Register 1111 1111 33, 142 T2CON T2CKPS0 -000 0000 33, 142 SSPBUF MSSP Receive Buffer/Transmit Register -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 xxxx xxxx 33, 181 SSPADD MSSP Address Register in I2C Slave mode. MSSP Baud Rate Reload Register in I2C Master mode. 0000 0000 33, 181 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 33, 174 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 33, 175 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN SSPCON2 ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte 0000 0000 33, 185 xxxx xxxx 33, 241 xxxx xxxx 33, 241 ADCON0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 34, 233 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 34, 234 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 ADCON2 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte CCP3CON ECCP1AS CVRCON Legend: Note 1: 2: 3: 4: 5: P3M1 P3M0 DC3B1 DC2B0 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 CVREN CVROE CVRR CVRSS CCP1M2 CCP2M2 CCP1M1 CCP2M1 CCP1M0 CCP2M0 0-00 0000 34, 235 xxxx xxxx 34, 172 xxxx xxxx 34, 172 0000 0000 34, 157 xxxx xxxx 34, 172 xxxx xxxx 34, 172 0000 0000 34, 157 xxxx xxxx 34, 172 xxxx xxxx 34, 172 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 34, 157 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 34, 169 CVR3 CVR2 CVR1 CVR0 0000 0000 34, 249 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read `0' in all other oscillator modes. Bit 21 of the TBLPTRU allows access to the device configuration bits. These registers are unused on PIC18F6525/6621 devices and read as `0'. RG5 is available only if MCLR function is disabled in configuration. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 52 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 4-3: File Name CMCON REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 Value on POR, BOR Details on page: 0000 0000 34, 243 TMR3H Timer3 Register High Byte xxxx xxxx 34, 145 TMR3L Timer3 Register Low Byte xxxx xxxx 34, 145 T3CON PSPCON(5) RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 34, 145 IBF OBF IBOV PSPMODE -- -- -- -- 0000 ---- 34, 129 SPBRG1 Enhanced USART1 Baud Rate Generator Register Low Byte 0000 0000 34, 217 RCREG1 Enhanced USART1 Receive Register 0000 0000 34, 224 TXREG1 Enhanced USART1 Transmit Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH RCSTA1 SPEN RX9 SREN CREN ADDEN FERR EEADRH -- -- -- -- -- -- 0000 0000 34, 222 TRMT TX9D 0000 0010 34, 214 OERR RX9D 0000 000x 34, 215 ---- --00 34, 83 EE Addr Register High EEADR Data EEPROM Address Register 0000 0000 34, 83 EEDATA Data EEPROM Data Register 0000 0000 34, 83 EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 34, 83 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 34, 80 IPR3 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 35, 100 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 35, 94 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 35, 97 IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 35, 99 PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 35, 93 PIE2 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 35, 96 IPR1 PSPIP(5) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 35, 98 PIR1 PSPIF(5) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 35, 92 PIE1 PSPIE(5) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 35, 95 EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 0-00 --00 35, 71 1111 1111 35, 127 MEMCON(3) TRISJ(3) Data Direction Control Register for PORTJ TRISH(3) Data Direction Control Register for PORTH TRISG -- -- -- Data Direction Control Register for PORTG 1111 1111 35, 124 ---1 1111 35, 119 TRISF Data Direction Control Register for PORTF 1111 1111 35, 116 TRISE Data Direction Control Register for PORTE 1111 1111 35, 113 TRISD Data Direction Control Register for PORTD 1111 1111 35, 110 TRISC Data Direction Control Register for PORTC 1111 1111 35, 108 TRISB Data Direction Control Register for PORTB TRISA -- TRISA6(1) Data Direction Control Register for PORTA LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch LATH(3) Read PORTH Data Latch, Write PORTH Data Latch LATG -- -- -- Read PORTG Data Latch, Write PORTG Data Latch 1111 1111 35, 105 -111 1111 35, 121 xxxx xxxx 35, 127 xxxx xxxx 35, 124 ---x xxxx 35, 121 LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 35, 119 LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 35, 116 LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 35, 113 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 35, 110 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 35, 108 -xxx xxxx 35, 105 LATA -- Legend: Note 1: 2: 3: 4: 5: LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read `0' in all other oscillator modes. Bit 21 of the TBLPTRU allows access to the device configuration bits. These registers are unused on PIC18F6525/6621 devices and read as `0'. RG5 is available only if MCLR function is disabled in configuration. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 53 PIC18F6525/6621/8525/8621 TABLE 4-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: PORTJ(3) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 35, 127 PORTH(3) Read PORTH pins, Write PORTH Data Latch 0000 xxxx 35, 124 --xx xxxx 36, 121 PORTG -- -- RG5 (4) Read PORTG pins, Write PORTG Data Latch PORTF Read PORTF pins, Write PORTF Data Latch x000 0000 36, 119 PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 36, 116 PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 36, 113 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 36, 110 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 36, 108 -x0x 0000 36, 105 0000 0000 36, 217 PORTA RA6(1) -- SPBRGH1 BAUDCON1 SPBRGH2 Read PORTA pins, Write PORTA Data Latch(1) Enhanced USART1 Baud Rate Generator Register High Byte -- RCIDL -- SCKP BRG16 -- WUE ABDEN Enhanced USART2 Baud Rate Generator Register High Byte -1-0 0-00 36, 216 0000 0000 36, 217 BAUDCON2 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 36, 216 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 36, 168 TMR4 Timer4 Register 0000 0000 36, 148 PR4 Timer4 Period Register 1111 1111 36, 148 T4CON T4CKPS0 -000 0000 36, 147 CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 36, 153 CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 36, 153 CCP4CON -- -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 -- DC4B1 DC4B0 CCPR5H Capture/Compare/PWM Register 5 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte CCP5CON SPBRG2 -- -- DC5B1 DC5B0 CCP4M3 CCP5M3 TMR4ON CCP4M2 CCP5M2 T4CKPS1 CCP4M1 CCP5M1 CCP4M0 CCP5M0 Enhanced USART2 Baud Rate Generator Register Low Byte --00 0000 36, 149 xxxx xxxx 36, 153 xxxx xxxx 36, 153 --00 0000 36, 149 0000 0000 36, 217 RCREG2 Enhanced USART2 Receive Register 0000 0000 36, 224 TXREG2 Enhanced USART2 Transmit Register 0000 0000 36, 222 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 36, 222 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 36, 222 PSS3AC1 PSS3AC0 PSS3BD1 P3DC3 P3DC2 P3DC1 PSS2AC1 PSS2AC0 PSS2BD1 P2DC3 P2DC2 P2DC1 ECCP3AS ECCP3DEL ECCP2AS ECCP2DEL Legend: Note 1: 2: 3: 4: 5: ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 P3RSEN P3DC6 P3DC5 P3DC4 ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 P2RSEN P2DC6 P2DC5 P2DC4 PSS3BD0 0000 0000 P3DC0 36, 169 0000 0000 36, 168 PSS2BD0 0000 0000 36, 169 P2DC0 0000 0000 36, 168 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read `0' in all other oscillator modes. Bit 21 of the TBLPTRU allows access to the device configuration bits. These registers are unused on PIC18F6525/6621 devices and read as `0'. RG5 is available only if MCLR function is disabled in configuration. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 54 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 4.10 Access Bank 4.11 The Access Bank is an architectural enhancement, which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. This data memory region can be used for: * * * * * BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read `0's and writes will have no effect. Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all `0's and all writes are ignored. The STATUS register bits will be set/cleared as appropriate for the instruction performed. The Access Bank is comprised of the upper 160 bytes in Bank 15 (SFRs) and the lower 96 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 4-7 indicates the Access RAM areas. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank. This bit is denoted by the `a' bit (for access bit). A MOVFF instruction ignores the BSR since the 12-bit addresses are embedded into the instruction word. Section 4.12 "Indirect Addressing, INDF and FSR Registers" provides a description of indirect addressing which allows linear addressing of the entire RAM space. When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function Registers so that these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. FIGURE 4-8: Bank Select Register (BSR) DIRECT ADDRESSING Direct Addressing BSR<3:0> Bank Select(2) 7 From Opcode(3) 0 Location Select(3) 00h 01h 0Eh 0Fh 000h 100h E00h F00h 0FFh 1FFh EFFh FFFh Bank 14 Bank 15 Data Memory(1) Bank 0 Note 1: Bank 1 For register file map detail, see Table 4-2. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. 2005 Microchip Technology Inc. DS39612B-page 55 PIC18F6525/6621/8525/8621 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-9 shows the operation of indirect addressing. This shows the moving of the value to the data memory address specified by the value of the FSR register. Indirect addressing is possible by using one of the INDF registers. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = 0), will read 00h. Writing to the INDF register indirectly, results in a no operation (NOP). The FSR register contains a 12-bit address which is shown in Figure 4-10. The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 4-5 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions. EXAMPLE 4-5: NEXT HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR CLRF FSR0, 0x100 POSTINC0 BTFSS FSR0H, 1 GOTO CONTINUE NEXT ; ; ; ; ; ; ; ; Clear INDF register and inc pointer All done with Bank1? NO, clear next YES, continue There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12 bits wide. To store the 12 bits of addressing information, two 8-bit registers are required. These indirect addressing registers are: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads DS39612B-page 56 the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all `0's are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected. 4.12.1 INDIRECT ADDRESSING OPERATION Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation on one of these five registers determines how the FSR will be modified during indirect addressing. When data access is done to one of the five INDFn locations, the address selected will configure the FSRn register to: * Do nothing to FSRn after an indirect access (no change) - INDFn. * Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn. * Auto-increment FSRn after an indirect access (post-increment) - POSTINCn. * Auto-increment FSRn before an indirect access (pre-increment) - PREINCn. * Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn. When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect address causes the FSR to equal `0', the Z bit will not be set. Incrementing or decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a Stack Pointer in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. If an FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (Status bits are not affected). If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 4-9: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register BSR<3:0> Instruction Fetched Opcode FIGURE 4-10: 4 12 12 8 File FSR INDIRECT ADDRESSING Indirect Addressing 11 FSR Register 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-2. 2005 Microchip Technology Inc. DS39612B-page 57 PIC18F6525/6621/8525/8621 4.13 STATUS Register The STATUS register, shown in Register 4-3, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). REGISTER 4-3: It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 25-2. Note: The C and DC bits operate as the borrow and digit borrow bits respectively in subtraction. STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x -- -- -- N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as `0' bit 4 N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: bit 0 For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. C: Carry/Borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high- or low-order bit of the source register. Legend: DS39612B-page 58 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 4.14 RCON Register Note: The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 4-4: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 IPEN -- -- RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as `0' bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 59 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 60 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 5.0 FLASH PROGRAM MEMORY 5.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable, during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. * Table Read (TBLRD) * Table Write (TBLWT) Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 5-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 5.5 "Writing to Flash Program Memory". Figure 5-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 5-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2005 Microchip Technology Inc. DS39612B-page 61 PIC18F6525/6621/8525/8621 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 5.2 Table pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 5.5 "Writing to Flash Program Memory". Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers 5.2.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit, EEPGD, determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. Control bit, CFGS, determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 24.0 "Special Features of the CPU"). When clear, memory selection access is determined by EEPGD. DS39612B-page 62 The FREE bit, when set, will allow a program memory erase operation. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR) due to Reset values of zero. Note: During normal operation, the WRERR bit is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 63 PIC18F6525/6621/8525/8621 5.2.2 TABLAT - TABLE LATCH REGISTER 5.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. TBLPTR - TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer register (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the TBLPTR (TBLPTR<21:3>) will determine which program memory block of 8 bytes is written to. For more detail, see Section 5.5 "Writing to Flash Program Memory". The Table Pointer register (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the configuration bits. When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. The Table Pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 5-1. These operations on the TBLPTR only affect the low-order 21 bits. TABLE 5-1: TABLE POINTER BOUNDARIES Figure 5-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 5-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE - TBLPTR<20:6> WRITE - TBLPTR<21:3> READ - TBLPTR<21:0> DS39612B-page 64 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 5.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 5-4: TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 5-4 shows the interface between the internal program memory and the TABLAT. READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 5-1: FETCH TBLRD TBLPTR = xxxxx0 TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVFW MOVWF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD 2005 Microchip Technology Inc. ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data DS39612B-page 65 PIC18F6525/6621/8525/8621 5.4 5.4.1 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. 2. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. 3. 4. 5. 6. For protection, the write initiate sequence for EECON2 must be used. 7. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 5-2: FLASH PROGRAM MEMORY ERASE SEQUENCE 8. Load Table Pointer register with address of row being erased. Set the EECON1 register for the erase operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Re-enable interrupts. ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 AAh EECON2 EECON1, INTCON, ; ; ; ; ; ERASE_ROW Required Sequence DS39612B-page 66 EEPGD CFGS WREN FREE GIE point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55h WR GIE ; write AAh ; start erase (CPU stall) ; re-enable interrupts 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 5.5 Writing to Flash Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes because only FIGURE 5-5: the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device for byte or word operations. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxxx0 8 Holding Register TBLPTR = xxxxx7 TBLPTR = xxxxx2 TBLPTR = xxxxx1 Holding Register 8 Holding Register Holding Register Program Memory 5.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Do the row erase procedure. Load Table Pointer register with address of first byte being written. Write the first 8 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN to enable byte writes. 2005 Microchip Technology Inc. 8. 9. 10. 11. 12. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Repeat steps 6-14 seven times to write 64 bytes. 15. Verify the memory (table read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 5-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the eight bytes in the holding register. DS39612B-page 67 PIC18F6525/6621/8525/8621 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat MODIFY_WORD ; point to buffer ; update buffer word ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF BSF TBLRD*WRITE_BUFFER_BACK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF PROGRAM_LOOP MOVLW MOVWF WRITE_WORD_TO_HREGS MOVFF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EEPGD EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55h ; ; ; ; write AAh start erase (CPU stall) re-enable interrupts dummy read decrement 8 COUNTER_HI BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L ; number of write buffer groups of 8 bytes 8 COUNTER ; number of bytes in holding register POSTINC0, WREG ; ; ; ; ; TBLWT+* DECFSZ COUNTER BRA WRITE_WORD_TO_HREGS DS39612B-page 68 ; load TBLPTR with the base ; address of the memory block ; point to buffer get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD BCF EECON1, CFGS BSF EECON1, WREN BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE DECFSZ COUNTER_HI BRA PROGRAM_LOOP BCF EECON1, WREN Required Sequence 5.5.2 ; ; ; ; point to Flash program memory access Flash program memory enable write to memory disable interrupts ; write 55h ; ; ; ; write AAh start program (CPU stall) re-enable interrupts loop until done ; disable write to memory WRITE VERIFY 5.5.4 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 5.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION TABLE 5-2: Name TBLPTRU To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 24.0 "Special Features of the CPU" for more detail. 5.6 If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. PROTECTION AGAINST SPURIOUS WRITES Flash Program Operation During Code Protection See Section 24.0 "Special Features of the CPU" for details on code protection of Flash program memory. REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 Bit 6 -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Value on: POR, BOR Value on all other Resets --00 0000 --00 0000 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE 0000 000u EECON2 EEPROM Control Register 2 (not a physical register) INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x -- -- EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 EECON1 PIE2 Legend: Note 1: x = unknown, u = unchanged, r = reserved, -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. Bit 21 of the TBLPTRU allows access to device configuration bits. 2005 Microchip Technology Inc. DS39612B-page 69 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 70 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 6.0 EXTERNAL MEMORY INTERFACE 6.1 Note: The external memory interface is not implemented on PIC18F6525/6621 (64-pin) devices. The external memory interface is a feature of the PIC18F8525/8621 devices that allows the controller to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. The physical implementation of the interface uses 27 pins. These pins are reserved for external address/ data bus functions; they are multiplexed with I/O port pins on four ports. Three I/O ports are multiplexed with the address/data bus, while the fourth port is multiplexed with the bus control signals. The I/O port functions are enabled when the EBDIS bit in the MEMCON register is set (see Register 6-1). A list of the multiplexed pins and their functions is provided in Table 6-1. As implemented in the PIC18F8525/8621 devices, the interface operates in a similar manner to the external memory interface introduced on PIC18C601/801 microcontrollers. The most notable difference is that the interface on PIC18F8525/8621 devices only operates in 16-bit modes. The 8-bit mode is not supported. For a more complete discussion of the operating modes that use the external memory interface, refer to Section 4.1.1 "PIC18F6525/6621/8525/8621 Program Memory Modes". REGISTER 6-1: bit 6 bit 5-4 bit 3-2 bit 1-0 As previously noted, PIC18F8525/8621 controllers are capable of operating in any one of four program memory modes using combinations of on-chip and external program memory. The functions of the multiplexed port pins depends on the program memory mode selected, as well as the setting of the EBDIS bit. In Microprocessor Mode, the external bus is always active and the port pins have only the external bus function. In Microcontroller Mode, the bus is not active and the pins have their port functions only. Writes to the MEMCOM register are not permitted. In Microprocessor with Boot Block or Extended Microcontroller Mode, the external program memory bus shares I/O port functions on the pins. When the device is fetching or doing table read/table write operations on the external program memory space, the pins will have the external bus function. If the device is fetching and accessing internal program memory locations only, the EBDIS control bit will change the pins from external memory to I/O port functions. When EBDIS = 0, the pins function as the external bus. When EBDIS = 1, the pins function as I/O ports. MEMCON: MEMORY CONTROL REGISTER R/W-0 EBDIS bit 7 bit 7 Program Memory Modes and the External Memory Interface U-0 -- R/W-0 WAIT1 R/W-0 WAIT0 U-0 -- U-0 -- R/W-0 WM1 R/W-0 WM0 bit 0 EBDIS: External Bus Disable bit 1 = External system bus disabled, all external bus drivers are mapped as I/O ports 0 = External system bus enabled and I/O ports are disabled Unimplemented: Read as `0' WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY Unimplemented: Read as `0' WM1:WM0: TBLWRT Operation with 16-Bit Bus bits 1x = Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when TABLAT<1> written 01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate Note: The MEMCON register is unimplemented and reads all `0's when the device is in Microcontroller mode. Legend: R = Readable bit -n = Value at POR 2005 Microchip Technology Inc. W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS39612B-page 71 PIC18F6525/6621/8525/8621 If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports. TABLE 6-1: Name When the device is executing out of internal memory (EBDIS = 0) in Microprocessor with Boot Block mode or Extended Microcontroller mode, the control signals will NOT be active. They will go to a state where the AD<15:0> and A<19:16> are tri-state; the CE, OE, WRH, WRL, UB and LB signals are `1' and ALE and BA0 are `0'. PIC18F8525/8621 EXTERNAL BUS - I/O PORT FUNCTIONS Port Bit Function RD0/AD0 PORTD bit 0 Input/Output or System Bus Address bit 0 or Data bit 0 RD1/AD1 PORTD bit 1 Input/Output or System Bus Address bit 1 or Data bit 1 RD2/AD2 PORTD bit 2 Input/Output or System Bus Address bit 2 or Data bit 2 RD3/AD3 PORTD bit 3 Input/Output or System Bus Address bit 3 or Data bit 3 RD4/AD4 PORTD bit 4 Input/Output or System Bus Address bit 4 or Data bit 4 RD5/AD5 PORTD bit 5 Input/Output or System Bus Address bit 5 or Data bit 5 RD6/AD6 PORTD bit 6 Input/Output or System Bus Address bit 6 or Data bit 6 RD7/AD7 PORTD bit 7 Input/Output or System Bus Address bit 7 or Data bit 7 RE0/AD8 PORTE bit 0 Input/Output or System Bus Address bit 8 or Data bit 8 RE1/AD9 PORTE bit 1 Input/Output or System Bus Address bit 9 or Data bit 9 RE2/AD10 PORTE bit 2 Input/Output or System Bus Address bit 10 or Data bit 10 RE3/AD11 PORTE bit 3 Input/Output or System Bus Address bit 11 or Data bit 11 RE4/AD12 PORTE bit 4 Input/Output or System Bus Address bit 12 or Data bit 12 RE5/AD13 PORTE bit 5 Input/Output or System Bus Address bit 13 or Data bit 13 RE6/AD14 PORTE bit 6 Input/Output or System Bus Address bit 14 or Data bit 14 RE7/AD15 PORTE bit 7 Input/Output or System Bus Address bit 15 or Data bit 15 RH0/A16 PORTH bit 0 Input/Output or System Bus Address bit 16 RH1/A17 PORTH bit 1 Input/Output or System Bus Address bit 17 RH2/A18 PORTH bit 2 Input/Output or System Bus Address bit 18 RH3/A19 PORTH bit 3 Input/Output or System Bus Address bit 19 RJ0/ALE PORTJ bit 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin RJ1/OE PORTJ bit 1 Input/Output or System Bus Output Enable (OE) Control pin RJ2/WRL PORTJ bit 2 Input/Output or System Bus Write Low (WRL) Control pin RJ3/WRH PORTJ bit 3 Input/Output or System Bus Write High (WRH) Control pin RJ4/BA0 PORTJ bit 4 Input/Output or System Bus Byte Address bit 0 RJ5/CE PORTJ bit 5 Input/Output or System Bus Chip Enable (CE) Control pin RJ6/LB PORTJ bit 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin RJ7/UB PORTJ bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin DS39612B-page 72 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 6.2 16-Bit Mode The external memory interface implemented in PIC18F8525/8621 devices operates only in 16-bit mode. The mode selection is not software configurable but is programmed via the configuration bits. The WM1:WM0 bits in the MEMCON register determine three types of connections in 16-bit mode. They are referred to as: * 16-bit Byte Write * 16-bit Word Write * 16-bit Byte Select These three different configurations allow the designer maximum flexibility in using 8-bit and 16-bit memory devices. For all 16-bit modes, the Address Latch Enable (ALE) pin indicates that the address bits, A15:A0, are available on the external memory interface bus. Following the address latch, the Output Enable signal (OE) will enable both bytes of program memory at once to form a 16-bit instruction word. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in Sleep mode. FIGURE 6-1: In Byte Select mode, JEDEC standard Flash memories will require BA0 for the byte address line and one I/O line, to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the UB or LB signals for byte selection. 6.2.1 16-BIT BYTE WRITE MODE Figure 6-1 shows an example of 16-bit Byte Write mode for PIC18F8525/8621 devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F8X2X AD<7:0> (MSB) 373 A<19:0> D<15:8> (LSB) A<x:0> A<x:0> D<7:0> D<7:0> CE AD<15:8> 373 OE D<7:0> CE WR (1) OE WR(1) ALE A<19:16> CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 5.1 "Table Reads and Table Writes". 2005 Microchip Technology Inc. DS39612B-page 73 PIC18F6525/6621/8525/8621 6.2.2 16-BIT WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8525/8621 devices. This mode is used for word-wide memories which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of wordwide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses. During a TBLWT cycle to an even address (TBLPTR<0> = 0), the TABLAT data is transferred to a holding latch and the external address data bus is tristated for the data portion of the bus cycle. No write signals are activated. FIGURE 6-2: During a TBLWT cycle to an odd address (TBLPTR<0> = 1), the TABLAT data is presented on the upper byte of the AD15:AD0 bus. The contents of the holding latch are presented on the lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is unused. The signal on the BA0 pin indicates the LSb of the TBLPTR but it is left unconnected. Instead, the UB and LB signals are active to select both bytes. The obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. 16-BIT WORD WRITE MODE EXAMPLE PIC18F8X2X AD<7:0> 373 A<20:1> D<15:0> A<x:0> D<15:0> CE AD<15:8> JEDEC Word EPROM Memory OE WR(1) 373 ALE A<19:16> CE OE WRH Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 5.1 "Table Reads and Table Writes". DS39612B-page 74 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 6.2.3 16-BIT BYTE SELECT MODE Figure 6-3 shows an example of 16-bit Byte Select mode for PIC18F8525/8621 devices. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written based on the Least Significant bit of the TBLPTR register. FIGURE 6-3: Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory's BYTE/WORD pin to provide the select signal. They also use the BA0 signal from the controller as a byte address. JEDEC standard static RAM memories, on the other hand, use the UB or LB signals to select the byte. 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8X2X AD<7:0> 373 A<20:1> A<x:1> JEDEC Word Flash Memory D<15:0> D<15:0> 138(2) AD<15:8> 373 ALE CE A0 BYTE/WORD OE WR(1) A<19:16> OE WRH WRL A<20:1> A<x:1> BA0 JEDEC Word SRAM Memory I/O D<15:0> D<15:0> CE LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 5.1 "Table Reads and Table Writes". 2: Demultiplexing is only required when multiple memory devices are accessed. 2005 Microchip Technology Inc. DS39612B-page 75 PIC18F6525/6621/8525/8621 6.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 6-4 through Figure 6-6. FIGURE 6-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) Apparent Q Actual Q Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 00h A<19:16> 3AABh AD<15:0> Q4 Q1 Q4 Q2 Q4 Q3 Q4 Q4 0Ch 0E55h 9256h CF33h BA0 ALE OE WRH `1' `1' WRL `1' `1' CE `0' `0' 1 TCY Wait Memory Cycle Instruction Execution FIGURE 6-5: Opcode Fetch MOVLW 55h from 007556h Table Read of 92h from 199E67h TBLRD Cycle 1 TBLRD Cycle 2 EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0Ch A<19:16> CF33h AD<15:0> 9256h CE ALE OE Memory Cycle Opcode Fetch TBLRD* from 000100h Opcode Fetch MOVLW 55h from 000102h TBLRD 92h from 199E67h Instruction Execution INST(PC - 2) TBLRD Cycle 1 TBLRD Cycle 2 DS39612B-page 76 Opcode Fetch ADDLW 55h from 000104h MOVLW 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 6-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q4 Q1 Q2 3AAAh Q3 Q4 Q1 00h 00h A<19:16> AD<15:0> Q3 0003h 3AABh 0E55h CE ALE OE Memory Cycle Instruction Execution Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h INST(PC - 2) SLEEP 2005 Microchip Technology Inc. Sleep Mode, Bus Inactive DS39612B-page 77 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 78 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 7.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are five SFRs used to read and write the program and data EEPROM memory. These registers are: * * * * * EECON1 EECON2 EEDATA EEADRH EEADR The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write. EEADR and EEADRH hold the address of the EEPROM location being accessed. These devices have 1024 bytes of data EEPROM with an address range from 00h to 3FFh. The EEPROM data memory is rated for high erase/ write cycles. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to parameter D122 (Section 27.0 "Electrical Characteristics") for exact limits. 7.1 The address register pair can address up to a maximum of 1024 bytes of data EEPROM. The two Most Significant bits of the address are stored in EEADRH, while the remaining eight Least Significant bits are stored in EEADR. The six Most Significant bits of EEADRH are unused and are read as `0'. 7.2 EECON1 and EECON2 Registers EECON1 is the control register for EEPROM memory accesses. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the EEPROM write sequence. Control bits RD and WR initiate read and write operations, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at the completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. Note: During normal operation, the WRERR bit is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR) due to the Reset condition forcing the contents of the registers to zero. Note: 2005 Microchip Technology Inc. EEADR and EEADRH Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software. DS39612B-page 79 PIC18F6525/6621/8525/8621 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration or Calibration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: DS39612B-page 80 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>), clear the CFGS EXAMPLE 7-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF MOVF 7.4 DATA EEPROM READ DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W ; ; ; ; ; ; ; ; Upper bits of Data Memory Address to read Lower bits of Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read W = EEDATA Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADRH:EEADR register pair and the data written to the EEDATA register. Then the sequence in Example 7-2 must be followed to initiate the write cycle. The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code EXAMPLE 7-2: Required Sequence control bit (EECON1<6>) and then set the RD control bit (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation). execution (i.e., runaway programs). The WREN bit should be kept clear at all times except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADRH, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Write Complete Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software. DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, CFGS EECON1, WREN ; ; ; ; ; ; ; ; ; BCF MOVLW MOVWF MOVLW MOVWF BSF BSF INTCON, GIE 0x55 EECON2 0xAA EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; BCF EECON1, WREN ; User code execution ; Disable writes on write complete (EEIF set) 2005 Microchip Technology Inc. Upper bits of Data Memory Address to write Lower bits of Data Memory Address to write Data Memory Value to write Point to DATA memory Access EEPROM Enable writes Disable Interrupts Write 55h Write AAh Set WR bit to begin write Enable Interrupts DS39612B-page 81 PIC18F6525/6621/8525/8621 7.5 Write Verify 7.7 Operation During Code-Protect Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Data EEPROM memory has its own code-protect mechanism. External read and write operations are disabled if either of these mechanisms are enabled. Refer to Section 24.0 "Special Features of the CPU", for additional information. 7.6 7.8 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. Using the Data EEPROM The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF CLRF BCF BCF BCF BSF EEADR EEADRH EECON1, EECON1, INTCON, EECON1, BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA INCFSZ BRA EECON1, RD 55h EECON2 AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F Loop EEADRH, F Loop BCF BSF EECON1, WREN INTCON, GIE CFGS EEPGD GIE WREN Loop DS39612B-page 82 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write AAh Set WR bit to begin write Wait for write to complete Increment Not zero, Increment Not zero, address do it again the high address do it again ; Disable writes ; Enable interrupts 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 7-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 INTCON GIE/GIEH EEADRH -- Bit 6 Bit 5 PEIE/GIEL TMR0IE -- -- Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF -- -- -- Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets INT0IF RBIF 0000 000x 0000 000u EE Addr Register High ---- --00 ---- --00 EEADR Data EEPROM Address Register 0000 0000 0000 0000 EEDATA Data EEPROM Data Register 0000 0000 0000 0000 EECON2 Data EEPROM Control Register 2 (not a physical register) -- -- xx-0 x000 uu-0 u000 EEPGD CFGS -- FREE WRERR WREN WR RD IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000 EECON1 PIE2 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. 2005 Microchip Technology Inc. DS39612B-page 83 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 84 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction 8.2 Operation Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. An 8 x 8 hardware multiplier is included in the ALU of the PIC18F6525/6621/8525/8621 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored in the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the ALUSTA register. Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the signed bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. EXAMPLE 8-1: Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: 8 x 8 UNSIGNED MULTIPLY ROUTINE MOVF ARG1, W MULWF ARG2 * Higher computational throughput * Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. ; ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY ROUTINE MOVF ARG1, W MULWF ARG2 Table 8-1 shows a performance comparison between Enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply. BTFSC ARG2, SB SUBWF PRODH, F MOVF ARG2, W BTFSC ARG1, SB SUBWF PRODH, F TABLE 8-1: ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 Test Sign Bit PRODH = PRODH - ARG2 PERFORMANCE COMPARISON Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed ; ; ; ; ; ; ; ; ; ; Program Memory (Words) Cycles (Max) Without hardware multiply 13 Hardware multiply 1 Without hardware multiply 33 Hardware multiply 6 Without hardware multiply Hardware multiply Multiply Method Time @ 40 MHz @ 10 MHz @ 4 MHz 69 6.9 s 27.6 s 69 s 1 100 ns 400 ns 1 s 91 9.1 s 36.4 s 91 s 6 600 ns 2.4 s 6 s 21 242 24.2 s 96.8 s 242 s 24 24 2.4 s 9.6 s 24 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s Hardware multiply 36 36 3.6 s 14.4 s 36 s 2005 Microchip Technology Inc. DS39612B-page 85 PIC18F6525/6621/8525/8621 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8-1: RES3:RES0 = = EXAMPLE 8-3: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) EQUATION 8-2: RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216) EXAMPLE 8-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L,W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ARG1H * ARG2L -> PRODH:PRODL Add cross products Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the signed bits of the arguments, each argument pairs' Most Significant bit (MSb) is tested and the appropriate subtractions are done. DS39612B-page 86 ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ; ; MOVF MULWF ; ; ; ; ; ; ; ; ; ; 16 x 16 SIGNED MULTIPLY ROUTINE ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 9.0 INTERRUPTS The PIC18F6525/6621/8525/8621 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. The high priority interrupt vector is at 000008h, while the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation. They are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used) which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits. 2005 Microchip Technology Inc. DS39612B-page 87 PIC18F6525/6621/8525/8621 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Sleep mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit GIEH/GIE TMR1IF TMR1IE TMR1IP IPEN IPEN XXXXIF XXXXIE XXXXIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP RBIF RBIE RBIP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts DS39612B-page 88 Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP GIEL/PEIE GIE/GEIH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN (RCON<7>) = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN (RCON<7>) = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 89 PIC18F6525/6621/8525/8621 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Note: DS39612B-page 90 x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Note: 2005 Microchip Technology Inc. x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39612B-page 91 PIC18F6525/6621/8525/8621 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request Flag registers (PIR1, PIR2 and PIR3). REGISTER 9-4: 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 7 bit 0 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: USART1 Receive Interrupt Flag bit 1 = The USART1 receive buffer, RCREGx, is full (cleared when RCREGx is read) 0 = The USART1 receive buffer is empty bit 4 TX1IF: USART1 Transmit Interrupt Flag bit 1 = The USART1 transmit buffer, TXREGx, is empty (cleared when TXREGx is written) 0 = The USART1 transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: DS39612B-page 92 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed bit 5 Unimplemented: Read as `0' bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete, or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred while the MSSP module (configured in I2C Master mode) was transmitting (must be cleared in software) 0 = No bus collision occurred bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 or TMR3 register capture occurred (must be cleared in software) 0 = No TMR1 or TMR3 register capture occurred Compare mode: 1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 93 PIC18F6525/6621/8525/8621 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = The USART2 receive buffer, RCREGx, is full (cleared when RCREGx is read) 0 = The USART2 receive buffer is empty bit 4 TX2IF: USART2 Transmit Interrupt Flag bit 1 = The USART2 transmit buffer, TXREGx, is empty (cleared when TXREGx is written) 0 = The USART2 transmit buffer is full bit 3 TMR4IF: TMR3 Overflow Interrupt Flag bit 1 = TMR4 register overflowed (must be cleared in software) 0 = TMR4 register did not overflow bit 2-0 CCPxIF: CCPx Interrupt Flag bit (ECCP3, CCP4 and CCP5) Capture mode: 1 = A TMR1 or TMR3 register capture occurred (must be cleared in software) 0 = No TMR1 or TMR3 register capture occurred Compare mode: 1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend: DS39612B-page 94 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When the IPEN bit (RCON<7>) is `0', the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 7 bit 0 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: USART1 Receive Interrupt Enable bit 1 = Enables the USART1 receive interrupt 0 = Disables the USART1 receive interrupt bit 4 TX1IE: USART1 Transmit Interrupt Enable bit 1 = Enables the USART1 transmit interrupt 0 = Disables the USART1 transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 95 PIC18F6525/6621/8525/8621 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as `0' bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enables the write operation interrupt 0 = Disables the write operation interrupt bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enables the bus collision interrupt 0 = Disables the bus collision interrupt bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enables the Low-Voltage Detect interrupt 0 = Disables the Low-Voltage Detect interrupt bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enables the ECCP2 interrupt 0 = Disables the ECCP2 interrupt Legend: DS39612B-page 96 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the USART2 receive interrupt 0 = Disables the USART2 receive interrupt bit 4 TX2IE: USART2 Transmit Interrupt Enable bit 1 = Enables the USART2 transmit interrupt 0 = Disables the USART2 transmit interrupt bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt bit 2-0 CCPxIE: CCPx Interrupt Enable bit (ECCP3, CCP4 and CCP5) 1 = Enables the CCPx interrupt 0 = Disables the CCPx interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 97 PIC18F6525/6621/8525/8621 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 7 bit 0 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: USART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: USART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: DS39612B-page 98 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as `0' bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 99 PIC18F6525/6621/8525/8621 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5 RC2IP: USART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: USART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 2-0 CCPxIP: CCPx Interrupt Priority bit (ECCP3, CCP4 and CCP5) 1 = High priority 0 = Low priority Legend: DS39612B-page 100 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 9.5 RCON Register The RCON register contains the IPEN bit which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14 "RCON Register". REGISTER 9-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN -- -- RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16 Compatibility mode) bit 6-5 Unimplemented: Read as `0' bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 4-4. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-4. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register 4-4. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-4. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 101 PIC18F6525/6621/8525/8621 9.6 INT0 Interrupt 9.8 External interrupts on the RB0/INT0/FLT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered; either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE. Flag bit, INTxF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from Sleep if bit INTxIE was set prior to going into Sleep. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. The interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the interrupt priority bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0; it is always a high priority interrupt source. 9.7 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 9.9 Context Saving During Interrupts During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 4.3 "Fast Register Stack"), the user may need to save the WREG, STATUS and BSR registers in software. Depending on the user's application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L registers (FFFFh 0000h) will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 "Timer0 Module" for further details on the Timer0 module. EXAMPLE 9-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF SAVING STATUS, WREG AND BSR REGISTERS IN RAM W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR located anywhere ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS DS39612B-page 102 ; Restore BSR ; Restore WREG ; Restore STATUS 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 10.0 I/O PORTS 10.1 Depending on the device selected, there are either seven or nine I/O ports available on PIC18F6525/6621/ 8525/8621 devices. Some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (data direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch register) The Data Latch (LAT) register is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified version of a generic I/O port and its operation is shown in Figure 10-1. FIGURE 10-1: SIMPLIFIED BLOCK DIAGRAM OF PORT/LAT/ TRIS OPERATION RD LAT TRIS PORTA is a 7-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register, read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/ T0CKI pin is a Schmitt Trigger input and an open-drain output. All other RA port pins have TTL input levels and full CMOS output drivers. The RA6 pin is only enabled as a general I/O pin in ECIO and RCIO Oscillator modes. The other PORTA pins are multiplexed with analog inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Note: D WR LAT + WR Port Q CK Data Latch Data Bus RD Port I/O pin PORTA, TRISA and LATA Registers On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as `0'. RA6 and RA4 are configured as digital inputs. The TRISA register controls the direction of the RA pins even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 10-1: CLRF CLRF MOVLW MOVWF MOVLW MOVWF 2005 Microchip Technology Inc. PORTA ; ; ; LATA ; ; ; 0x0F ; ADCON1 ; 0x0F ; ; ; TRISA ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<6:4> as outputs DS39612B-page 103 PIC18F6525/6621/8525/8621 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS FIGURE 10-3: BLOCK DIAGRAM OF RA4/T0CKI PIN RD LATA RD LATA Data Bus D WR LATA or PORTA Data Bus Q WR LATA or PORTA VDD CK Q P WR TRISA N Q I/O pin(1) WR TRISA CK Q CK Q N Data Latch Data Latch D D VSS Analog Input Mode Q TRIS Latch D Q CK Q I/O pin(1) VSS Schmitt Trigger Input Buffer TRIS Latch RD TRISA RD TRISA Q D TTL Input Buffer Q D ENEN EN RD PORTA RD PORTA TMR0 Clock Input To A/D Converter and LVD Modules Note 1: Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 10-4: I/O pins have protection diodes to VDD and VSS. BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O) ECRA6 or RCRA6 Enable Data Bus RD LATA WR LATA or PORTA D Q CK Q VDD P Data Latch WR TRISA D Q CK Q N I/O pin(1) VSS TRIS Latch TTL Input Buffer RD TRISA ECRA6 or RCRA6 Enable Q D EN RD PORTA Note 1: DS39612B-page 104 I/O pins have protection diodes to VDD and VSS. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 10-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output, analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output, analog input or VREF+. RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open-drain type. RA5/AN4/LVDIN bit 5 TTL Input/output, analog input or Low-Voltage Detect input. OSC2/CLKO/RA6 bit 6 TTL OSC2, clock output or I/O pin Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR -- RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000 -- LATA6(1) LATA Data Output Register -xxx xxxx -uuu uuuu TRISA -- TRISA6(1) PORTA Data Direction Register -111 1111 -111 1111 ADCON1 -- -- Name PORTA LATA VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, -- = unimplemented locations read as `0'. Shaded cells are not used by PORTA. Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read `0' in all other oscillator modes. 2005 Microchip Technology Inc. DS39612B-page 105 PIC18F6525/6621/8525/8621 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register, read and write the latched output value for PORTB. EXAMPLE 10-2: CLRF PORTB CLRF LATB MOVLW 0xCF MOVWF TRISB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. For PIC18F8525/8621 devices, RB3 can be configured by the configuration bit, CCP2MX, as the alternate peripheral pin for the ECCP2 module. This is only available when the device is configured in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller operating modes. The RB5 pin is used as the LVP programming pin. When the LVP configuration bit is programmed, this pin loses the I/O function and becomes a programming test function. Note: When LVP is enabled, the weak pull-up on RB5 is disabled. FIGURE 10-5: BLOCK DIAGRAM OF RB7:RB4 PINS VDD RBPU(2) Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, these pins are configured as digital inputs. Four of the PORTB pins (RB3:RB0) are the external interrupt pins, INT3 through INT0. In order to use these pins as external interrupts, the corresponding TRISB bit must be set to `1'. The other four PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB (except with the MOVFF instruction). Clear flag bit RBIF. DS39612B-page 106 Weak P Pull-up Data Bus WR LATB or PORTB Data Latch D Q I/O pin(1) CK TRIS Latch D WR TRISB Q TTL Input Buffer CK ST Buffer RD TRISB RD LATB Latch Q D RD PORTB EN Q1 Set RBIF Q D RD PORTB From other RB7:RB4 pins EN Q3 RB7:RB5 in Serial Programming Mode Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch D Q Data Bus WR LATB or WR PORTB I/O pin(1) CK TRIS Latch D WR TRISB Q TTL Input Buffer CK RD TRISB Q D RD PORTB EN INTx Schmitt Trigger Buffer Note 1: 2: FIGURE 10-7: RD Port I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). BLOCK DIAGRAM OF RB3 PIN VDD RBPU(2) CCP2MX Weak P Pull-up ECCP Output(3) 1 VDD P Enable(3) ECCP Output Data Bus WR LATB or WR PORTB 0 Data Latch D I/O pin(1) Q N CK VSS TRIS Latch D WR TRISB CK TTL Input Buffer Q RD TRISB RD LATB Q D RD PORTB EN RD PORTB ECCP2 or INT3 Schmitt Trigger Buffer Note 1: 2: 3: CCP2MX = 0 I/O pin has diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). For PIC18F8525/8621 parts, the ECCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode. 2005 Microchip Technology Inc. DS39612B-page 107 PIC18F6525/6621/8525/8621 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT0/FLT0 bit 0 TTL/ST(1) Input/output pin or external interrupt input 0, ECCP1 PWM Fault input. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt input 1. Internal software programmable weak pull-up. RB2/INT2 bit 2 TTL/ST(1) Input/output pin or external interrupt input 2. Internal software programmable weak pull-up. RB3/INT3/ ECCP2(3)/P2A(3) bit 3 TTL/ST(4) Input/output pin, external interrupt input 3, Enhanced Capture 2 input/ Compare 2 output/PWM 2 output or Enhanced PWM output P2A. Internal software programmable weak pull-up. RB4/KBI0 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5/KBI1/PGM bit 5 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-Voltage ICSPTM enable pin. RB6/KBI2/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7/KBI3/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: Note 1: 2: 3: 4: TTL = TTL input, ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. Valid for PIC18F8525/8621 devices in all operating modes except Microcontroller mode when CCP2MX is not set. RC1 is the default assignment for ECCP2/PA2 when CCP2MX is set in all devices; RE7 is the alternate assignment for PIC18F8525/8621 devices in Microcontroller mode when CCP2MX is clear. This buffer is a Schmitt Trigger input when configured as the ECCP2 input. TABLE 10-4: Name PORTB Function SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP Legend: TMR0IF INT0IF RBIF INTEDG1 INTEDG2 INTEDG3 TMR0IP TMR0IE INT3IP RBIP 1111 1111 1111 1111 INT2IF INT1IF 1100 0000 1100 0000 INT3IE INT0IE INT2IE RBIE INT1IE INT3IF 0000 000x 0000 000u x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS39612B-page 108 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 10.3 PORTC, TRISC and LATC Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). RC1 is normally configured by configuration bit, CCP2MX, as the default peripheral pin of the ECCP2 module (default/erased state, CCP2MX = 1). EXAMPLE 10-3: The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register, read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 10-5). PORTC pins have Schmitt Trigger input buffers. CLRF PORTC CLRF LATC MOVLW 0xCF MOVWF TRISC When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs On a Power-on Reset, these pins are configured as digital inputs. FIGURE 10-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORTC/Peripheral Out Select Peripheral Data Out VDD 0 P RD LATC 1 Data Bus WR LATC or WR PORTC D Q CK Q I/O pin(1) Data Latch D WR TRISC CK Q TRIS Latch TRIS OVERRIDE N Q VSS TRIS Override Logic Pin Override Peripheral RC0 Yes Timer1 Oscillator for Timer1/Timer3 RC1 Yes Timer1 OSC for Timer1/Timer3, ECCP2 I/O RC2 Yes ECCP1 I/O RC3 Yes SPITM/I2CTM Master Clock RC4 Yes I2C Data Out RD TRISC Schmitt Trigger Peripheral Output Enable(2) Q D EN RD PORTC Peripheral Data In Note 1: 2: I/O pins have diode protection to VDD and VSS. Peripheral output enable is only active if peripheral select is active. 2005 Microchip Technology Inc. RC5 Yes SPI Data Out RC6 Yes USART1 Async Xmit, Sync Clock RC7 Yes USART1 Sync Data Out DS39612B-page 109 PIC18F6525/6621/8525/8621 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. RC1/T1OSI/ ECCP2(1)/P2A(1) bit 1 ST Input/output port pin, Timer1 oscillator input, Enhanced Capture 2 input/Compare 2 output/PWM 2 output or Enhanced PWM output P2A. RC2/ECCP1/P1A bit 2 ST Input/output port pin, Enhanced Capture 1 input/Compare 1 output/ PWM 1 output or Enhanced PWM output P1A. RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPITM and I2CTM modes. RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode). RC5/SDO bit 5 ST Input/output port pin or synchronous serial port data output. RC6/TX1/CK1 bit 6 ST Input/output port pin, Addressable USART1 Asynchronous Transmit or Addressable USART1 Synchronous Clock. RC7/RX1/DT1 bit 7 ST Input/output port pin, Addressable USART1 Asynchronous Receive or Addressable USART1 Synchronous Data. Legend: ST = Schmitt Trigger input Note 1: Valid when CCP2MX is set in all devices and in all operating modes (default). RE7 is the alternate assignment for ECCP2/P2A for all PIC18F6525/6621 devices and PIC18F8525/8621 devices in Microcontroller modes when CCP2MX is not set; RB3 is the alternate assignment for PIC18F8525/8621 devices in all other operating modes. TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu LATC LATC Data Output Register xxxx xxxx uuuu uuuu TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged DS39612B-page 110 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 10.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register, read and write the latched output value for PORTD. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: FIGURE 10-9: PORTD BLOCK DIAGRAM IN I/O PORT MODE RD LATD Data Bus D WR LATD or PORTD Q I/O pin(1) CK Data Latch D WR TRISD Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRISD On a Power-on Reset, these pins are configured as digital inputs. Q PORTD is multiplexed with the system bus as the external memory interface. I/O port functions are only available when the system bus is disabled by setting the EBDIS bit in the MEMCOM register (MEMCON<7>). When operating as the external memory interface, PORTD is the low-order byte of the multiplexed address/data bus (AD7:AD0). D ENEN RD PORTD Note 1: I/O pins have diode protection to VDD and VSS. PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.10 "Parallel Slave Port" for additional information on the Parallel Slave Port (PSP). EXAMPLE 10-4: CLRF PORTD CLRF LATD MOVLW 0xCF MOVWF TRISD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs 2005 Microchip Technology Inc. DS39612B-page 111 PIC18F6525/6621/8525/8621 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTD RD LATD Data Bus D WR LATD or PORTD CK Q Port Data I/O pin(1) 0 1 Data Latch D WR TRISD Q CK TRIS Latch TTL Input Buffer RD TRISD System Bus Control Bus Enable Data/TRIS Out Drive Bus Instruction Register Instruction Read Note 1: DS39612B-page 112 I/O pins have protection diodes to VDD and VSS. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 10-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/AD0(2)/PSP0 bit 0 ST/TTL(1) Input/output port pin, address/data bus bit 0 or Parallel Slave Port bit 0. bit 1 ST/TTL (1) Input/output port pin, address/data bus bit 1 or Parallel Slave Port bit 1. (1) Input/output port pin, address/data bus bit 2 or Parallel Slave Port bit 2. RD1/AD1(2) /PSP1 (2) RD2/AD2 /PSP2 bit 2 ST/TTL RD3/AD3(2)/PSP3 bit 3 ST/TTL(1) Input/output port pin, address/data bus bit 3 or Parallel Slave Port bit 3. /PSP4 bit 4 ST/TTL (1) Input/output port pin, address/data bus bit 4 or Parallel Slave Port bit 4. RD5/AD5(2)/PSP5 bit 5 ST/TTL(1) Input/output port pin, address/data bus bit 5 or Parallel Slave Port bit 5. bit 6 ST/TTL(1) Input/output port pin, address/data bus bit 6 or Parallel Slave Port bit 6. bit 7 (1) Input/output port pin, address/data bus bit 7 or Parallel Slave Port bit 7. RD4/AD4(2) (2) RD6/AD6 /PSP6 RD7/AD7(2) /PSP7 ST/TTL Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. 2: External memory interface functions are only available on PIC18F8525/8621 devices. TABLE 10-8: Name PORTD SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu LATD LATD Data Output Register TRISD PORTD Data Direction Register 1111 1111 1111 1111 PSPCON(1) IBF OBF IBOV PSPMODE -- -- -- -- 0000 ---- 0000 ---- MEMCON(2) EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 0-00 --00 0-00 --00 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by PORTD. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2: This register is unused on PIC18F6525/6621 devices and reads as `0'. 2005 Microchip Technology Inc. DS39612B-page 113 PIC18F6525/6621/8525/8621 10.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. PORTE is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTE is multiplexed with the ECCP module (Table 10-9). On PIC18F8525/8621 devices, PORTE is also multiplexed with the system bus as the external memory interface; the I/O bus is available only when the system bus is disabled by setting the EBDIS bit in the MEMCON register (MEMCON<7>). If the device is configured in Microprocessor or Extended Microcontroller mode, then the PORTE<7:0> becomes the high byte of the address/ data bus for the external program memory interface. In Microcontroller mode, the PORTE<2:0> pins become the control inputs for the Parallel Slave Port when bit PSPMODE (PSPCON<4>) is set. (Refer to Section 4.1.1 "PIC18F6525/6621/8525/8621 Program Memory Modes" for more information.) DS39612B-page 114 When the Parallel Slave Port is active, three PORTE pins (RE0/AD8/RD/P2D, RE1/AD9/WR/P2C and RE2/ AD10/CS/P2B) function as its control inputs. This automatically occurs when the PSPMODE bit (PSPCON<4>) is set. Users must also make certain that bits TRISE<2:0> are set to configure the pins as digital inputs and the ADCON1 register is configured for digital I/O. The PORTE PSP control functions are summarized in Table 10-9. Pin RE7 can be configured as the alternate peripheral pin for the ECCP2 module when the device is operating in Microcontroller mode. This is done by clearing the configuration bit, CCP2MX, in the CONFIG3H Configuration register (CONFIG3H<0>). Note: For PIC18F8525/8621 (80-pin) devices operating in Extended Microcontroller mode, PORTE defaults to the system bus on Power-on Reset. EXAMPLE 10-5: CLRF PORTE CLRF LATE MOVLW 0x03 MOVWF TRISE INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE1:RE0 as inputs RE7:RE2 as outputs 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE Peripheral Out Select Peripheral Data Out VDD 0 P RD LATE 1 Data Bus WR LATE or WR PORTE D Q CK Q Data Latch WR TRISE D Q CK Q I/O pin(1) N VSS TRIS Override TRIS OVERRIDE TRIS Latch Pin Override Peripheral RE0 Yes External Bus RE1 Yes External Bus RE2 Yes External Bus RE3 Yes External Bus RE4 Yes External Bus RD PORTE RE5 Yes External Bus Peripheral Data In RE6 Yes External Bus Note 1: I/O pins have diode protection to VDD and VSS. RE7 Yes External Bus RD TRISE Schmitt Trigger Peripheral Enable Q D EN FIGURE 10-12: PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTE RD LATE Data Bus D WR LATE or PORTE CK Q Port Data I/O pin(1) 0 1 Data Latch D WR TRISE Q CK TRIS Latch TTL Input Buffer RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS. 2005 Microchip Technology Inc. DS39612B-page 115 PIC18F6525/6621/8525/8621 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/AD8/RD/P2D bit 0 ST/TTL(1) Input/output port pin, address/data bit 8, read control for Parallel Slave Port or Enhanced PWM 2 output P2D For RD (PSP Control mode): 1 = Not a read operation 0 = Read operation, reads PORTD register (if chip selected) RE1/AD9/WR/P2C bit 1 ST/TTL(1) Input/output port pin, address/data bit 9, write control for Parallel Slave Port or Enhanced PWM 2 output P2C For WR (PSP Control mode): 1 = Not a write operation 0 = Write operation, writes PORTD register (if chip selected) RE2/AD10/CS/P2B bit 2 ST/TTL(1) Input/output port pin, address/data bit 10, chip select control for Parallel Slave Port or Enhanced PWM 2 output P2B For CS (PSP Control mode): 1 = Device is not selected 0 = Device is selected RE3/AD11/P3C(2) bit 3 ST/TTL(1) Input/output port pin, address/data bit 11 or Enhanced PWM 3 output P3C. RE4/AD12/P3B(2) bit 4 ST/TTL(1) Input/output port pin, address/data bit 12 or Enhanced PWM 3 output P3B. RE5/AD13/P1C(2) bit 5 ST/TTL(1) Input/output port pin, address/data bit 13 or Enhanced PWM 1 output P1C. RE6/AD14/P1B(2) bit 6 ST/TTL(1) Input/output port pin, address/data bit 14 or Enhanced PWM 1 output P1B. RE7/AD15/ ECCP2(3)/P2A(3) bit 7 ST/TTL(1) Input/output port pin, address/data bit 15, Enhanced Capture 2 input/ Compare 2 output/PWM 2 output or Enhanced PWM 2 output P2A. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O or CCP/ECCP modes and TTL buffers when in System Bus or PSP Control modes. 2: Valid for all PIC18F6525/6621 devices and PIC18F8525/8621 devices when ECCPMX is set. Alternate assignments for P1B/P1C/P3B/P3C are RH7, RH6, RH5 and RH4, respectively. 3: Valid for all PIC18F6525/6621 devices and PIC18F8525/8621 devices in Microcontroller mode when CCP2MX is not set. RC1 is the default assignment for ECCP2/P2A for all devices in Microcontroller mode when CCP2MX is set; RB3 is the alternate assignment for PIC18F8525/8621 devices in operating modes except Microcontroller mode when CCP2MX is not set. TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on: POR, BOR Value on all other Resets PORTE Data Direction Control Register 1111 1111 1111 1111 PORTE Read PORTE pin/Write PORTE Data Latch xxxx xxxx uuuu uuuu LATE Read PORTE Data Latch/Write PORTE Data Latch xxxx xxxx uuuu uuuu MEMCON(1) EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 0-00 --00 0000 --00 PSPCON(2) IBF OBF IBOV PSPMODE -- -- -- -- 0000 ---- 0000 ---- Name TRISE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by PORTE. Note 1: This register is unused on PIC18F6525/6621 devices and reads as `0'. 2: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 116 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 10.6 EXAMPLE 10-6: PORTF, LATF and TRISF Registers CLRF PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). CLRF MOVLW MOVWF MOVLW MOVWF MOVLW Read-modify-write operations on the LATF register, read and write the latched output value for PORTF. PORTF is multiplexed with several analog peripheral functions, including the A/D converter inputs and comparator inputs, outputs and voltage reference. MOVWF Note 1: On a Power-on Reset, the RF6:RF0 pins are configured as inputs and read as `0'. PORTF ; ; ; LATF ; ; ; 0x07 ; CMCON ; 0x0F ; ADCON1 ; 0xCF ; ; ; TRISF ; ; ; INITIALIZING PORTF Initialize PORTF by clearing output data latches Alternate method to clear output data latches Turn off comparators Set PORTF as digital I/O Value used to initialize data direction Set RF3:RF0 as inputs RF5:RF4 as outputs RF7:RF6 as inputs 2: To configure PORTF as digital I/O, turn off comparators and set ADCON1 value. FIGURE 10-13: PORTF RF1/AN6/C2OUT, RF2/AN7/C1OUT PINS BLOCK DIAGRAM PORT/Comparator Select Comparator Data Out VDD 0 P RD LATF Data Bus WR LATF or WR PORTF D CK Q I/O pin Q Data Latch D WR TRISF 1 N Q VSS CK Q TRIS Latch Analog Input Mode RD TRISF Schmitt Trigger Q D EN RD PORTF To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS. 2005 Microchip Technology Inc. DS39612B-page 117 PIC18F6525/6621/8525/8621 FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM D WR LATF or WR PORTF D WR LATF or WR PORTF CK Q VDD CK Data Bus Q P D VSS Analog Input Mode Q TRIS Latch Q Schmitt Trigger Input Buffer I/O pin WR TRISF CK I/O pin D N Q Q Data Latch Data Latch WR TRISF RF7 PIN BLOCK DIAGRAM RD LATF RD LATF Data Bus FIGURE 10-15: CK TRIS Latch TTL Input Buffer RD TRISF RD TRISF ST Input Buffer Q Q D D ENEN EN RD PORTF RD PORTF SS Input To A/D Converter or Comparator Input Note 1: I/O pins have diode protection to VDD and VSS. DS39612B-page 118 Note: I/O pins have diode protection to VDD and VSS. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 10-11: PORTF FUNCTIONS Name Bit# Buffer Type Function RF0/AN5 bit 0 ST Input/output port pin or analog input. RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or Comparator 2 output. RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or Comparator 1 output. RF3/AN8 bit 3 ST Input/output port pin or analog input/comparator input. RF4/AN9 bit 4 ST Input/output port pin or analog input/comparator input. RF5/AN10/CVREF bit 5 ST Input/output port pin, analog input/comparator input or comparator reference output. RF6/AN11 bit 6 ST Input/output port pin or analog input/comparator input. RF7/SS bit 7 ST/TTL Input/output port pin or slave select pin for synchronous serial port. Legend: ST = Schmitt Trigger input, TTL = TTL input TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Value on: POR, BOR Value on all other Resets PORTF Data Direction Control Register 1111 1111 1111 1111 PORTF Read PORTF pin/Write PORTF Data Latch x000 0000 u000 0000 LATF Read PORTF Data Latch/Write PORTF Data Latch xxxx xxxx uuuu uuuu Name TRISF Bit 7 -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 ADCON1 -- Bit 6 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by PORTF. 2005 Microchip Technology Inc. DS39612B-page 119 PIC18F6525/6621/8525/8621 10.7 PORTG, TRISG and LATG Registers The sixth pin of PORTG (MCLR/VPP/RG5) is a digital input pin. Its operation is controlled by the MCLRE configuration bit in Configuration Register 3H (CONFIG3H<7>). In its default configuration (MCLRE = 1), the pin functions as the device Master Clear input. When selected as a port pin (MCLRE = 0), it functions as an input only pin; as such, it does not have TRISG or LATG bits associated with it. PORTG is a 6-bit wide port with 5 bidirectional pins (RG0:RG4) and one optional input only pin (RG5). The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). In either configuration, RG5 also functions as the programming voltage input during device programming. Note 1: On a Power-on Reset, RG5 is enabled as a digital input only if Master Clear functionality is disabled (MCLRE = 0). The Data Latch register (LATG) is also memory mapped. Read-modify-write operations on the LATG register, read and write the latched output value for PORTG. 2: If the device Master Clear is disabled, verify that either of the following is done to ensure proper entry into ICSP mode: a.) disable low-voltage programming (CONFIG4L<2> = 0); or b.) make certain that RB5/KBI1/PGM is held low during entry into ICSP. PORTG is multiplexed with both CCP/ECCP and EUSART functions (Table 10-13). PORTG pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: EXAMPLE 10-7: On a Power-on Reset, these pins are configured as digital inputs. The pin override value is not loaded into the TRIS register. This allows read-modify-write operations of the TRIS register without concern due to peripheral overrides. FIGURE 10-16: CLRF PORTG CLRF LATG MOVLW 0x04 MOVWF TRISG TRIS OVERRIDE Pin Peripheral Data Out 0 RD LATG WR LATG or WR PORTG Override D CK RG0 Yes ECCP3 I/O P RG1 Yes USART1 Async Xmit, Sync Clock RG2 Yes USART1 Async Rcv, Sync Data Out RG3 Yes CCP4 I/O RG4 Yes CCP5 I/O Q I/O Q D Q CK Q TRIS Latch N VSS TRIS Override Logic Peripheral VDD 1 Data Latch WR TRISG Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RG1:RG0 as outputs RG2 as input RG4:RG3 as inputs PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORTG/Peripheral Out Select Data Bus INITIALIZING PORTG ; ; ; ; ; ; ; ; ; ; ; ; pin(1) Note 1: I/O pins have diode protection to VDD and VSS. 2: Peripheral output enable is only active if peripheral select is active. RD TRISG Schmitt Trigger Peripheral Output Enable(2) Q D EN RD PORTG Peripheral Data In DS39612B-page 120 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 10-17: MCLR/VPP/RG5 PIN BLOCK DIAGRAM MCLRE Data Bus MCLR/VPP/RG5 RD TRISA Schmitt Trigger RD LATA Latch Q D EN RD PORTA High-Voltage Detect HV Internal MCLR Filter Low-Level MCLR Detect TABLE 10-13: PORTG FUNCTIONS Name Bit# Buffer Type Function RG0/ECCP3/P3A bit 0 ST Input/output port pin, Enhanced Capture 3 input/Compare 3 output/ PWM 3 output or Enhanced PWM 3 output P3A. RG1/TX2/CK2 bit 1 ST Input/output port pin, addressable USART2 asynchronous transmit or addressable USART2 synchronous clock. RG2/RX2/DT2 bit 2 ST Input/output port pin, addressable USART2 asynchronous receive or addressable USART2 synchronous data. RG3/CCP4/P3D bit 3 ST Input/output port pin, Capture 4 input/Compare 4 output/PWM 4 output or Enhanced PWM 3 output P3D. RG4/CCP5/P1D bit 4 ST Input/output port pin, Capture 5 input/Compare 5 output/PWM 5 output or Enhanced PWM 1 output P1D. MCLR/VPP/RG5 bit 5 ST Master Clear input or programming voltage input (if MCLR is enabled). Input only port pin or programming voltage input (if MCLR is disabled). Legend: ST = Schmitt Trigger input TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 0 Value on POR, BOR Value on all other Resets RG5(1) Read PORTG pins/Write PORTG Data Latch --xx xxxx --uu uuuu LATG Data Output Register ---x xxxx ---u uuuu Data Direction Control Register for PORTG ---1 1111 ---1 1111 Bit 7 Bit 6 Bit 5 PORTG -- -- LATG -- -- -- TRISG -- -- -- Bit 4 Bit 3 Bit 2 Bit 1 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0' Note 1: RG5 is available as an input only when MCLR is disabled. 2005 Microchip Technology Inc. DS39612B-page 121 PIC18F6525/6621/8525/8621 10.8 Note: PORTH, LATH and TRISH Registers PORTH is available only on PIC18F8525/ 8621 devices. FIGURE 10-18: RD LATH PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). Data Bus Read-modify-write operations on the LATH register, read and write the latched output value for PORTH. WR TRISH Pins RH7:RH4 are multiplexed with analog inputs AN15:AN12. Pins RH3:RH0 are multiplexed with the system bus as the external memory interface; they are the high-order address bits A19:A16. By default, pins RH7:RH4 are enabled as A/D inputs and pins RH3:RH0 are enabled as the system address bus. Register ADCON1 configures RH7:RH4 as I/O or A/D inputs. Register MEMCON configures RH3:RH0 as I/O or system bus pins. Note 1: On Power-on Reset, PORTH pins RH7:RH4 default to A/D inputs and read as `0'. 2: On Power-on Reset, PORTH pins RH3:RH0 default to system bus signals. EXAMPLE 10-8: CLRF CLRF MOVLW MOVWF MOVLW MOVWF PORTH ; ; ; LATH ; ; ; 0Fh ; ADCON1 ; 0CFh ; ; ; TRISH ; ; ; INITIALIZING PORTH Initialize PORTH by clearing output data latches Alternate method to clear output data latches RH3:RH0 PINS BLOCK DIAGRAM IN I/O MODE WR LATH or PORTH D I/O pin(1) CK Data Latch D Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRISH Q D ENEN RD PORTH Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 10-19: RH7:RH4 PINS BLOCK DIAGRAM IN I/O MODE RD LATH Data Bus WR LATH or PORTH D WR TRISH Q I/O pin(1) CK Data Latch D Value used to initialize data direction Set RH3:RH0 as inputs RH5:RH4 as outputs RH7:RH6 as inputs Q Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRISH Q D EN EN RD PORTH To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS. DS39612B-page 122 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 10-20: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTH RD LATH Data Bus WR LATH or PORTH D Q Port I/O pin(1) 0 Data 1 CK Data Latch D WR TRISH Q CK TRIS Latch TTL Input Buffer RD TRISH External Enable System Bus Control Address Out Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS. 2005 Microchip Technology Inc. DS39612B-page 123 PIC18F6525/6621/8525/8621 TABLE 10-15: PORTH FUNCTIONS Name Bit# Buffer Type Function bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface. bit 1 ST/TTL(1) Input/output port pin or address bit 17 for external memory interface. RH2/A18 bit 2 ST/TTL (1) Input/output port pin or address bit 18 for external memory interface. RH3/A19 bit 3 ST/TTL(1) Input/output port pin or address bit 19 for external memory interface. RH4/AN12/P3C(2) bit 4 ST Input/output port pin, analog input channel 12 or Enhanced PWM output P3C. RH5/AN13/P3B(2) bit 5 ST Input/output port pin, analog input channel 13 or Enhanced PWM output P3B. RH6/AN14/P1C(2) bit 6 ST Input/output port pin, analog input channel 14 or Enhanced PWM output P1C. RH7/AN15/P1B(2) bit 7 ST Input/output port pin, analog input channel 15 or Enhanced PWM3 output P1B. RH0/A16 RH1/A17 Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. 2: Valid only for PIC18F8525/8621 devices when ECCPMX is not set. The alternate assignments for P1B/P1C/P3B/P3C in all PIC18F6525/6621 devices and in PIC18F8525/8621 devices when ECCPMX is set are RE6, RE5, RE4 and RE3, respectively. TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets TRISH PORTH Data Direction Control Register 1111 1111 1111 1111 PORTH Read PORTH pin/Write PORTH Data Latch 0000 xxxx 0000 uuuu LATH Read PORTH Data Latch/Write PORTH Data Latch ADCON1 MEMCON(1) xxxx xxxx uuuu uuuu -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 EBDIS -- WAIT1 0-00 --00 WAIT0 -- -- WM1 WM0 0-00 --00 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by PORTH. Note 1: This register is unused on PIC18F6525/6621 devices and reads as `0'. DS39612B-page 124 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 10.9 Note: PORTJ, TRISJ and LATJ Registers PORTJ is available only on PIC18F8525/ 8621 devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATJ) is also memory mapped. Read-modify-write operations on the LATJ register, read and write the latched output value for PORTJ. PORTJ is multiplexed with the system bus as the external memory interface; I/O port functions are only available when the system bus is disabled. When operating as the external memory interface, PORTJ provides the control signal to external memory devices. The RJ5 pin is not multiplexed with any system bus functions. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTJ pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs. EXAMPLE 10-9: CLRF PORTJ CLRF LATJ MOVLW 0xCF MOVWF TRISJ INITIALIZING PORTJ ; ; ; ; ; ; ; ; ; ; ; ; FIGURE 10-21: Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RJ3:RJ0 as inputs RJ5:RJ4 as output RJ7:RJ6 as inputs PORTJ BLOCK DIAGRAM IN I/O MODE RD LATJ Data Bus WR LATJ or PORTJ D I/O pin(1) CK Data Latch D WR TRISJ Q Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRISJ The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. Q D ENEN RD PORTJ Note 1: I/O pins have diode protection to VDD and VSS. 2005 Microchip Technology Inc. DS39612B-page 125 PIC18F6525/6621/8525/8621 FIGURE 10-22: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ Data Bus D I/O pin(1) Port Q 0 Data WR LATJ or PORTJ 1 CK Data Latch D WR TRISJ Q CK TRIS Latch RD TRISJ Control Out System Bus Control External Enable Drive System Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 10-23: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ Data Bus WR LATJ or PORTJ D Port I/O pin(1) 0 Data 1 CK Data Latch D WR TRISJ Q Q CK TRIS Latch RD TRISJ UB/LB Out System Bus Control WM = 01 Drive System Note 1: I/O pins have diode protection to VDD and VSS. DS39612B-page 126 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 10-17: PORTJ FUNCTIONS Name Bit# Buffer Type Function RJ0/ALE bit 0 ST Input/output port pin or address latch enable control for external memory interface. RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface. RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface. RJ3/WRH bit 3 ST Input/output port pin or write high byte control for external memory interface. RJ4/BA0 bit 4 ST Input/output port pin or byte address 0 control for external memory interface. RJ5/CE bit 5 ST Input/output port pin or chip enable control for external memory interface. RJ6/LB bit 6 ST Input/output port pin or lower byte select control for external memory interface. RJ7/UB bit 7 ST Input/output port pin or upper byte select control for external memory interface. Legend: ST = Schmitt Trigger input TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTJ Read PORTJ pin/Write PORTJ Data Latch xxxx xxxx uuuu uuuu LATJ LATJ Data Output Register xxxx xxxx uuuu uuuu TRISJ Data Direction Control Register for PORTJ 1111 1111 1111 1111 Legend: x = unknown, u = unchanged 2005 Microchip Technology Inc. DS39612B-page 127 PIC18F6525/6621/8525/8621 10.10 Parallel Slave Port PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set. It is asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. Note: For PIC18F8525/8621 devices, the Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PCFG2:PCFG0 (ADCON1<2:0>), must be set, which will configure pins RE2:RE0 as digital I/O. A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (PSPCON<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs) and the ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. FIGURE 10-24: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus D WR LATD or PORTD Q RDx pin CK Data Latch Q RD PORTD TTL D ENEN TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read TTL RD Chip Select TTL CS Write TTL WR Note: I/O pin has protection diodes to VDD and VSS. DS39612B-page 128 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 10-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER(1) R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE -- -- -- -- bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as `0' Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. Legend: FIGURE 10-25: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF 2005 Microchip Technology Inc. DS39612B-page 129 PIC18F6525/6621/8525/8621 FIGURE 10-26: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 PORTE Read PORTE pin/Write PORTE Data Latch xxxx xxxx uuuu uuuu LATE LATE Data Output bits xxxx xxxx uuuu uuuu TRISE PORTE Data Direction bits 1111 1111 1111 1111 (1) PSPCON IBF OBF IBOV PSPMODE -- -- -- -- 0000 ---- 0000 ---- INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PSPIF(1) ADIF RC1IF TX1IF PIE1 PSPIE(1) ADIE RC1IE TX1IE IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 Legend: Note 1: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 130 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 11.0 TIMER0 MODULE The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock REGISTER 11-1: Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 131 PIC18F6525/6621/8525/8621 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 1 1 T0CKI pin Programmable Prescaler 0 TMR0 (2 TCY Delay) T0SE 3 Sync with Internal Clocks PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: FOSC/4 TIMER0 BLOCK DIAGRAM IN 16-BIT MODE 0 1 1 T0CKI pin T0SE Programmable Prescaler 0 Sync with Internal Clocks TMR0L TMR0 High Byte 8 (2 TCY Delay) 3 PSA T0PS2, T0PS1, T0PS0 T0CS Set Interrupt Flag bit TMR0IF on Overflow Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39612B-page 132 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 11.1 11.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control, (i.e., it can be changed "on-the-fly" during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. 11.3 When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 11.4 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. A write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x and so on) will clear the prescaler count. Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. TABLE 11-1: Name 16-Bit Mode Timer Reads and Writes TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 11-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Prescaler Note: Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IE bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep since the timer is shut off during Sleep. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed below. 11.2 SWITCHING PRESCALER ASSIGNMENT REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0L Timer0 Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 High Byte Register 0000 0000 uuuu uuuu INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF T0CON TMR0ON PSA T0PS2 TRISA -- Legend: Note 1: T08BIT T0CS T0SE TRISA6(1) PORTA Data Direction Register T0PS1 RBIF 0000 000x 0000 000u T0PS0 1111 1111 1111 1111 -111 1111 -111 1111 x = unknown, u = unchanged, -- = unimplemented locations, read as `0'. Shaded cells are not used by Timer0. RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read `0' in all other oscillator modes. 2005 Microchip Technology Inc. DS39612B-page 133 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 134 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * Reset from ECCP module special event trigger Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Figure 12-1 is a simplified block diagram of the Timer1 module. REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 Unimplemented: Read as `0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 135 PIC18F6525/6621/8525/8621 12.1 Timer1 Operation When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is ignored and the pins are read as `0'. Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter Timer1 also has an internal "Reset input". This Reset can be generated by the ECCP1 or ECCP2 special event trigger. This is discussed in detail in Section 12.4 "Resetting Timer1 Using an ECCP Special Trigger Output". The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. FIGURE 12-1: TIMER1 BLOCK DIAGRAM ECCP Special Event Trigger TMR1IF Overflow Interrupt Flag Bit TMR1 TMR1H 1 TMR1ON On/Off T1OSC T1OSO/T13CKI T1OSCEN Enable Oscillator(1) T1OSI Synchronized Clock Input 0 CLR TMR1L T1SYNC 1 Synchronize Prescaler 1, 2, 4, 8 FOSC/4 Internal Clock det 0 2 T1CKPS1:T1CKPS0 Sleep Input TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L ECCP Special Event Trigger Read TMR1L TMR1IF Overflow Interrupt Flag bit TMR1 8 Timer 1 High Byte TMR1L 1 TMR1ON On/Off T1OSC T1OSO/T13CKI T1OSI Synchronized Clock Input 0 CLR T1SYNC 1 T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize det 0 2 TMR1CS T1CKPS1:T1CKPS0 Sleep Input Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39612B-page 136 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 12.2 Timer1 Oscillator 12.3 Timer1 Interrupt A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing the TMR1 Interrupt Enable bit, TMR1IE (PIE1<0>). The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. 12.4 FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR C1 33 pF Note: XTAL 32.768 kHz T1OSO See the notes with Table 12-1 for additional information about capacitor selection. CAPACITOR SELECTION FOR THE ALTERNATE OSCILLATOR(2-4) Osc Type Freq C1 C2 LP 32 kHz 15-22 pF(1) 15-22 pF(1) Crystal Tested 32.768 kHz Note 1: Microchip suggests 33 pF as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. 2005 Microchip Technology Inc. The special event triggers from the ECCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. C2 33 pF TABLE 12-1: If either the ECCP1 or ECCP2 module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. The trigger for ECCP2 will also start an A/D conversion if the A/D module is enabled. PIC18F6X2X/8X2X T1OSI Note: Resetting Timer1 Using an ECCP Special Trigger Output In the event that a write to Timer1 coincides with a special event trigger from ECCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. 12.5 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. DS39612B-page 137 PIC18F6525/6621/8525/8621 12.6 Using Timer1 as a Real-Time Clock the routine which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 "Timer1 Oscillator") gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow, triggers the interrupt and calls EXAMPLE 12-1: Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the Most Significant bit of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .59 secs ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? ; ; ; ; No, done Clear seconds Increment minutes 60 minutes elapsed? ; ; ; ; No, done clear minutes Increment hours 24 hours elapsed? ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt RTCisr DS39612B-page 138 secs mins, F .59 mins mins hours, F .23 hours .01 hours ; No, done ; Reset hours to 1 ; Done 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 12-2: Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TMR1L Timer1 Register Low Byte xxxx xxxx uuuu uuuu TMR1H Timer1 Register High Byte xxxx xxxx uuuu uuuu T1CON Legend: Note 1: RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 139 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 140 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 13.0 TIMER2 MODULE 13.1 The Timer2 module timer has the following features: * * * * * * * 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 MSSP module optional use of TMR2 output to generate clock shift Timer2 has a control register shown in Register 13-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 13-1 is a simplified block diagram of the Timer2 module. Register 13-1 shows the Timer2 Control register. The prescaler and postscaler selection of Timer2 are controlled by this register. REGISTER 13-1: Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the ECCP module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt, latched in flag bit TMR2IF (PIR1<1>). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. T2CON: TIMER2 CONTROL REGISTER U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 R/W-0 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 141 PIC18F6525/6621/8525/8621 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate the shift clock. TIMER2 BLOCK DIAGRAM Sets Flag bit TMR2IF TMR2 Output(1) Prescaler 1:1, 1:4, 1:16 FOSC/4 TMR2 2 Reset Comparator EQ Postscaler 1:1 to 1:16 T2CKPS1:T2CKPS0 4 PR2 T2OUTPS3:T2OUTPS0 Note 1: TMR2 register output can be software selected by the MSSP module as a baud clock. TABLE 13-1: Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on all other Resets Bit 0 Value on POR, BOR RBIF 0000 000x 0000 000u TMR0IE INT0IE RBIE TMR0IF INT0IF PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 INTCON GIE/GIEH PEIE/GIEL TMR2 T2CON PR2 Legend: Note 1: Timer2 Module Register -- 0000 0000 0000 0000 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Timer2 Period Register 1111 1111 1111 1111 x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 142 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers: TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h * Reset from ECCP module trigger REGISTER 14-1: Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP/ECCP clock source. Register 12-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module, as well as contains the Timer1 oscillator enable bit (T1OSCEN) which can be a clock source for Timer3. T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 11 = Timer3 and Timer4 are the clock sources for ECCP1 through CCP5 10 = Timer3 and Timer4 are the clock sources for ECCP3 through CCP5; Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2 01 = Timer3 and Timer4 are the clock sources for ECCP2 through CCP5; Timer1 and Timer2 are the clock sources for ECCP1 00 = Timer1 and Timer2 are the clock sources for ECCP1 through CCP5 bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 143 PIC18F6525/6621/8525/8621 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is ignored and the pins are read as `0'. The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). Timer3 also has an internal "Reset input". This Reset can be generated by the ECCP module (Section 14.0 "Timer3 Module"). FIGURE 14-1: TIMER3 BLOCK DIAGRAM ECCP Special Event Trigger T3CCPx TMR3IF Overflow Interrupt Flag bit TMR3H Synchronized Clock Input 0 CLR TMR3L 1 TMR3ON On/Off T3SYNC T1OSC T1OSO/ T13CKI 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock T1OSI Synchronize Prescaler 1, 2, 4, 8 det 0 2 Sleep Input TMR3CS T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 8 Write TMR3L Read TMR3L Set TMR3IF Flag bit on Overflow 8 ECCP Special Event Trigger T3CCPx Synchronized 0 Clock Input TMR3 Timer3 High Byte TMR3L CLR 1 To Timer1 Clock Input T1OSO/ T13CKI T1OSI TMR3ON On/Off T1OSC T3SYNC 1 T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize det 0 2 T3CKPS1:T3CKPS0 TMR3CS Sleep Input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39612B-page 144 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated up to 200 kHz. See Section 12.0 "Timer1 Module" for further details. 14.3 The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit, TMR3IE (PIE2<1>). TABLE 14-1: If either the ECCP1 or ECCP2 module is configured in Compare mode to generate a special event trigger (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. Note: Timer3 Interrupt Resetting Timer3 Using an ECCP Special Trigger Output The special event triggers from the ECCP module will not set interrupt flag bit, TMR3IF (PIR1<0>). Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer3 coincides with a special event trigger from ECCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer3. REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Value on all other Resets Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 TMR3L Timer3 Register Low Byte TMR3H Timer3 Register High Byte xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RD16 -- T3CON RD16 T3CCP2 Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer3 module. T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CKPS1 T3CKPS0 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu 2005 Microchip Technology Inc. T3CCP1 DS39612B-page 145 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 146 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 15.0 TIMER4 MODULE 15.1 The Timer4 module timer has the following features: * * * * * * 8-bit timer (TMR4 register) 8-bit period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register shown in Register 15-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 are also controlled by this register. Figure 15-1 is a simplified block diagram of the Timer4 module. Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T4CKPS1:T4CKPS0 (T4CON<1:0>). The match output of TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR4 interrupt, latched in flag bit TMR4IF (PIR3<3>). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR4 register * a write to the T4CON register * any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 R/W-0 T4CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6-3 T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 147 PIC18F6525/6621/8525/8621 15.2 Timer4 Interrupt 15.3 The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 15-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the CCP modules. It is not used as a baud rate clock for the MSSP, as is the Timer2 output. TIMER4 BLOCK DIAGRAM Sets Flag bit TMR4IF TMR4 Output Prescaler 1:1, 1:4, 1:16 FOSC/4 2 TMR4 Reset Comparator EQ Postscaler 1:1 to 1:16 T4CKPS1:T4CKPS0 4 PR4 T4OUTPS3:T4OUTPS0 TABLE 15-1: Name REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE RC2IP Bit 1 INT0IE RBIE TMR0IF INT0IF TX2IP TMR4IP CCP5IP CCP4IP Value on all other Resets Bit 0 Value on POR, BOR RBIF 0000 000x 0000 000u IPR3 -- -- PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 TMR4 T4CON PR4 Legend: Timer4 Register -- CCP3IP --11 1111 --00 0000 0000 0000 0000 0000 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 Timer4 Period Register 1111 1111 1111 1111 x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer4 module. DS39612B-page 148 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6525/6621/8525/8621 devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) implement standard Capture and Compare modes, as well as Enhanced PWM modes. These are discussed in Section 17.0 "Enhanced Capture/Compare/PWM (ECCP) Module". Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. The operations of PWM mode described in Section 16.4 "PWM Mode" apply to CCP4 and CCP5 only. Note: Each CCP/ECCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. For the sake of clarity, all CCP module operation in the following sections is described with respect to CCP4, but is equally applicable to CCP5. REGISTER 16-1: Throughout this section and Section 17.0 "Enhanced Capture/Compare/PWM (ECCP) Module", references to register and bit names that may be associated with a specific CCP module are referred to generically by the use of `x' or `y' in place of the specific module number. Thus, "CCPxCON" might refer to the control register for CCP4 or CCP5, or ECCP1, ECCP2 or ECCP3. "CCPxCON" is used throughout these sections to refer to the module control register, regardless of whether the CCP module is a standard or Enhanced implementation. CCPxCON REGISTER (CCP4 AND CCP5 MODULES) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- DCxB1 DCxB0 CCPxM3 CCPxM2 R/W-0 R/W-0 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode; initialize CCP pin low; on compare match, force CCP pin high (CCPIF bit is set) 1001 = Compare mode; initialize CCP pin high; on compare match, force CCP pin low (CCPIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPIF bit is set, CCP pin reflects I/O state) 1011 = Reserved 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 149 PIC18F6525/6621/8525/8621 16.1 TABLE 16-1: CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register in turn is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.1 CCP MODULES AND TIMER RESOURCES The CCP/ECCP modules utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available to modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. FIGURE 16-1: CCP Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 or Timer4 The assignment of a particular timer to a module is determined by the Timer-to-CCP enable bits in the T3CON register (Register 14-1, page 143). Depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (Capture/Compare or PWM) sharing timer resources. The possible configurations are shown in Figure 16-1. CCP AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 TMR1 CCP MODE - TIMER RESOURCE TMR3 ECCP1 T3CCP<2:1> = 01 TMR1 TMR3 ECCP1 T3CCP<2:1> = 10 TMR1 TMR3 T3CCP<2:1> = 11 TMR1 TMR3 ECCP1 ECCP1 ECCP2 ECCP2 ECCP2 ECCP2 ECCP3 ECCP3 ECCP3 ECCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 Timer1 is used for all Capture and Compare operations for all CCP modules. Timer2 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer3 and Timer4 are not available. DS39612B-page 150 TMR2 TMR4 Timer1 and Timer2 are used for Capture and Compare or PWM operations for ECCP1 only (depending on selected mode). All other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/ Compare or PWM modes. TMR2 TMR4 Timer1 and Timer2 are used for Capture and Compare or PWM operations for ECCP1 and ECCP2 only (depending on the mode selected for each module). Both modules may use a timer as a common time base if they are both in Capture/Compare or PWM modes. TMR2 TMR4 Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. The other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/ Compare or PWM modes. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 16.2 16.2.3 Capture Mode In Capture mode, the CCPR4H:CCPR4L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RG3/CCP4/P1D. An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge 16.2.1 CCP PIN CONFIGURATION In Capture mode, the RG3/CCP4/P1D pin should be configured as an input by setting the TRISG<3> bit. Note: 16.2.2 If the RG3/CCP4/P1D is configured as an output, a write to the port can cause a capture condition. TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the T3CON register (see Section 16.1.1 "CCP Modules and Timer Resources"). FIGURE 16-2: When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP4IE (PIE3<1>) clear to avoid false interrupts and should clear the flag bit, CCP4IF, following any such change in operating mode. 16.2.4 The event is selected by the mode select bits, CCP4M3:CCP4M0 (CCP4CON<3:0>). When a capture is made, the interrupt request flag bit CCP4IF (PIR3<1>) is set; it must be cleared in software. If another capture occurs before the value in register CCPR4 is read, the old captured value is overwritten by the new captured value. SOFTWARE INTERRUPT CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCP4M3:CCP4M0). Whenever the CCP module is turned off or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 16-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 16-1: CLRF MOVLW MOVWF CHANGING BETWEEN CAPTURE PRESCALERS CCP4CON ; Turn CCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON CCP4CON ; Load CCP1CON with ; this value CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set Flag bit CCP4IF T3CCP2 Prescaler / 1, 4, 16 RG3/CCP4/P1D pin TMR3 Enable CCPR4H and Edge Detect T3CCP2 CCPR4L TMR1 Enable TMR1H TMR1L CCP1CON<3:0> Q's 2005 Microchip Technology Inc. DS39612B-page 151 PIC18F6525/6621/8525/8621 16.3 16.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP4 pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. * * * * 16.3.3 driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the I/O latch) When the Generate Software Interrupt mode is chosen (CCP4M3:CCP4M0 = 1010), the CCP4 pin is not affected. Only a CCP interrupt is generated if enabled and the CCP4IE bit is set. The action on the pin is based on the value of the mode select bits (CCP4M3:CCP4M0). At the same time, the interrupt flag bit CCP4IF is set. 16.3.1 16.3.4 SPECIAL EVENT TRIGGER Although shown in Figure 16-3, the compare on match special event triggers are not implemented on CCP4 or CCP5; they are only available on ECCP1 and ECCP2. Their operation is discussed in detail in Section 17.2.1 "Special Event Trigger". CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. Note: SOFTWARE INTERRUPT MODE Clearing the CCP4CON register will force the RG3/CCP4/P1D compare output latch to the default low level. This is not the PORTG I/O data latch. FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger (ECCP1 and ECCP2 only) Set Flag bit CCP4IF CCPR4H CCPR4L Q RG3/CCP4/P1D pin TRISG<3> Output Enable S R Output Logic CCP4CON<3:0> Mode Select Comparator Match T3CCP2 TMR1H DS39612B-page 152 TMR1L 0 1 TMR3H TMR3L 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 16-2: Name INTCON RCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 GIE/GIEH PEIE/GIEL Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u Bit 6 IPEN -- -- RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000 PIE2 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000 IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 TRISB PORTB Data Direction Register 1111 1111 1111 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TRISE PORTE Data Direction Register TRISG -- -- -- 1111 1111 1111 1111 PORTG Data Direction Register ---1 1111 ---1 1111 TMR1L Timer1 Register Low Byte xxxx xxxx uuuu uuuu TMR1H Timer1 Register High Byte xxxx xxxx uuuu uuuu T1CON RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte T3CON CCP1CON RD16 P1M1 T3CCP2 P1M0 T3CKPS1 T3CKPS0 DC1B1 DC1B0 CCP1M3 xxxx xxxx uuuu uuuu CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte xxxx xxxx uuuu uuuu CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte xxxx xxxx uuuu uuuu CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCPR4L Capture/Compare/PWM Register 4 Low Byte CCPR4H Capture/Compare/PWM Register 4 High Byte CCP4CON -- -- DC4B1 DC4B0 CCPR5L Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCP5CON Legend: Note 1: -- -- DC5B1 DC5B0 CCP3M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M2 CCP3M1 CCP3M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 --00 0000 x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by Capture and Compare, Timer1 or Timer3. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 153 PIC18F6525/6621/8525/8621 16.4 16.4.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP4 pin produces up to a 10-bit resolution PWM output. Since the CCP4 pin is multiplexed with the PORTG data latch, the TRISG<3> bit must be cleared to make the CCP4 pin an output. Note: Clearing the CCP4CON register will force the CCP4 PWM output latch to the default low level. This is not the PORTG I/O data latch. Figure 16-4 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 16.4.3 "Setup for PWM Operation". FIGURE 16-4: SIMPLIFIED PWM BLOCK DIAGRAM The PWM period is specified by writing to the PR2 (PR4) register. The PWM period can be calculated using the following formula: EQUATION 16-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 (TMR4) is equal to PR2 (PR2), the following three events occur on the next increment cycle: * TMR2 (TMR4) is cleared * The CCP4 pin is set (exception: if PWM duty cycle = 0%, the CCP4 pin will not be set) * The PWM duty cycle is latched from CCPR4L into CCPR4H Note: CCP1CON<5:4> Duty Cycle Registers CCPR4L CCPR4H (Slave) 16.4.2 R Comparator Q RG3/CCP4 TMR2 (Note 1) S TRISG<3> Comparator Clear Timer, CCP1 pin and latch D.C. PR2 Note 1: PWM PERIOD The Timer2 and Timer4 postscalers (see Section 13.0 "Timer2 Module") are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR4L register and to the CCP4CON<5:4> bits. Up to 10-bit resolution is available. The CCPR4L contains the eight MSbs and the CCP4CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR4L:CCP4CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: EQUATION 16-2: 8-bit TMR2 or TMR4 is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit time base. PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) * TOSC * (TMR2 Prescale Value) A PWM output (Figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). CCPR4L and CCP4CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR4H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR4H is a read-only register. FIGURE 16-5: The CCPR4H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. PWM OUTPUT Period When the CCPR4H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP4 pin is cleared. Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS39612B-page 154 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 16-3: 16.4.3 The following steps should be taken when configuring the CCP module for PWM operation: 1. F OSC log --------------- F PWM PWM Resolution (max) = -----------------------------bits log ( 2 ) 2. 3. Note: If the PWM duty cycle value is longer than the PWM period, the CCP4 pin will not be cleared. 4. 5. 6. TABLE 16-3: SETUP FOR PWM OPERATION Select TMR2 or TMR4 by setting or clearing the T3CCP2:T3CCP1 bits in the T3CON register. Set the PWM period by writing to the PR2 or PR4 register Set the PWM duty cycle by writing to the CCPR4L register and CCP4CON<5:4> bits. Make the CCP4 pin an output by clearing the TRISG<3> bit. Set TMR2 or TMR4 prescale value, enable Timer2 or Timer4 by writing to T2CON or T4CON. Configure the CCP4 module for PWM operation. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2005 Microchip Technology Inc. 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 14 12 10 8 7 6.58 DS39612B-page 155 PIC18F6525/6621/8525/8621 TABLE 16-4: Name INTCON RCON REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u BOR 0--1 11qq 0--q qquu IPEN -- -- RI TO PD POR PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000 PIE2 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000 IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 TMR2 Timer2 Register 0000 0000 0000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 T2CON -- T3CON RD16 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu TMR4 Timer4 Register 0000 0000 uuuu uuuu PR4 Timer4 Period Register 1111 1111 uuuu uuuu T4CON -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 uuuu uuuu CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCPR4L Capture/Compare/PWM Register 4 Low Byte CCPR4H Capture/Compare/PWM Register 4 High Byte CCP4CON -- -- DC4B1 DC4B0 CCP3M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M2 CCP3M1 CCP3M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000 CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx uuuu uuuu CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx uuuu uuuu CCP5CON Legend: Note 1: -- -- DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 --00 0000 x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by PWM, Timer2 or Timer4. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 156 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 17.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE Capture and Compare functions of the ECCP module are the same as the standard CCP module. The prototype control register for the Enhanced CCP module is shown in Register 17-1. In addition to the expanded range of modes available through the CCPxCON register, the ECCP modules each have two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: * ECCPxDEL (Dead-Band Delay) * ECCPxAS (Auto-Shutdown Configuration) The Enhanced CCP (ECCP) modules differ from the standard CCP modules by the addition of Enhanced PWM capabilities. These allow for 2 or 4 output channels, user selectable polarity, dead-band control and automatic shutdown and restart and are discussed in detail in Section 17.4 "Enhanced PWM Mode". Except for the addition of the special event trigger, REGISTER 17-1: CCPxCON REGISTER (ECCP1, ECCP2 AND ECCP3 MODULES) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 PxM1:PxM0: Enhanced PWM Output Configuration bits If CCPxM3:CCPxM2 = 00, 01, 10: xx = PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins If CCPxM3:CCPxM2 = 11: 00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: Enhanced CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize ECCP pin low, set output on compare match (set CCPxIF) 1001 = Compare mode, initialize ECCP pin high, clear output on compare match (set CCPxIF) 1010 = Compare mode, generate software interrupt only, ECCP pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CCxIF bit, ECCP2 trigger starts A/D conversion if A/D module is enabled)(1) 1100 = PWM mode; PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode; PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode; PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode; PxA, PxC active-low; PxB, PxD active-low Note 1: Implemented only for ECCP1 and ECCP2; same as `1010' for ECCP3. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 157 PIC18F6525/6621/8525/8621 17.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCP pin assignments are constant, while others change based on device configuration. For those pins that do change, the controlling bits are: * CCP2MX configuration bit (CONFIG3H<0>) * ECCPMX configuration bit (CONFIG3H<1>) * Program Memory mode (set by configuration bits CONFIG3L<1:0>) The pin assignments for the Enhanced CCP modules are summarized in Table 17-1, Table 17-2 and Table 17-3. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, respectively). The appropriate TRIS direction bits for the corresponding port pins must also be set as outputs. 17.1.1 USE OF CCP4 AND CCP5 WITH ECCP1 AND ECCP3 Only the ECCP2 module has four dedicated output pins available for use. Assuming that the I/O ports or other multiplexed functions on those pins are not needed, they may be used whenever needed without interfering with any other CCP module. TABLE 17-1: ECCP1 and ECCP3, on the other hand, only have three dedicated output pins: ECCPx/PxA, PxB and PxC. Whenever these modules are configured for Quad PWM mode, the pin normally used for CCP4 or CCP5 becomes the D output pins for ECCP3 and ECCP1, respectively. The CCP4 and CCP5 modules remain functional but their outputs are overridden. 17.1.2 ECCP MODULE OUTPUTS AND PROGRAM MEMORY MODES For PIC18F8525/8621 devices, the Program Memory mode of the device (Section 4.1.1 "PIC18F6525/6621/ 8525/8621 Program Memory Modes") impacts both pin multiplexing and the operation of the module. The ECCP2 input/output (ECCP2/P2A) can be multiplexed to one of three pins. By default, this is RC1 for all devices. In this case, the default occurs when CCP2MX is set and the device is operating in Microcontroller mode. With PIC18F8525/8621 devices, three other options exist. When CCP2MX is not set (= 0) and the device is in Microcontroller mode, ECCP2/P2A is multiplexed to RE7; in all other program memory modes, it is multiplexed to RB3. The final option is for CCP2MX to be set while the device is operating in one of the three other program memory modes. In this case, ECCP1 and ECCP3 operate as compatible (i.e., single output) CCP modules. The pins used by their other outputs (PxB through PxD) are available for other multiplexed functions. ECCP2 continues to operate as an Enhanced CCP module regardless of the program memory mode. PIN CONFIGURATIONS FOR ECCP1 ECCP Mode CCP1CON Configuration RC2 Compatible CCP 00xx 11xx ECCP1 RE6 Dual PWM 10xx 11xx P1A Quad PWM x1xx 11xx P1A Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 Dual PWM 10xx 11xx P1A P1B Quad PWM x1xx 11xx P1A P1B Compatible CCP 00xx 11xx RE6 RE5 RG4 RH7 RH6 RE5 RG4/CCP5 N/A N/A P1B RE5 RG4/CCP5 N/A N/A P1B P1C P1D N/A N/A RG4/CCP5 RH7/AN15 RH6/AN14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 P1C P1D RH7/AN15 RH6/AN14 All PIC18F6525/6621 devices: PIC18F8525/8621 devices, ECCPMX = 1, Microcontroller mode: PIC18F8525/8621 devices, ECCPMX = 0, Microcontroller mode: ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 RE5/AD13 RG4/CCP5 P1B RH6/AN14 RE5/AD13 P1D P1B P1C Dual PWM 10xx 11xx P1A RE6/AD14 Quad PWM x1xx 11xx P1A RE6/AD14 PIC18F8525/8621 devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP Legend: Note 1: 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 x = Don't care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. With ECCP1 in Quad PWM mode, CCP5's output is overridden by P1D; otherwise CCP5 is fully operational. DS39612B-page 158 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 17-2: ECCP Mode PIN CONFIGURATIONS FOR ECCP2 CCP2CON Configuration RB3 RC1 RE7 RE2 RE1 RE0 All devices, CCP2MX = 1, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D All devices, CCP2MX = 0, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OS1 ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B RE1 RE0 x1xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B P2C P2D Quad PWM PIC18F8525/8621 devices, CCP2MX = 0, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP2 RC1/T1OS1 RE7/AD15 RE2/CS RE1/WR RE0/RD Dual PWM 10xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B RE1/WR RE0/RD Quad PWM x1xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B P2C P2D Legend: x = Don't care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. TABLE 17-3: PIN CONFIGURATIONS FOR ECCP3 ECCP Mode CCP3CON Configuration RG0 Compatible CCP 00xx 11xx ECCP3 RE4 Dual PWM 10xx 11xx P3A Quad PWM x1xx 11xx P3A Compatible CCP 00xx 11xx ECCP3 RE4/AD12 RE3/AD11 Dual PWM 10xx 11xx P3A P3B Quad PWM x1xx 11xx P3A P3B Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P3A RE6/AD14 RE5/AD13 RG3/CCP4 P3B RH6/AN14 Quad PWM x1xx 11xx P3A RE6/AD14 RE5/AD13 P3D P3B P3C RE4 RE3 RG3 RH5 RH4 RE3 RG3/CCP4 N/A N/A P3B RE3 RG3/CCP4 N/A N/A P3B P3C P3D N/A N/A RG3/CCP4 RH5/AN13 RH4/AN12 RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12 P3C P3D RH5/AN13 RH4/AN12 All PIC18F6525/6621 devices: PIC18F8525/8621 devices, ECCPMX = 1, Microcontroller mode: PIC18F8525/8621 devices, ECCPMX = 0, Microcontroller mode: PIC18F8525/8621 devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP Legend: Note 1: 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 x = Don't care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. With ECCP3 in Quad PWM mode, CCP4's output is overridden by P1D; otherwise CCP4 is fully operational. 2005 Microchip Technology Inc. DS39612B-page 159 PIC18F6525/6621/8525/8621 17.1.3 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules, the ECCP modules can utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. Additional details on timer resources are provided in Section 16.1.1 "CCP Modules and Timer Resources". 17.2 Capture and Compare Modes Except for the operation of the special event trigger discussed below, the Capture and Compare modes of the ECCP module are identical in operation to that of CCP4. These are discussed in detail in Section 16.2 "Capture Mode" and Section 16.3 "Compare Mode". 17.2.1 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated in Compare mode, on a match between the CCPR register pair and the selected timer. This can be used in turn to initiate an action. The special event trigger output of either ECCP1 or ECCP2 resets the TMR1 or TMR3 register pair, depending on which timer resource is currently selected. This allows the CCPRx register to effectively be a 16-bit programmable period register for Timer1 or Timer3. In addition, the ECCP2 special event trigger will also start an A/D conversion if the A/D module is enabled. The triggers are not implemented for ECCP3, CCP4 or CCP5. Selecting the Special Event mode (CCPxM3:CCPxM0 = 1011) for these modules has the same effect as selecting the Compare with Software Interrupt mode (CCPxM3:CCPxM0 = 1010). Note: 17.3 The special event trigger from ECCP2 will not set the Timer1 or Timer3 interrupt flag bits. Standard PWM Mode When configured in Single Output mode, the ECCP module functions identically to the standard CCP module in PWM mode as described in Section 16.4 "PWM Mode". This is also sometimes referred to as "Compatible CCP" mode as in Tables 17-1 through 17-3. Note: When setting up single output PWM operations, users are free to use either of the processes described in Section 16.4.3 "Setup for PWM Operation" or Section 17.4.9 "Setup for PWM Operation". The latter is more generic but will work for either single or multi-output PWM. DS39612B-page 160 17.4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated PxA through PxD. Users are also able to select the polarity of the signal (either active-high or active-low). The module's output mode and polarity are configured by setting the PxM1:PxM0 and CCPxM3CCPxM0 bits of the CCPxCON register (CCPxCON<7:6> and CCPxCON<3:0>, respectively). For the sake of clarity, Enhanced PWM mode operation is described generically throughout this section with respect to ECCP1 and TMR2 modules. Control register names are presented in terms of ECCP1. All three Enhanced modules, as well as the two timer resources, can be used interchangeably and function identically. TMR2 or TMR4 can be selected for PWM operation by selecting the proper bits in T3CON. Figure 17-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRIS bits for output. 17.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the equation: EQUATION 17-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The ECCP1 pin is set (if PWM duty cycle = 0%, the ECCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 13.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 17-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> Duty Cycle Registers CCP1M<3:0> 4 P1M1<1:0> 2 CCPR1L ECCP1/P1A ECCP1/P1A TRISx<x> CCPR1H (Slave) P1B R Comparator Output Controller Q P1B TRISx<x> P1C TMR2 (Note 1) P1D Comparator PR2 P1C TRISx<x> S Clear Timer, set ECCP1 pin and latch D.C. P1D TRISx<x> ECCP1DEL Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. 17.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. The PWM duty cycle is calculated by the equation: The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 17-3: EQUATION 17-2: log FOSC FPWM PWM Resolution (max) = log(2) ( PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. TABLE 17-4: Note: ) bits If the PWM duty cycle value is longer than the PWM period, the ECCP1 pin will not be cleared. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2005 Microchip Technology Inc. 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 DS39612B-page 161 PIC18F6525/6621/8525/8621 17.4.3 PWM OUTPUT CONFIGURATIONS The Single Output mode is the standard PWM mode discussed in Section 17.4 "Enhanced PWM Mode". The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: * * * * Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode FIGURE 17-2: The general relationship of the outputs in all configurations is summarized in Figure 17-2. PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 CCP1CON <7:6> 00 (Single Output) PR2 + 1 Duty Cycle SIGNAL Period P1A Modulated Delay Delay P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive DS39612B-page 162 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 17-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 CCP1CON <7:6> 00 (Single Output) PR2 + 1 Duty Cycle SIGNAL Period P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 "Programmable Dead-Band Delay"). 17.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 17-4). This mode can be used for half-bridge applications, as shown in Figure 17-5, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits PDC6:PDC0 sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 17.4.6 "Programmable Dead-Band Delay" for more details on dead-band delay operations. FIGURE 17-4: HALF-BRIDGE PWM OUTPUT Period Period Duty Cycle (2) P1A td td P1B(2) (1) (1) (1) td = Dead Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the TRISC<2> and TRISE<6> bits must be cleared to configure P1A and P1B as outputs. 2005 Microchip Technology Inc. DS39612B-page 163 PIC18F6525/6621/8525/8621 FIGURE 17-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") PIC18F6X2X/8X2X FET Driver + V - P1A Load FET Driver + V - P1B V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F6X2X/8X2X FET Driver FET Driver P1A FET Driver Load FET Driver P1B V- DS39612B-page 164 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 17.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 17-6. FIGURE 17-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. The TRISC<2>, TRISC<6:5> and TRISG<4> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs. FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2005 Microchip Technology Inc. DS39612B-page 165 PIC18F6525/6621/8525/8621 FIGURE 17-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F6X2X/8X2X FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 17.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of (4 TOSC * (Timer2 Prescale Value) before the next PWM period begins. The Timer2 prescaler will be either 1, 4 or 16, depending on the value of the T2CKPS bit (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 17-8. Note that in the Full-Bridge Output mode, the ECCP1 module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. 2. Figure 17-9 shows an example where the PWM direction changes from forward to reverse at a near 100% duty cycle. At time t1, the output P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices QC and QD (see Figure 17-7) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39612B-page 166 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 17-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 17-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC tON(2) External Switch C(1) tOFF(3) External Switch D(1) Potential Shoot-Through Current(1) t = tOFF - tON(2,3) Note 1: All signals are shown as active-high. 2: tON is the turn-on delay of power switch QC and its driver. 3: tOFF is the turn-off delay of power switch QD and its driver. 2005 Microchip Technology Inc. DS39612B-page 167 PIC18F6525/6621/8525/8621 17.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 17-4 for illustration. The lower seven bits of the ECCPxDEL register (Register 17-2) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). 17.4.7 ENHANCED PWM AUTO-SHUTDOWN When an ECCP module is programmed for any PWM mode, the active output pin(s) may be configured for auto-shutdown. Auto-shutdown immediately places the PWM output pin(s) into a defined shutdown state when a shutdown event occurs. REGISTER 17-2: A shutdown event can be caused by either of the two comparator modules or the INT0/FLT0 pin (or any combination of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a digital signal on the INT0/FLT0 pin can also trigger a shutdown. The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The auto-shutdown sources to be used are selected using the ECCP1AS2:ECCP1AS0 bits (bits<6:4> of the ECCP1AS register). When a shutdown occurs, the output pin(s) are asynchronously placed in their shutdown states, specified by the PSS1AC1:PSS1AC0 and PSS1BD1:PSS1BD0 bits (ECCP1AS3:ECCP1AS0). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be tri-stated (not driving). The ECCP1ASE bit (ECCP1AS<7>) is also set to hold the Enhanced PWM outputs in their shutdown states. The ECCP1ASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the Auto-Shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. ECCPxDEL: PWM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon Auto-Shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon Auto-Shutdown, ECCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC6:PxDC0: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Legend: DS39612B-page 168 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 17-3: ECCPxAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 bit 7 ECCPxASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6-4 ECCPxAS2:ECCPxAS0: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = INT0/FLT0 101 = INT0/FLT0 or Comparator 1 110 = INT0/FLT0 or Comparator 2 111 = INT0/FLT0 or Comparator 1 or Comparator 2 bit 3-2 PSSxAC1:PSSxAC0: Pins A and C Shutdown State Control bits 00 = Drive Pins A and C to `0' 01 = Drive Pins A and C to `1' 1x = Pins A and C tri-state bit 1-0 PSSxBD1:PSSxBD0: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to `0' 01 = Drive Pins B and D to `1' 1x = Pins B and D tri-state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 169 PIC18F6525/6621/8525/8621 17.4.7.1 Auto-Shutdown and Automatic Restart 17.4.8 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the P1RSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 17-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared. If PRSEN = 0 (Figure 17-11), once a shutdown condition occurs, the ECCP1ASE bit will remain set until it is cleared by firmware. Once ECCP1ASE is cleared, the Enhanced PWM will resume at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. Independent of the P1RSEN bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. The ECCP1ASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a `1' to the ECCPASE bit. FIGURE 17-10: START-UP CONSIDERATIONS When the ECCP module is used in the PWM mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the off state until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period FIGURE 17-11: Shutdown Shutdown Event Occurs Event Clears PWM Resumes PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period Shutdown Event ECCPASE bit PWM Activity Normal PWM Start of PWM Period DS39612B-page 170 ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 17.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation using Timer2: 1. 2. 3. 4. 5. 6. 7. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 register. If auto-shutdown is required do the following: * Disable auto-shutdown (ECCP1AS = 0) * Configure source (FLT0, Comparator 1 or Comparator 2) * Wait for non-shutdown condition Configure the ECCP1 module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the P1M1:P1M0 bits. * Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. For Half-Bridge Output mode, set the dead-band delay by loading ECCP1DEL<6:0> with the appropriate value. If auto-shutdown operation is required, load the ECCP1AS register: * Select the auto-shutdown sources using the ECCP1AS2:ECCP1AS0 bits. * Select the shutdown states of the PWM output pins using the PSS1AC1:PSS1AC0 and PSS1BD1:PSS1BD0 bits. * Set the ECCP1ASE bit (ECCP1AS<7>). * Configure the comparators using the CMCON register. * Configure the comparator inputs as analog inputs. 2005 Microchip Technology Inc. 8. If auto-restart operation is required, set the P1RSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: * Wait until TMRn overflows (TMRnIF bit is set). * Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. * Clear the ECCP1ASE bit (ECCP1AS<7>). 17.4.10 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module. DS39612B-page 171 PIC18F6525/6621/8525/8621 TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u IPEN -- -- RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000 PIE2 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000 IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 Name INTCON RCON TRISB PORTB Data Direction Register 1111 1111 1111 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TRISCD PORTD Data Direction Register 1111 1111 1111 1111 TRISE PORTE Data Direction Register 1111 1111 1111 1111 TRISF PORTF Data Direction Register TRISG -- -- 1111 1111 1111 1111 -- PORTG Data Direction Register ---1 1111 ---1 1111 TRISH PORTH Data Direction Register 1111 1111 1111 1111 TMR1L Timer1 Register Low Byte xxxx xxxx uuuu uuuu TMR1H Timer1 Register High Byte xxxx xxxx uuuu uuuu T1CON TMR2 T2CON -- RD16 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Timer2 Register -- 0000 0000 0000 0000 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 TMR3L Timer3 Register Low Byte xxxx xxxx uuuu uuuu TMR3H Timer3 Register High Byte xxxx xxxx uuuu uuuu T3CON TMR4 T4CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Timer4 Register -- 0000 0000 0000 0000 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 PR4 Timer4 Period Register 1111 1111 1111 1111 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte CCP1CON ECCP1AS ECCP1DEL P1M1 P1M0 DC1B1 DC1B0 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 P1RSEN P1DC6 P1DC5 CCP1M2 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000 P1DC4 P1DC3 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte CCP2CON ECCP2AS ECCP2DEL P2M1 P2M0 DC2B1 DC2B0 ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 P2RSEN P2DC6 P2DC5 ECCP3AS ECCP3DEL Legend: Note 1: DC3B0 ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 Px3RSEN P3DC6 P3DC5 P3DC4 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 P2DC3 Enhanced Capture/Compare/PWM Register 3 High Byte DC3B1 P1DC0 0000 0000 0000 0000 PSS2AC1 P2DC4 CCPR3H P3M0 P1DC1 CCP1M0 CCP2M2 Enhanced Capture/Compare/PWM Register 3 Low Byte P3M1 P1DC2 CCP1M1 CCP2M3 CCPR3L CCP3CON xxxx xxxx uuuu uuuu CCP1M3 P2DC2 CCP2M1 P2DC1 CCP2M0 0000 0000 0000 0000 P2DC0 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M3 CCP3M2 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000 P3DC3 P3DC2 CCP3M1 P3DC1 CCP3M0 0000 0000 0000 0000 P3DC0 0000 0000 uuuu uuuu x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used during ECCP operation. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 172 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.0 18.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RF7/SS Figure 18-1 shows the block diagram of the MSSP module when operating in SPI mode. FIGURE 18-1: MSSP BLOCK DIAGRAM (SPITM MODE) The I2C interface supports the following modes in hardware: Internal Data Bus Read * Master mode * Multi-Master mode * Slave mode 18.2 Control Registers The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections. Write SSPBUF reg RC4/SDI/SDA SSPSR reg RC5/SDO RF7/SS Shift Clock bit 0 SS Control Enable Edge Select 2 Clock Select RC3/SCK/ SCL SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64 ( ) Data to TXx/RXx in SSPSR TRIS bit 2005 Microchip Technology Inc. DS39612B-page 173 PIC18F6525/6621/8525/8621 18.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. * MSSP Control Register 1 (SSPCON1) * MSSP Status Register (SSPSTAT) * Serial Receive/Transmit Buffer Register (SSPBUF) * MSSP Shift Register (SSPSR) - Not directly accessible During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 18-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Edge Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write bit Information Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: DS39612B-page 174 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: bit 5 In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 175 PIC18F6525/6621/8525/8621 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before EXAMPLE 18-1: LOOP reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 18-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. LOADING THE SSPBUF (SSPSR) REGISTER BTFSS BRA MOVF SSPSTAT, BF LOOP SSPBUF, W ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF MOVWF TXDATA, W SSPBUF ;W reg = contents of TXDATA ;New data to xmit DS39612B-page 176 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3.3 ENABLING SPI I/O 18.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI is automatically controlled by the SPI module * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * SS must have TRISF<7> bit set TYPICAL CONNECTION Figure 18-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data - Slave sends dummy data * Master sends data - Slave sends data * Master sends dummy data - Slave sends data Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 18-2: SPITM MASTER/SLAVE CONNECTION SPITM Master SSPM3:SSPM0 = 00xxb SPITM Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer (SSPBUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPBUF) LSb 2005 Microchip Technology Inc. Shift Register (SSPSR) MSb SCK PROCESSOR 1 SDO Serial Clock LSb SCK PROCESSOR 2 DS39612B-page 177 PIC18F6525/6621/8525/8621 18.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 18-3, Figure 18-5 and Figure 18-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 18-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. FIGURE 18-3: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 18-3 shows the waveforms for Master mode. SPITM MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF DS39612B-page 178 Next Q4 Cycle after Q2 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1<4>). While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from Sleep. 18.3.7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The data latch FIGURE 18-4: must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 7 bit 0 bit 0 bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF 2005 Microchip Technology Inc. Next Q4 Cycle after Q2 DS39612B-page 179 PIC18F6525/6621/8525/8621 FIGURE 18-5: SPITM MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF FIGURE 18-6: SPITM MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39612B-page 180 Next Q4 Cycle after Q2 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3.8 SLEEP OPERATION 18.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 18-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 18-1: In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device from Sleep. 18.3.9 EFFECTS OF A RESET Name SPITM BUS MODES Control Bits State Standard SPI Mode Terminology CKP CKE 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 There is also a SMP bit which controls when the data is sampled. A Reset disables the MSSP module and terminates the current transfer. TABLE 18-2: BUS MODE COMPATIBILITY REGISTERS ASSOCIATED WITH SPITM OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 TRISC TRISF SSPBUF PORTC Data Direction Register TRISF7 TRISF6 TRISF5 1111 1111 1111 1111 MSSP Receive Buffer/Transmit Register 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: Note 1: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the MSSP in SPITM mode. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 181 PIC18F6525/6621/8525/8621 18.4 I2C Mode 18.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCL) - RC3/SCK/SCL * Serial data (SDA) - RC4/SDI/SDA The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. FIGURE 18-7: MSSP BLOCK DIAGRAM (I2CTM MODE) Internal Data Bus Read Write The MSSP module has six registers for I2C operation. These are: * * * * MSSP Control Register 1 (SSPCON1) MSSP Control Register 2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer Register (SSPBUF) * MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are readonly. The upper two bits of the SSPSTAT are read/ write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value. SSPBUF reg RC3/SCK/SCL REGISTERS Shift Clock SSPSR reg RC4/ SDI/ SDA LSb MSb Match Detect Addr Match During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Stop bit Detect DS39612B-page 182 In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Set, Reset S, P bits (SSPSTAT reg) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: bit 2 This bit is cleared on Reset and when SSPEN is cleared. This bit is cleared on Reset and when SSPEN is cleared. R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 183 PIC18F6525/6621/8525/8621 REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: DS39612B-page 184 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 185 PIC18F6525/6621/8525/8621 18.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: I2C Master mode, clock = (FOSC/4) x (SSPADD + 1) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address), with Start and Stop bit interrupts enabled * I 2C Slave mode (10-bit address), with Start and Stop bit interrupts enabled * I 2C firmware controlled master operation, slave is Idle * * * * Selection of any I 2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins. 18.4.3 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on Start and Stop bits When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. * The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. 18.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPSR register value is loaded into the SSPBUF register. The buffer full bit BF is set. An ACK pulse is generated. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is set (interrupt is generated, if enabled) on the falling edge of the ninth SCL pulse. In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. 3. 4. 5. 6. 7. 8. 9. Receive first (high) byte of address (bits SSPIF, BF and UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated Start condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. DS39612B-page 186 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON1<0> = 1), RC3/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit CKP (SSPCON<4>). See Section 18.4.4 "Clock Stretching" for more detail. 18.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section 18.4.4 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then pin RC3/ SCK/SCL should be enabled by setting bit, CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 18-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. 2005 Microchip Technology Inc. DS39612B-page 187 DS39612B-page 188 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to `0' when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent. 9 ACK FIGURE 18-8: SDA PIC18F6525/6621/8525/8621 I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) 2005 Microchip Technology Inc. 2005 Microchip Technology Inc. 1 CKP 2 A6 Data in sampled BF (SSPSTAT<0>) SSPIF (PIR1<3>) S A7 3 A5 4 A4 5 A3 6 A2 Receiving Address 7 A1 8 R/W = 1 9 ACK SCL held low while CPU responds to SSPIF 1 D7 3 D5 4 D4 5 D3 6 D2 CKP is set in software SSPBUF is written in software Cleared in software 2 D6 Transmitting Data 7 8 D0 9 ACK From SSPIF ISR D1 1 D7 4 D4 5 D3 6 D2 CKP is set in software 7 8 D0 9 ACK From SSPIF ISR D1 Transmitting Data Cleared in software 3 D5 SSPBUF is written in software 2 D6 P FIGURE 18-9: SCL SDA PIC18F6525/6621/8525/8621 I2CTM SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39612B-page 189 DS39612B-page 190 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to `0' when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A1 Cleared in software 3 A5 Dummy read of SSPBUF to clear BF flag 1 A6 Receive Second Byte of Address 1 D7 4 5 6 Cleared in software 3 7 8 9 1 2 4 5 6 Cleared in software 3 D3 D2 Receive Data Byte D1 D0 ACK D7 D6 D5 D4 Cleared by hardware when SSPADD is updated with high byte of address 2 D3 D2 Receive Data Byte D6 D5 D4 Clock is held low until update of SSPADD has taken place 7 8 D1 D0 9 P Bus master terminates transfer SSPOV is set because SSPBUF is still full. ACK is not sent. ACK FIGURE 18-10: SDA Receive First Byte of Address Clock is held low until update of SSPADD has taken place PIC18F6525/6621/8525/8621 I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) 2005 Microchip Technology Inc. 2005 Microchip Technology Inc. 2 CKP (SSPCON1<4>) UA (SSPSTAT<1>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 S SCL 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 Receive First Byte of Address 1 9 ACK 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 6 A6 A5 A4 A3 A2 A1 8 A0 Receive Second Byte of Address Dummy read of SSPBUF to clear BF flag A7 9 ACK 2 3 1 4 1 Cleared in software 1 1 5 0 6 8 9 ACK R/W = 1 1 2 4 5 6 CKP is set in software 9 P Completion of data transmission clears BF flag 8 ACK Bus master terminates transfer CKP is automatically cleared in hardware, holding SCL low 7 D4 D3 D2 D1 D0 Cleared in software 3 D7 D6 D5 Transmitting Data Byte Clock is held low until CKP is set to `1' Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence 7 A9 A8 Cleared by hardware when SSPADD is updated with high byte of address. Dummy read of SSPBUF to clear BF flag Sr 1 Receive First Byte of Address Clock is held low until update of SSPADD has taken place FIGURE 18-11: SDA R/W = 0 Clock is held low until update of SSPADD has taken place PIC18F6525/6621/8525/8621 I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS39612B-page 191 PIC18F6525/6621/8525/8621 18.4.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 18.4.4.1 Clock Stretching for 7-bit Slave Receive Mode (SEN = 1) In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence if the BF bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low. The CKP being cleared to `0' will assert the SCL line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 18-13). Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. 18.4.4.2 18.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode 7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 18-9). Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. 18.4.4.4 Clock Stretching for 10-bit Slave Transmit Mode In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence which contains the highorder bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 18-11). Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn't cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39612B-page 192 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to `0'. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 18-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 18-12). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX - 1 SCL CKP Master device asserts clock Master device deasserts clock WR SSPCON 2005 Microchip Technology Inc. DS39612B-page 193 DS39612B-page 194 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs 8 D0 CKP written to `1' in software 2 D6 Clock is held low until CKP is set to `1' 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent. 9 ACK Clock is not held low because ACK = 1 FIGURE 18-13: SDA Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock PIC18F6525/6621/8525/8621 I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) 2005 Microchip Technology Inc. 2005 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock 7 A2 A1 Cleared in software 3 A5 Dummy read of SSPBUF to clear BF flag 1 A6 Receive Second Byte of Address 9 ACK 2 4 5 6 Cleared in software 3 D3 D2 7 9 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. 8 ACK 1 4 5 6 Cleared in software 3 CKP written to `1' in software 2 D3 D2 Receive Data Byte D7 D6 D5 D4 Clock is held low until CKP is set to `1' D1 D0 Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock Dummy read of SSPBUF to clear BF flag 1 D7 D6 D5 D4 Receive Data Byte Clock is held low until update of SSPADD has taken place 7 8 9 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent. D1 D0 ACK Clock is not held low because ACK = 1 FIGURE 18-14: SDA Receive First Byte of Address Clock is held low until update of SSPADD has taken place PIC18F6525/6621/8525/8621 I2CTM SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) DS39612B-page 195 PIC18F6525/6621/8525/8621 18.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 18-15). The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7> set). Following a Start bit detect, 8 bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 18-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7-BIT OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 SCL S 1 2 3 4 5 6 7 8 9 1 9 SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) `0' GCEN (SSPCON2<7>) `1' DS39612B-page 196 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set or the bus is Idle, with both the S and P bits clear. The following events will cause MSSP Interrupt Flag bit, SSPIF, to be set (MSSP interrupt, if enabled): In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit conditions. * * * * * Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDA and SCL. Assert a Repeated Start condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDA and SCL. FIGURE 18-16: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. Start condition Stop condition Data transfer byte transmitted/received Acknowledge transmit Repeated Start MSSP BLOCK DIAGRAM (I2CTM MASTER MODE) Internal Data Bus Read SSPM3:SSPM0 SSPADD<6:0> Write SSPBUF Baud Rate Generator Shift Clock SDA SDA In SCL In Bus Collision 2005 Microchip Technology Inc. LSb Start bit, Stop bit, Acknowledge Generate Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Clock Cntl SCL Receive Enable SSPSR MSb Clock Arbitrate/WCOL Detect (hold off clock source) 18.4.6 Set/Reset S, P, WCOL (SSPSTAT), Set SSPIF, BCLIF, Reset ACKSTAT, PEN (SSPCON2) DS39612B-page 197 PIC18F6525/6621/8525/8621 18.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 18.4.7 "Baud Rate Generator" for more detail. DS39612B-page 198 A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out of the SDA pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out of the SDA pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 18-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to `0' and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 18-17: Table 18-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPM3:SSPM0 Reload SCL Control SSPADD<6:0> Reload CLKO TABLE 18-3: BRG Down Counter FOSC/4 I2CTM CLOCK RATE w/BRG FOSC FCY FCY*2 BRG Value FSCL (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100 kHz 4 MHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2005 Microchip Technology Inc. DS39612B-page 199 PIC18F6525/6621/8525/8621 18.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 18-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 18-18). BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX - 1 SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39612B-page 200 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. FIGURE 18-19: 18.4.8.1 If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete. FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, SCL = 1 TBRG At completion of Start bit, hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st bit SDA 2nd bit TBRG SCL TBRG S 2005 Microchip Technology Inc. DS39612B-page 201 PIC18F6525/6621/8525/8621 18.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. 2: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low-to-high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 18.4.9.1 If the user writes the SSPBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: FIGURE 18-20: WCOL Status Flag Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. REPEATED START CONDITION WAVEFORM Write to SSPCON2 occurs here. SDA = 1, SCL (no change). S bit set by hardware SDA = 1, SCL = 1 TBRG TBRG At completion of Start bit, hardware clears RSEN bit and sets SSPIF TBRG 1st bit SDA RSEN bit set by hardware on the falling edge of ninth clock, end of Xmit Write to SSPBUF occurs here TBRG SCL TBRG Sr = Repeated Start DS39612B-page 202 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the buffer full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 18-21). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 18.4.10.1 BF Status Flag 18.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 18.4.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/ low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). 18.4.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 18.4.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 18.4.11.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 18.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software. 2005 Microchip Technology Inc. DS39612B-page 203 DS39612B-page 204 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W Start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address From slave, clear ACKSTAT bit SSPCON2<6> P Cleared in software 9 ACK ACKSTAT in SSPCON2 = 1 FIGURE 18-21: SEN = 0 Write SSPCON2<0> SEN = 1 Start condition begins PIC18F6525/6621/8525/8621 I 2CTM MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 2005 Microchip Technology Inc. 2005 Microchip Technology Inc. S ACKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 Cleared in software 3 6 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 9 R/W = 1 ACK ACK from Slave 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 D7 D6 D5 D4 D3 D2 D1 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK P Set SSPIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPSTAT<4>) and SSPIF PEN bit = 1 written here SSPOV is set because SSPBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 Receiving Data from Slave RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 Last bit is shifted into SSPSR and contents are unloaded into SSPBUF Cleared in software Set SSPIF interrupt at end of receive 4 Cleared in software 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN cleared automatically Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) FIGURE 18-22: SEN = 0 Write to SSPBUF occurs here, start XMIT Write to SSPCON2<0> (SEN = 1), begin Start Condition Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 PIC18F6525/6621/8525/8621 I 2CTM MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS39612B-page 205 PIC18F6525/6621/8525/8621 18.4.12 ACKNOWLEDGE SEQUENCE TIMING 18.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 18-24). An Acknowledge sequence is enabled by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 18-23). 18.4.12.1 18.4.13.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 18-23: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPIF SSPIF set at the end of receive Cleared in software Cleared in software SSPIF set at the end of Acknowledge sequence Note: TBRG = one baud rate generator period. FIGURE 18-24: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one baud rate generator period. DS39612B-page 206 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.14 SLEEP OPERATION 18.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 18.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 18.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is Idle with both the S and P bits clear. When the bus is busy, enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI-MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 18-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 18-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF 2005 Microchip Technology Inc. DS39612B-page 207 PIC18F6525/6621/8525/8621 18.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 18-26). SCL is sampled low before SDA is asserted low (Figure 18-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 18-28). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to `0' and during this time, if the SCL pin is sampled as `0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLIF flag is set and * the MSSP module is reset to its Idle state (Figure 18-26). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded from SSPADD<6:0> and counts down to `0'. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 18-26: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCLIF SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39612B-page 208 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 18-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S `0' `0' SSPIF `0' `0' FIGURE 18-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN BCLIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 `0' S SSPIF SDA = 0, SCL = 1, set SSPIF 2005 Microchip Technology Inc. Interrupts cleared in software DS39612B-page 209 PIC18F6525/6621/8525/8621 18.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 18-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1'. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 18-30. When the user deasserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to `0'. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 18-29: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software `0' S `0' SSPIF FIGURE 18-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S `0' SSPIF DS39612B-page 210 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to `0'. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 18-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 18-32). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. FIGURE 18-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P `0' SSPIF `0' FIGURE 18-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCLIF PEN BCLIF P `0' SSPIF `0' 2005 Microchip Technology Inc. DS39612B-page 211 PIC18F6525/6621/8525/8621 TABLE 18-4: Name REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE (1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 TRISC TRISF PORTC Data Direction Register TRISF7 TRISF6 TRISF5 1111 1111 1111 1111 1111 1111 1111 1111 SSPBUF MSSP Receive Buffer/Transmit Register SSPADD MSSP Address Register in I2C Slave mode. MSSP Baud Rate Reload Register in I2C Master mode. 0000 0000 0000 0000 SSPCON1 SSPSTAT Legend: Note 1: xxxx xxxx uuuu uuuu WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the MSSP in I2CTM mode. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 212 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The EUSART can be configured in the following modes: * Asynchronous (full duplex) with: - Auto-Wake-up on character reception - Auto-Baud calibration - 12-bit Break character transmission * Synchronous - Master (half duplex) with selectable clock polarity * Synchronous - Slave (half duplex) with selectable clock polarity The pins of USART1 and USART2 are multiplexed with the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/ DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/DT2), respectively. In order to configure these pins as an EUSART: * For USART1: - bit SPEN (RCSTA1<7>) must be set (= 1) - bit TRISC<7> must be set (= 1) - bit TRISC<6> must be cleared (= 0) for Asynchronous and Synchronous Master modes - bit TRISC<6> must be set (= 1) for Synchronous Slave mode * For USART2: - bit SPEN (RCSTA2<7>) must be set (= 1) - bit TRISG<2> must be set (= 1) - bit TRISG<1> must be cleared (= 0) for Asynchronous and Synchronous Master modes - bit TRISC<6> must be set (= 1) for Synchronous Slave mode Note: The operation of each Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTAx) * Receive Status and Control (RCSTAx) * Baud Rate Control (BAUDCONx) These are detailed on the following pages in Register 19-1, Register 19-2 and Register 19-3, respectively. Note: 2005 Microchip Technology Inc. The EUSART control will automatically reconfigure the pin from input to output as needed. Throughout this section, references to register and bit names that may be associated with a specific EUSART module are referred to generically by the use of `x' in place of the specific module number. Thus, "RCSTAx" might refer to the Receive Status register for either USART1 or USART2 DS39612B-page 213 PIC18F6525/6621/8525/8621 REGISTER 19-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC R/W-0 SENDB bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send sync break on next transmission (cleared by hardware upon completion) 0 = Sync break transmission completed Synchronous mode: Don't care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: DS39612B-page 214 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 19-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don't care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 215 PIC18F6525/6621/8525/8621 REGISTER 19-3: BAUDCONx: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 -- RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator - SPBRGx only (Compatible mode), SPBRGHx value ignored bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Rate Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: DS39612B-page 216 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.1 EUSART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTAx<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored. Table 19-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table 19-1. From TABLE 19-1: this, the error in baud rate can be determined. An example calculation is shown in Example 19-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 19-2. It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 19.1.1 SAMPLING The data on the RXx pin (either RC7/RX1/DT1 or RG2/ RX2/DT2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RXx pin. BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 1 8-bit/Asynchronous 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 0 0 FOSC/[16 (n + 1)] FOSC/[4 (n + 1)] Legend: x = Don't care, n = value of SPBRGHx:SPBRGx register pair EXAMPLE 19-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16% TABLE 19-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 -1-0 0-00 Name BAUDCONx SPBRGHx Enhanced USARTx Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRGx Enhanced USARTx Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used by the BRG. 2005 Microchip Technology Inc. DS39612B-page 217 PIC18F6525/6621/8525/8621 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- 1.221 2.441 1.73 255 Actual Rate (K) % Error 0.3 -- -- 1.2 -- 2.4 SPBRG value SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error -- -- -- 1.73 255 1.202 2.404 0.16 129 FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value -- -- -- -- 0.16 129 1201 -0.16 103 2.404 0.16 64 2403 -0.16 51 (decimal) 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 -- -- -- 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 -- -- -- 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 207 300 -0.16 0.16 51 1201 Actual Rate (K) % Error 0.3 0.300 0.16 1.2 1.202 SPBRG value SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error SPBRG value 103 300 -0.16 51 -0.16 25 1201 -0.16 12 (decimal) 2.4 2.404 0.16 25 2403 -0.16 12 -- -- -- 9.6 8.929 -6.99 6 -- -- -- -- -- -- 19.2 20.833 8.51 2 -- -- -- -- -- -- 57.6 62.500 8.51 0 -- -- -- -- -- -- 115.2 62.500 -45.75 0 -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- -- 9.6 9.766 1.73 19.2 19.231 0.16 Actual Rate (K) % Error 0.3 -- 1.2 -- 2.4 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- -- 255 9.615 0.16 129 19.231 0.16 SPBRG value FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value -- -- -- -- -- -- -- -- -- 2.441 1.73 255 2403 -0.16 207 129 9.615 0.16 64 9615 -0.16 51 64 19.531 1.73 31 19230 -0.16 25 (decimal) -- 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) % Error FOSC = 2.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 0.3 -- -- -- -- -- -- 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 -- -- -- 19.2 19.231 0.16 12 -- -- -- -- -- -- 57.6 62.500 8.51 3 -- -- -- -- -- -- 115.2 125.000 8.51 1 -- -- -- -- -- -- DS39612B-page 218 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 1665 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 25 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz Actual Rate (K) FOSC = 1.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 -- -- -- 19.2 19.231 0.16 12 -- -- -- -- -- -- 57.6 62.500 8.51 3 -- -- -- -- -- -- 115.2 125.000 8.51 1 -- -- -- -- -- -- SPBRG value (decimal) % Error SPBRG value (decimal) % Error SPBRG value (decimal) 207 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 33332 0.300 0.00 8332 1.200 0.02 4165 Actual Rate (K) % Error 0.3 0.300 1.2 1.200 2.4 2.400 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.00 16665 0.300 0.00 0.02 4165 1.200 0.02 2.400 0.02 2082 2.402 0.06 SPBRG value FOSC = 8.000 MHz Actual Rate (K) % Error 8332 300 -0.01 6665 2082 1200 -0.04 1665 1040 2400 -0.04 832 SPBRG value (decimal) SPBRG value (decimal) 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) 0.3 1.2 FOSC = 4.000 MHz Actual Rate (K) % Error 0.300 1.200 0.01 0.04 FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 3332 832 300 1201 -0.04 -0.16 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error 1665 415 300 1201 -0.04 -0.16 832 207 SPBRG value SPBRG value (decimal) 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 -- -- -- 115.2 111.111 -3.55 8 -- -- -- -- -- -- 2005 Microchip Technology Inc. DS39612B-page 219 PIC18F6525/6621/8525/8621 19.1.2 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 19-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table 19-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RC1IF interrupt. RCREGx content should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII "U", which is also the LIN bus Sync character), in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRGx begins counting up using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. TABLE 19-4: While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRGx and SPBRGHx will be used FIGURE 19-1: BRG Value BRG COUNTER CLOCK RATES BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/128 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRGx and SPBRGHx are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALCULATION XXXXh RXx pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. DS39612B-page 220 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and flag bit TXxIF is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXxIE. Flag bit TXxIF will be set regardless of the state of enable bit TXxIE and cannot be cleared in software. Flag bit TXxIF is not cleared immediately upon loading the Transmit Buffer register, TXREGx. TXxIF becomes valid in the second instruction cycle following the load instruction. Polling TXxIF immediately following a load of TXREGx will return invalid results. The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTAx<4>). In this mode, the EUSART uses standard non-return-to-zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART module's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. While flag bit TXxIF indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * 2: Flag bit TXxIF is set when enable bit TXEN is set. Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-bit Break Character Transmit Auto-Baud Rate Detection 19.2.1 To set up an Asynchronous Transmission: 1. 2. 3. 4. EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 19-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREGx register (if available). FIGURE 19-2: 5. 6. 7. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXxIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN which will also set bit TXxIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREGx register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb (8) LSb * * * Pin Buffer and Control 0 TSR Register TXx pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGHx SPBRGx Baud Rate Generator 2005 Microchip Technology Inc. SPEN TX9 TX9D DS39612B-page 221 PIC18F6525/6621/8525/8621 FIGURE 19-3: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 19-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 1 TCY TXxIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit bit 0 Word 2 Word 1 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 19-5: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PSPIF(1) ADIF RC1IF PIE1 PSPIE(1) ADIE IPR1 PSPIP(1) ADIP PIR3 -- -- RC2IF PIE3 -- -- RC2IE -- -- RC2IP SPEN RX9 SREN IPR3 RCSTAx TXREGx BAUDCONx SPBRGx Legend: Note 1: Bit 0 Value on all other Resets Bit 2 INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 Enhanced USARTx Transmit Register TXSTAx SPBRGHx Bit 1 Value on POR, BOR Bit 3 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 -1-0 0-00 Enhanced USARTx Baud Rate Generator Register High Byte 0000 0000 0000 0000 Enhanced USARTx Baud Rate Generator Register Low Byte 0000 0000 0000 0000 x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 222 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.2.2 EUSART ASYNCHRONOUS RECEIVER 19.2.3 The receiver block diagram is shown in Figure 19-5. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCxIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCxIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCxIE and GIE bits are set. 8. Read the RCSTAx register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREGx to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. To set up an Asynchronous Reception: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCxIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCxIF will be set when reception is complete and an interrupt will be generated if enable bit RCxIE was set. 7. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREGx register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-5: SETTING UP 9-BIT MODE WITH ADDRESS DETECT EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx Baud Rate Generator / 64 or / 16 or /4 RSR Register MSb Stop (8) 7 * * * 1 LSb Start 0 RX9 Pin Buffer and Control Data Recovery RX9D RXx RCREGx Register FIFO SPEN 8 Interrupt RCxIF Data Bus RCxIE 2005 Microchip Technology Inc. DS39612B-page 223 PIC18F6525/6621/8525/8621 FIGURE 19-6: ASYNCHRONOUS RECEPTION Start bit bit 0 RXx (pin) bit 1 bit 7/8 Stop bit Start bit bit 7/8 bit 0 Rcv Shift Reg Rcv Buffer Reg Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx Read Rcv Buffer Reg RCREGx Stop bit RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer register) is read after the third word causing the OERR (overrun) bit to be set. TABLE 19-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 INT0IF Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x IPR3 RCSTAx RCREGx Enhanced USARTx Receive Register TXSTAx BAUDCONx SPBRGHx SPBRGx Legend: Note 1: 0000 0000 0000 0000 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 -1-0 0-00 Enhanced USARTx Baud Rate Generator Register High Byte 0000 0000 0000 0000 Enhanced USARTx Baud Rate Generator Register Low Byte 0000 0000 0000 0000 x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 224 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line, while the EUSART is operating in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RC1IF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 19-7) and asynchronously, if the device is in Sleep mode (Figure 19-8). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RXx line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 19.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false end-of- FIGURE 19-7: character and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices, or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. 19.2.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCxIF flag is set should not be used as an indicator of the integrity of the data in RCREGx. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note: The EUSART remains in Idle while the WUE bit is set. FIGURE 19-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit RXx/DTx Line Note 1 RCxIF Cleared due to user read of RCREGx Sleep Command Executed Note 1: 2: Sleep Ends If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2005 Microchip Technology Inc. DS39612B-page 225 PIC18F6525/6621/8525/8621 19.2.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREGx will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREGx for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 19-9 for the timing of the Break character sequence. 19.2.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. FIGURE 19-9: Write to TXREGx 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREGx to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREGx becomes empty, as indicated by the TXxIF, the next data byte can be written to TXREGx. 19.2.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the Auto-Wake-up feature described in Section 19.2.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RXx/ DTx, cause an RCxIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXxIF interrupt is observed. SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) DS39612B-page 226 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.3 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCYCLE), the TXREGx is empty and interrupt bit TXxIF is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXxIE. Flag bit TXxIF will be set regardless of the state of enable bit TXxIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register. The Synchronous Master mode is entered by setting the CSRC bit (TXSTAx<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTAx<4>). In addition, enable bit SPEN (RCSTAx<7>) is set in order to configure the TXx and RXx pins to CKx (clock) and DTx (data) lines, respectively. While flag bit TXxIF indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. The Master mode indicates that the processor transmits the master clock on the CKx line. Clock polarity is selected with the SCKP bit (BAUDCONx<4>); setting SCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 19.3.1 To set up a Synchronous Master Transmission: 1. EUSART SYNCHRONOUS MASTER TRANSMISSION 2. The EUSART transmitter block diagram is shown in Figure 19-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). FIGURE 19-10: 3. 4. 5. 6. 7. 8. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXxIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS TRANSMISSION Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 Word 1 bit 0 bit 1 bit 7 Word 2 RC6/TX1/CK1 pin (SCKP = 0) RC6/TX1/CK1 pin (SCKP = 1) Write to TXREG1 Reg Write Word 1 Write Word 2 TX1IF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. 2005 Microchip Technology Inc. DS39612B-page 227 PIC18F6525/6621/8525/8621 FIGURE 19-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit TABLE 19-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x IPR3 RCSTAx TXREGx Enhanced USARTx Transmit Register TXSTAx BAUDCONx 0000 0000 0000 0000 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGHx Enhanced USARTx Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRGx Enhanced USARTx Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: Note 1: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 228 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>), or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. FIGURE 19-12: 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCxIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCxIF will be set when reception is complete and an interrupt will be generated if the enable bit RCxIE was set. 8. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREGx register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC7/TX1/CK1 pin (SCKP = 0) RC7/TX1/CK1 pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RC1IF bit (Interrupt) Read RXREG1 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. 2005 Microchip Technology Inc. DS39612B-page 229 PIC18F6525/6621/8525/8621 TABLE 19-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE (1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x IPR3 RCSTAx RCREGx Enhanced USARTx Receive Register TXSTAx BAUDCONx 0000 0000 0000 0000 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGHx Enhanced USARTx Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRGx Enhanced USARTx Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: Note 1: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 230 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 19.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 19.4.1 Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXxIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2. 3. 4. 5. EUSART SYNCHRONOUS SLAVE TRANSMIT 6. The operation of the Synchronous Master and Slave modes are identical except in the case of the Sleep mode. 7. 8. If two words are written to the TXREGx and then the SLEEP instruction is executed, the following will occur: a) b) c) d) e) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREGx register. Flag bit TXxIF will not be set. When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit TXxIF will now be set. If enable bit TXxIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 19-9: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 (1) 1111 1111 ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 PIR3 PSPIP -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 RCSTAx TXREGx Enhanced USARTx Transmit Register TXSTAx BAUDCONx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGHx Enhanced USARTx Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRGx Enhanced USARTx Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: Note 1: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. DS39612B-page 231 PIC18F6525/6621/8525/8621 19.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode and bit SREN, which is a "don't care" in Slave mode. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCxIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCxIF will be set when reception is complete. An interrupt will be generated if enable bit RCxIE was set. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREGx register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this Low-Power mode. Once the word is received, the RSR register will transfer the data to the RCREGx register; if the RC1IE enable bit is set, the interrupt generated will wake the chip from Low-Power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 6. 7. 8. 9. TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 000u INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR3 -- -- RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 -- -- RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 -- -- RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 RCSTAx RCREGx Enhanced USARTx Receive Register TXSTAx BAUDCONx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 -- RCIDL -- SCKP BRG16 -- WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGHx Enhanced USARTx Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRGx Enhanced USARTx Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: Note 1: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 232 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 20.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The module has five registers: The analog-to-digital (A/D) converter module has 12 inputs for the PIC18F6525/6621 devices and 16 for the PIC18F8525/8621 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and setting the GO/DONE bit immediately. When the GO/DONE bit is set, the selected channel is sampled for the programmed acquisition time before a conversion is actually started. This removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see Register 20-3 and Section 20.5 "A/D Conversions"). REGISTER 20-1: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register 20-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 20-2, configures the functions of the port pins. The ADCON2 register, shown in Register 20-3, configures the A/D clock source, justification and auto-acquisition time. ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(1) 1101 = Channel 13 (AN13)(1) 1110 = Channel 14 (AN14)(1) 1111 = Channel 15 (AN15)(1) Note 1: These channels are not available on the PIC18F6525/6621 (64-pin) devices. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 233 PIC18F6525/6621/8525/8621 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits: A/D VREF+ A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- PCFG3 PCFG0 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN15 bit 3-0 VCFG1 VCFG0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A D D D D D D D D D D D D D D D A D D D D D D D D D D D D D D D A A D D D D D D D D D D D D D D A A A D D D D D D D D D D D D D A A A A D D D D D D D D D D D D A A A A A D D D D D D D D D D D A A A A A A D D D D D D D D D D A A A A A A A D D D D D D D D D A A A A A A A A D D D D D D D D A A A A A A A A A D D D D D D D A A A A A A A A A A D D D D D D A A A A A A A A A A A D D D D D A A A A A A A A A A A A D D D D A A A A A A A A A A A A A D D D A A A A A A A A A A A A A A D D A A A A A A A A A A A A A A A D A = Analog input Note: D = Digital I/O Shaded cells indicate A/D channels available only on PIC18F8525/8621 devices. Legend: DS39612B-page 234 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as `0' bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 000 = 0 TAD(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from A/D RC oscillator)(1) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from A/D RC oscillator)(1) Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 235 PIC18F6525/6621/8525/8621 The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ pin and RA2/AN2/VREF- pin. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion is aborted. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference), or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared and A/D interrupt flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 20-1. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter which generates the result via successive approximation. FIGURE 20-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 0011 (Input Voltage) 10-bit Converter A/D 0010 0001 VCFG1:VCFG0 0000 AVDD AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ Reference Voltage VREFAVSS Note 1: 2: Channels AN15 through AN12 are not available on PIC18F6525/6621 devices. I/O pins have diode protection to VDD and VSS. DS39612B-page 236 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. 2. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 20.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. 3. The following steps should be followed to do an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) FIGURE 20-2: 4. 5. 6. 7. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (not required in case of auto-acquisition time). Start conversion: * Set GO/DONE bit (ADCON0 register) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs VAIN ANx RIC 1k CPIN 5 pF VT = 0.6V SS RSS ILEAKAGE 500 nA CHOLD = 120 pF VSS Legend: CPIN = input capacitance = threshold voltage VT ILEAKAGE = leakage current at the pin due to various junctions = interconnect resistance RIC SS = sampling switch CHOLD = sample/hold capacitance (from DAC) = sampling switch resistance RSS 2005 Microchip Technology Inc. VDD 6V 5V 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k) DS39612B-page 237 PIC18F6525/6621/8525/8621 20.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. Note: = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0 ACQUISITION TIME Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF A/D MINIMUM CHARGING TIME = (VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) = -(120 pF)(1 k + RSS + RS) ln(1/2047) EQUATION 20-3: TACQ CHOLD Rs Conversion Error VDD Temperature VHOLD = EQUATION 20-2: VHOLD or Tc Example 20-3 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 20-1: TACQ To calculate the minimum acquisition time, Equation 20-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. = CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TAMP + TC + TCOFF Temperature coefficient is only required for temperatures > 25C. TACQ = 2 s + TC + [(Temp - 25C)(0.05 s/C)] TC = -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 k + 7 k + 2.5 k) ln(0.0004885) -120 pF (10.5 k) ln(0.0004885) -1.26 s (-7.6241) 9.61 s TACQ = 2 s + 9.61 s + [(50C - 25C)(0.05 s/C)] 11.61 s + 1.25 s 12.86 s DS39612B-page 238 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 20.2 Selecting and Configuring Acquisition Time 20.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: Acquisition time may be set with the ACQT2:ACQT0 bits (ADCON2<5:3>), which provides a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. * * * * * * * Automatic acquisition is selected when the ACQT2:ACQT0 = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT2:ACQT0 bits and is compatible with devices that do not offer programmable acquisition times. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC oscillator Table 20-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18F6525/6621/8525/8621 2 TOSC 000 1.25 MHz 4 TOSC 100 2.50 MHz 8 TOSC 001 5.00 MHz 16 TOSC 101 10.0 MHz 32 TOSC 010 20.0 MHz 64 TOSC 110 40.0 MHz RC x11 -- 2005 Microchip Technology Inc. DS39612B-page 239 PIC18F6525/6621/8525/8621 20.4 Configuring Analog Port Pins The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as a digital input will convert as an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 20.5 A/D Conversions Figure 20-3 shows the operation of the A/D converter after the GODONE bit has been set. Clearing the GO/ DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait is required before the next acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume current out of the device's specification limits. FIGURE 20-3: A/D CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b0 b1 b3 b0 b4 b2 b5 b7 b6 b8 b9 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS39612B-page 240 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 20.6 Use of the ECCP2 Trigger An A/D conversion can be started by the special event trigger of the ECCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/ DONE bit will be set, starting the A/D conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the TABLE 20-2: A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the special event trigger sets the GO/DONE bit and starts a conversion. If the A/D module is not enabled (ADON is cleared), the special event trigger will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter. SUMMARY OF REGISTERS ASSOCIATED WITH A/D Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 (1) PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP IPR2 -1-1 1111 -1-1 1111 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu ADCON0 -- -- CHS3 CHS3 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 ADCON2 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 0-00 0000 PORTA -- RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000 TRISA -- -111 1111 -111 1111 PORTF RF7 RF2 RF1 RF0 x000 0000 u000 0000 1111 1111 1111 1111 0000 xxxx 0000 uuuu 1111 1111 1111 1111 TRISF TRISA6(2) PORTA Data Direction Register RF6 RF5 RF4 RF3 PORTF Data Direction Control Register PORTH (3) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 TRISH(3) PORTH Data Direction Control Register Legend: Note 1: 2: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Enabled only in Microcontroller mode for PIC18F8525/8621 devices. RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read `0' in all other oscillator modes. Implemented on PIC18F8525/8621 devices only, otherwise read as `0'. 3: 2005 Microchip Technology Inc. DS39612B-page 241 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 242 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 21.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RF1 through RF6 pins. The onchip Voltage Reference (Section 22.0 "Comparator Voltage Reference Module") can also be an input to the comparators. REGISTER 21-1: The CMCON register, shown as Register 21-1, controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 21-1. CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RF5/AN10 C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 bit 2-0 CM2:CM0: Comparator Mode bits Figure 21-1 shows the Comparator modes and the CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 243 PIC18F6525/6621/8525/8621 21.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 21-1 shows the eight possible modes. The TRISF register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 21-1: A VIN+ A VIN- A VIN+ RF3/AN8 A VIN- RF5/AN10/ A CVREF VIN+ A VIN- A VIN+ RF4/AN9 RF3/AN8 D VIN- RF5/AN10/ D CVREF VIN+ D VIN- D VIN+ RF6/AN11 C1 Off (Read as `0') RF4/AN9 C2 Off (Read as `0') RF3/AN8 A VIN- RF5/AN10/ A CVREF VIN+ RF6/AN11 C1 C1 Off (Read as `0') C2 Off (Read as `0') Two Independent Comparators with Outputs CM2:CM0 = 011 Two Independent Comparators CM2:CM0 = 010 RF6/AN11 Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. Comparators Off CM2:CM0 = 111 VIN- RF5/AN10/ A CVREF RF4/AN9 Note: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) CM2:CM0 = 000 RF6/AN11 mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 27.0 "Electrical Characteristics". C1OUT C1 C1OUT C2 C2OUT RF2/AN7/C1OUT C2 RF4/AN9 C2OUT RF3/AN8 A VIN- A VIN+ RF1/AN6/C2OUT Two Common Reference Comparators CM2:CM0 = 100 A VIN- RF5/AN10/ A CVREF VIN+ A VIN- D VIN+ RF6/AN11 Two Common Reference Comparators with Outputs CM2:CM0 = 101 A VIN- RF5/AN10/ A CVREF VIN+ RF6/AN11 C1 C1OUT C1 C1OUT C2 C2OUT RF2/AN7/C1OUT RF4/AN9 RF3/AN8 C2 C2OUT RF4/AN9 RF3/AN8 A VIN- D VIN+ RF1/AN6/C2OUT Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 One Independent Comparator with Output CM2:CM0 = 001 RF6/AN11 A VIN- VIN+ RF5/AN10/ A CVREF RF2/AN7/C1OUT RF4/AN9 RF3/AN8 D VIN- D VIN+ RF6/AN11 C1 C1OUT RF3/AN8 Off (Read as `0') A = Analog Input, port reads zeros always DS39612B-page 244 RF5/AN10/ A CVREF RF4/AN9 C2 D = Digital Input A CIS = 0 CIS = 1 VINVIN+ C1 C1OUT C2 C2OUT A A CIS = 0 CIS = 1 VINVIN+ CVREF From VREF Module CIS (CMCON<3>) is the Comparator Input Switch 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 21.2 21.3.2 Comparator Operation INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 21-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 21-2 represent the uncertainty due to input offsets and response time. The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 22.0 "Comparator Voltage Reference Module" contains a detailed description of the comparator voltage reference module that provides this signal. The internal reference signal is used when comparators are in mode CM<2:0> = 110 (Figure 21-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 21.3 21.4 Comparator Reference An external or internal reference signal may be used depending on the comparator operating mode. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 21-2). FIGURE 21-2: VIN+ VIN- SINGLE COMPARATOR + Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Section 27.0 "Electrical Characteristics"). 21.5 Output - VINVIN+ Comparator Response Time Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 21-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RF1 and RF2 pins while in this mode. Output The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). 21.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same, or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s). 2005 Microchip Technology Inc. Note 1: When reading the Port register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. DS39612B-page 245 PIC18F6525/6621/8525/8621 FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RF1 or RF2 Pin Bus Data Q Read CMCON Set CMIF bit D EN Q From Other Comparator D EN CL Read CMCON Reset 21.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR registers) is the comparator interrupt flag. The CMIF bit must be reset by clearing `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. DS39612B-page 246 Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 21.7 Comparator Operation During Sleep 21.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators, CM<2:0> = 111, before entering Sleep. If the device wakes up from Sleep, the contents of the CMCON register are not affected. 21.8 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 21-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator module to be in the comparator Reset mode, CM<2:0> = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at Reset time. The comparators will be powered down during the Reset interval. FIGURE 21-4: COMPARATOR ANALOG INPUT MODEL VDD VT = 0.6V RS < 10k RIC Comparator Input AIN VA CPIN 5 pF VT = 0.6V ILEAKAGE 500 nA VSS Legend: CPIN VT ILEAKAGE RIC RS VA 2005 Microchip Technology Inc. = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage DS39612B-page 247 PIC18F6525/6621/8525/8621 TABLE 21-1: Name CMCON REGISTERS ASSOCIATED WITH COMPARATOR MODULE INTCON Bit 3 Bit 2 Bit 1 Bit 0 Value on all other Resets Bit 6 Bit 5 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u CVRCON CVREN CVROE Bit 4 Value on POR Bit 7 GIE/ GIEH PEIE/ GIEL PIR2 -- CMIF -- EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 -- CMIE -- EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 IPR2 -- CMIP -- EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 u000 0000 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 PORTF Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are unused by the comparator module. DS39612B-page 248 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 22.0 COMPARATOR VOLTAGE REFERENCE MODULE 22.1 The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 22-1. The block diagram is given in Figure 22-1. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA3 and RA2. The comparator reference supply voltage is controlled by the CVRSS bit. REGISTER 22-1: Configuring the Comparator Voltage Reference The comparator voltage reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = (CVR<3:0>/24) x CVRSRC If CVRR = 0: CVREF = (CVRSRC x 1/4) + (CVR<3:0>/32) x CVRSRC The settling time of the comparator voltage reference must be considered when changing the CVREF output (Section 27.0 "Electrical Characteristics"). CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5> to `1'. bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ - VREF0 = Comparator reference source, CVRSRC = AVDD - AVSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 VR3:VR0 15) When CVRR = 1: CVREF = (CVR<3:0>/ 24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (CVR3:CVR0/32) * (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 249 PIC18F6525/6621/8525/8621 FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM AVDD VREF+ CVRSS = 0 16 Stages CVRSS = 1 CVREN 8R R R R R CVRR 8R CVRSS = 0 CVRSS = 1 CVREF 16-1 Analog Mux VREFCVR3 (From CVRCON<3:0>) CVR0 Note: R is defined in Section 27.0 "Electrical Characteristics". 22.2 Voltage Reference Accuracy/Error 22.4 Effects of a Reset The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 22-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 27.0 "Electrical Characteristics". A device Reset disables the voltage reference by clearing bit CVREN (CVRCON<7>). This Reset also disconnects the reference from the RA2 pin by clearing bit CVROE (CVRCON<6>) and selects the highvoltage range by clearing bit CVRR (CVRCON<5>). The VRSS value select bits, CVRCON<3:0>, are also cleared. 22.3 The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RF5 pin if the TRISF<5> bit is set and the CVROE bit is set. Enabling the voltage reference output onto the RF5 pin configured as a digital input will increase current consumption. Connecting RF5 as a digital output with VRSS enabled will also increase current consumption. Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 22.5 Connection Considerations The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 22-2 shows an example buffering technique. DS39612B-page 250 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) CVREF Module RF5 + - CVREF Output Voltage Reference Output Impedance Note 1: TABLE 22-1: Name R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 CVRCON CVREN CVROE Value on POR Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 TRISF2 TRISF1 CMCON C2OUT C1OUT TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used with the comparator voltage reference. 2005 Microchip Technology Inc. DS39612B-page 251 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 252 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 23.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks" before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower then the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. Figure 23-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shutdown the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference TB - TA is the total time for shutdown. TYPICAL LOW-VOLTAGE DETECT APPLICATION Voltage FIGURE 23-1: The Low-Voltage Detect circuitry is completely under software control. This allows the circuitry to be "turned off" by the software which minimizes the current consumption for the device. VA VB Legend: VA = LVD trip point VB = Minimum valid device operating voltage Time TA TB The block diagram for the LVD module is shown in Figure 23-2. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the 2005 Microchip Technology Inc. supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2V internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 23-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). DS39612B-page 253 PIC18F6525/6621/8525/8621 FIGURE 23-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVDL3:LVDL0 LVDCON Register 16 to 1 MUX VDD Internally Generated Reference Voltage LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, FIGURE 23-3: LVDIF LVDIN (Figure 23-3). This gives users flexibility because it allows them to configure the Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD LVDCON Register 16 to 1 MUX LVDL3:LVDL0 LVDIN Externally Generated Trip Point LVDEN LVD VxEN BODEN EN BGAP DS39612B-page 254 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 23.1 Control Register The Low-Voltage Detect (Register 23-1) controls the Low-Voltage Detect circuitry. REGISTER 23-1: Control operation register of the LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 -- -- IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.45V-4.83V 1101 = 4.16V-4.5V 1100 = 3.96V-4.3V 1011 = 3.76V-3.92V 1010 = 3.57V-3.87V 1001 = 3.47V-3.75V 1000 = 3.27V-3.55V 0111 = 2.98V-3.22V 0110 = 2.77V-3.01V 0101 = 2.67V-2.89V 0100 = 2.48V-2.68V 0011 = 2.37V-2.57V 0010 = 2.18V-2.36V 0001 = 1.98V-2.14V 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 255 PIC18F6525/6621/8525/8621 23.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. 4. 5. 6. Write the value to the LVDL3:LVDL0 bits (LVDCON register) which selects the desired LVD trip point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure 23-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 23-4: LOW-VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIRVST LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIRVST LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS39612B-page 256 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 23.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36. The low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 23-4. 23.2.2 CURRENT CONSUMPTION 23.3 Operation During Sleep When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 23.4 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off. When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter D022B. 2005 Microchip Technology Inc. DS39612B-page 257 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 258 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 24.0 SPECIAL FEATURES OF THE CPU Sleep mode is designed to offer a very low current power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits is used to select various options. There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. These are: * Oscillator Selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Sleep * Code Protection * ID Locations * In-Circuit Serial Programming 24.1 The configuration bits can be programmed (read as `0') or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped, starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h through 3FFFFFh) which can only be accessed using table reads and table writes. All PIC18F6525/6621/8525/8621 devices have a Watchdog Timer which is permanently enabled via the configuration bits, or software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT) which provides a fixed delay on power-up only, designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry. TABLE 24-1: Configuration Bits Programming the Configuration registers is done in a manner similar to programming the Flash memory. The EECON1 register WR bit starts a self-timed write to the Configuration register. In normal operation mode, a TBLWT instruction, with the TBLPTR pointed to the Configuration register, sets up the address and the data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. CONFIGURATION BITS AND DEVICE IDS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value CONFIG1H -- -- OSCSEN -- FOSC3 FOSC2 FOSC1 FOSC0 --1- 1111 300002h CONFIG2L -- -- -- -- BORV1 BORV0 300003h CONFIG2H -- -- -- WAIT -- -- File Name 300001h 300004h(1) CONFIG3L WDTPS3 WDTPS2 WDTPS1 -- -- -- BOR PWRTEN ---- 1111 WDTPS0 WDTEN ---1 1111 PM1 PM0 1--- --11 CCP2MX 1--- --11 (1) 300005h CONFIG3H MCLRE -- -- -- -- -- 300006h CONFIG4L DEBUG -- -- -- -- LVP -- STVREN 1--- -1-1 300008h CONFIG5L -- -- -- -- CP3(2) CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 11-- ---- 30000Ah CONFIG6L -- -- -- -- WRT3(2) WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC -- -- -- -- -- 111- ---- 30000Ch CONFIG7L -- -- -- -- EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H -- EBTRB -- -- -- -- -- -- -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 (Note 3) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1010 Legend: Note 1: 2: 3: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. Unimplemented in PIC18F6525/6621 devices; maintain this bit set. Unimplemented in PIC18FX525 devices; maintain this bit set. See Register 24-13 for DEVID1 values. 2005 Microchip Technology Inc. EBTR3(2) EBTR2 ECCPMX DS39612B-page 259 PIC18F6525/6621/8525/8621 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 -- -- OSCSEN -- FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4 Unimplemented: Read as `0' bit 3-0 FOSC3:FOSC0: Oscillator Selection bits 1111 = RC oscillator with OSC2 configured as RA6 1110 = HS oscillator with SW enabled 4x PLL 1101 = EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL 1100 = EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL 1011 = Reserved; do not use 1010 = Reserved; do not use 1001 = Reserved; do not use 1000 = Reserved; do not use 0111 = RC oscillator with OSC2 configured as RA6 0110 = HS oscillator with HW enabled 4x PLL 0101 = EC oscillator with OSC2 configured as RA6 0100 = EC oscillator with OSC2 configured as divide by 4 clock output 0011 = RC oscillator with OSC2 configured as divide by 4 clock output 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed DS39612B-page 260 U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 -- -- -- -- BORV1 BORV0 BOR PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as `0' bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOR: Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed REGISTER 24-3: U = Unimplemented bit, read as `0' u = Unchanged from programmed state CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 -- -- -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as `0' bit 4-1 WDTPS2:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed 2005 Microchip Technology Inc. U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39612B-page 261 PIC18F6525/6621/8525/8621 REGISTER 24-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1) R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT -- -- -- -- -- PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as `0' bit 1-0 PM1:PM0: Processor Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microprocessor with Boot Block mode 00 = Extended Microcontroller mode Note 1: This register is unimplemented for PIC18F6525/6621 devices; maintain these bits set. Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed REGISTER 24-5: U = Unimplemented bit, read as `0' u = Unchanged from programmed state CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 MCLRE(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 R/P-1 R/P-1 -- ECCPMX(2) CCP2MX bit 7 bit 0 bit 7 MCLRE: MCLR Enable bit(1) 1 = MCLR pin enabled, RG5 input pin disabled 0 = RG5 input enabled, MCLR disabled bit 6-2 Unimplemented: Read as `0' bit 1 ECCPMX: ECCP Mux bit(2) 1 = ECCP1 (P1B/P1C) and ECCP3 (P3B/P3C) PWM outputs are multiplexed with RE6 through RE3 0 = ECCP1 (P1B/P1C) and ECCP3 (P3B/P3C) PWM outputs are multiplexed with RH7 through RH4 bit 0 CCP2MX: ECCP2 Mux bit In Microcontroller mode: 1 = ECCP2 input/output is multiplexed with RC1 0 = ECCP2 input/output is multiplexed with RE7 In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes (PIC18F8525/8621 devices only): 1 = ECCP2 input/output is multiplexed with RC1 0 = ECCP2 input/output is multiplexed with RB3 Note 1: If MCLR is disabled, either disable Low-Voltage ICSP or hold RB5/KBI1/PGM low to ensure proper entry into ICSP mode. 2: This register is unimplemented for PIC18F6525/6621 devices; maintain these bits set. Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed DS39612B-page 262 U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG -- -- -- -- LVP -- STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. bit 6-3 Unimplemented: Read as `0' bit 2 LVP: Low-Voltage ICSP Enable bit 1 = Low-Voltage ICSP enabled 0 = Low-Voltage ICSP disabled bit 1 Unimplemented: Read as `0' bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' -n = Value when device is unprogrammed REGISTER 24-7: u = Unchanged from programmed state CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 -- U-0 -- U-0 -- U-0 R/C-1 R/C-1 R/C-1 R/C-1 -- CP3(1) CP2 CP1 CP0 bit 7 bit 0 bit 7-4 bit 3 Unimplemented: Read as `0' CP3: Code Protection bit(1) 1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected bit 2 CP2: Code Protection bit 1 = Block 2 (008000-00BFFFh) not code-protected 0 = Block 2 (008000-00BFFFh) code-protected CP1: Code Protection bit 1 = Block 1 (004000-007FFFh) not code-protected 0 = Block 1 (004000-007FFFh) code-protected CP0: Code Protection bit 1 = Block 0 (000800-003FFFh) not code-protected 0 = Block 0 (000800-003FFFh) code-protected Note 1: Unimplemented in PIC18FX525 devices; maintain this bit set. bit 1 bit 0 Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed 2005 Microchip Technology Inc. U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39612B-page 263 PIC18F6525/6621/8525/8621 REGISTER 24-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB -- -- -- -- -- -- bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) not code-protected 0 = Boot block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed REGISTER 24-9: U = Unimplemented bit, read as `0' u = Unchanged from programmed state CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 -- U-0 -- U-0 -- U-0 R/C-1 R/C-1 R/C-1 R/C-1 -- WRT3(1) WRT2 WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as `0' bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (00C000-00FFFFh) not write-protected 0 = Block 3 (00C000-00FFFFh) write-protected Note 1: Unimplemented in PIC18FX525 devices; maintain this bit set. bit 2 WRT2: Write Protection bit 1 = Block 2 (008000-00BFFFh) not write-protected 0 = Block 2 (008000-00BFFFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (004000-007FFFh) not write-protected 0 = Block 1 (004000-007FFFh) write-protected bit 0 WR0: Write Protection bit 1 = Block 0 (000800-003FFFh) not write-protected 0 = Block 0 (000800-003FFFh) write-protected Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed DS39612B-page 264 U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 REGISTER 24-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC -- -- -- -- -- bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0007FFh) not write-protected 0 = Boot block (000000-0007FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected bit 4-0 Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state REGISTER 24-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 -- -- -- -- EBTR3(1) EBTR2 EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as `0' bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18FX525 devices; maintain this bit set. bit 2 EBTR2: Table Read Protection bit 1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800-003FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800-003FFFh) protected from table reads executed in other blocks Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed 2005 Microchip Technology Inc. U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39612B-page 265 PIC18F6525/6621/8525/8621 REGISTER 24-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 -- EBTRB -- -- -- -- -- -- bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot block (000000-0007FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state REGISTER 24-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6525/6621/8525/8621 DEVICES (ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 100 = PIC18F8621 101 = PIC18F6621 110 = PIC18F8525 111 = PIC18F6525 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state REGISTER 24-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F6525/6621/8525/8621 DEVICES (ADDRESS 3FFFFFh) R-0 R-0 R-0 R-0 R-1 R-0 R-1 R-0 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 7-0 bit 0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0000 1010 = PIC18F6525/6621/8525/8621 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed DS39612B-page 266 U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 24.2 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction. The WDT time-out period values may be found in the Electrical Specifications section under parameter 31. Values for the WDT postscaler may be assigned using the configuration bits. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT and prevent it from timing out and generating a device Reset condition. 2: When a CLRWDT instruction is executed and the postscaler is assigned to the WDT, the postscaler count will be cleared but the postscaler assignment is not changed. During normal operation, a WDT time-out generates a device Reset (Watchdog Timer Reset). If the device is in Sleep mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer wake-up). The TO bit in the RCON register will be cleared upon a WDT time-out. The Watchdog Timer is enabled or disabled by a device configuration bit, WDTEN (CONFIG2H<0>). If WDTEN is set, software execution may not disable this function. When WDTEN is cleared, the SWDTEN bit enables or disables the operation of the WDT. 24.2.1 CONTROL REGISTER Register 24-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable configuration bit only when the configuration bit has disabled the WDT. REGISTER 24-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- SWDTEN bit 7 bit 0 bit 7-1 Unimplemented: Read as `0' bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off (if CONFIG2H<0> = 0) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2005 Microchip Technology Inc. x = Bit is unknown DS39612B-page 267 PIC18F6525/6621/8525/8621 24.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming by the value written to the CONFIG2H Configuration register. FIGURE 24-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 16 16-to-1 MUX WDTEN Configuration bit WDTPS3:WDTPS0 SWDTEN bit WDT Time-out Note: TABLE 24-2: WDTPS3:WDTPS0 are bits in register CONFIG2H. SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Name CONFIG2H RCON WDTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN IPEN -- -- RI TO PD POR BOR -- -- -- -- -- -- -- SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. DS39612B-page 268 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 24.3 Power-Down Mode (Sleep) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or high-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are high-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 24.3.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from INTx pin, RB port change or a peripheral interrupt. The following peripheral interrupts can wake the device from Sleep: 1. 2. PSP read or write. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. TMR3 interrupt. Timer3 must be operating as an asynchronous counter. 4. CCP Capture mode interrupt (Capture will not occur). 5. MSSP (Start/Stop) bit detect interrupt. 6. MSSP transmit or receive in Slave mode (SPI/I2C). 7. USART RXx or TXx (Synchronous Slave mode). 8. A/D conversion (when A/D clock source is RC). 9. EEPROM write operation complete. 10. LVD interrupt. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. External MCLR Reset will cause a device Reset. All other events are considered a continuation of program execution and will cause a "wake-up". The TO and PD bits in the RCON register can be used to determine the cause of the device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). When the SLEEP instruction is being executed, the next instruction (PC + 2) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the instruction following Sleep is not desirable, the user should have a NOP after the SLEEP instruction. 24.3.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 2005 Microchip Technology Inc. DS39612B-page 269 PIC18F6525/6621/8525/8621 WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) FIGURE 24-2: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 24.4 1: 2: 3: 4: PC PC + 2 Inst(PC) = Sleep Inst(PC - 1) PC + 4 PC + 4 PC + 4 Inst(PC + 4) Inst(PC + 2) Inst(PC + 2) Sleep Dummy Cycle 0008h 000Ah Inst(0008h) Inst(000Ah) Dummy Cycle Inst(0008h) XT, HS or LP Oscillator mode assumed. GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes. CLKO is not available in these oscillator modes but shown here for timing reference. Program Verification and Code Protection Each of the blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PICmicro devices. * Code-Protect bit (CPn) * Write-Protect bit (WRTn) * External Block Table Read bit (EBTRn) The user program memory is divided on binary boundaries into four blocks of 16 Kbytes each. The first block is further divided into a boot block of 2048 bytes and a second block (Block 0) of 14 Kbytes. Figure 24-3 shows the program memory organization for 48 and 64-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 24-3. FIGURE 24-3: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6525/6621/8525/8621 DEVICES MEMORY SIZE/DEVICE Block Code Protection Controlled By: 48 Kbytes (PIC18FX525) 64 Kbytes (PIC18FX621) Address Range Boot Block Boot Block 000000h 0007FFh CPB, WRTB, EBTRB Block 0 Block 0 000800h 003FFFh CP0, WRT0, EBTR0 Block 1 Block 1 004000h CP1, WRT1, EBTR1 007FFFh 008000h Block 2 Block 2 CP2, WRT2, EBTR2 00BFFFh 00C000h Unimplemented, read `0' Block 3 CP3, WRT3, EBTR3 00FFFFh DS39612B-page 270 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH CODE PROTECTION File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L -- -- -- -- CP3(1) CP2 CP1 CP0 300009h CONFIG5H CPD CPB -- -- -- -- -- -- WRT2 WRT1 WRT0 -- -- -- EBTR2 EBTR1 EBTR0 -- -- -- 30000Ah CONFIG6L -- -- -- -- 30000Bh CONFIG6H WRTD WRTB WRTC -- 30000Ch CONFIG7L -- -- -- -- 30000Dh CONFIG7H -- EBTRB -- -- (1) WRT3 -- EBTR3 -- (1) Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18FX525 devices. 24.4.1 PROGRAM MEMORY CODE PROTECTION The user memory may be read to or written from any location using the table read and table write instructions. The Device ID register may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. In user mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is `0'. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to `0', a table read instruction that executes from within that block is allowed to read. A 2005 Microchip Technology Inc. table read instruction that executes from a location outside of that block is not allowed to read and will result in reading `0's. Figures 24-4 through 24-6 illustrate table write and table read protection. Note: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. DS39612B-page 271 PIC18F6525/6621/8525/8621 FIGURE 24-4: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 000FFFh WRTB,EBTRB = 11 WRT0,EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1,EBTR1 = 11 007FFFh 008000h PC = 008FFEh WRT2,EBTR2 = 11 TBLWT* 00BFFFh 00C000h WRT3,EBTR3 = 11 00FFFFh Results: All table writes disabled to Block n whenever WRTn = 0. FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 000FFFh WRTB,EBTRB = 11 WRT0,EBTR0 = 10 003FFFh 004000h PC = 004FFEh TBLRD* WRT1,EBTR1 = 11 007FFFh 008000h WRT2,EBTR2 = 11 00BFFFh 00C000h WRT3,EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0. TABLAT register returns a value of `0'. DS39612B-page 272 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 24-6: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 000FFFh PC = 003FFEh WRTB,EBTRB = 11 WRT0,EBTR0 = 10 TBLRD* 003FFFh 004000h WRT1,EBTR1 = 11 007FFFh 008000h WRT2,EBTR2 = 11 00BFFFh 00C000h WRT3,EBTR3 = 11 00FFFFh Results: Table reads permitted within Block n, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. 24.4.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read data EEPROM regardless of the protection bit settings. 2005 Microchip Technology Inc. 24.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers. In user mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. DS39612B-page 273 PIC18F6525/6621/8525/8621 24.5 ID Locations 24.8 Eight memory locations (200000h-200007h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are accessible during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code-protected. 24.6 In-Circuit Serial ProgrammingTM (ICSPTM) PIC18F6525/6621/8525/8621 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 24.7 In-Circuit Debugger When the DEBUG bit in Configuration register, CONFIG4L, is programmed to a `0', the in-circuit debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 24-4 shows which features are consumed by the background debugger. TABLE 24-4: DEBUGGER RESOURCES I/O pins Stack RB6, RB7 2 levels Program Memory 512 bytes Data Memory 10 bytes To use the in-circuit debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the in-circuit debugger module available from Microchip or one of the third party development tool companies. Low-Voltage ICSP Programming The LVP bit in Configuration register, CONFIG4L, enables Low-Voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB5/KBI1/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. During programming, VDD is applied to the MCLR/VPP pin. To enter Programming mode, VDD must be applied to the RB5/KBI1/PGM pin provided the LVP bit is set. The LVP bit defaults to a `1' from the factory. Note 1: The High-Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low-Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O pin and should be held low during normal operation. 3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 5 in the TRISB register must be cleared to disable the pull-up on RB5 and ensure the proper operation of the device. 4: If the device Master Clear is disabled, verify that either of the following is done to ensure proper entry into ICSP mode: a.) disable Low-Voltage Programming (CONFIG4L<2> = 0); or b.) make certain that RB5/KBI1/PGM is held low during entry into ICSP. If Low-Voltage Programming mode is not used, the LVP bit can be programmed to a `0' and RB5/KBI1/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on MCLR/VPP. It should be noted that once the LVP bit is programmed to `0', only the High-Voltage Programming mode is available and only High-Voltage Programming mode can be used to program the device. When using Low-Voltage ICSP, the part must be supplied 4.5V to 5.5V if a bulk erase will be executed. This includes reprogramming of the code-protect bits from an on-state to off-state. For all other cases of LowVoltage ICSP, the part may be programmed at the normal operating voltage. This means unique user IDs or user code can be reprogrammed or added. DS39612B-page 274 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 25.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PICmicro(R) instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 25-2 lists byte-oriented, bit-oriented, literal and control operations. Table 25-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the call or return instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for three double-word instructions. These three instructions were made double-word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. All bit-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. 1. 2. Figure 25-1 shows the general formats that the instructions can have. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. 2005 Microchip Technology Inc. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 25-2, lists the instructions recognized by the Microchip MPASMTM Assembler. Section 25.1 "Instruction Set" provides a description of each instruction. DS39612B-page 275 PIC18F6525/6621/8525/8621 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location. f 8-bit register file address (0x00 to 0xFF). fs 12-bit register file address (0x000 to 0xFFF). This is the source address. fd 12-bit register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) +* n The relative address (2's complement number) for relative branch instructions, or the direct address for call/ branch and return instructions. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or unchanged. WREG Working register (accumulator). x Don't care (`0' or `1') The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TOS Top-of-Stack. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. GIE Global Interrupt Enable bit. WDT Watchdog Timer. TO Time-out bit. PD Power-down bit. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. [ ] Optional. ( ) Contents. Assigned to. < > Register bit field. In the set of. italics User defined term (font is courier). DS39612B-page 276 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 OPCODE b (BIT #) a 0 f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 OPCODE 0 k (literal) MOVLW 0x7F k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 OPCODE 15 0 n<7:0> (literal) 12 11 GOTO Label 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 OPCODE 15 S 0 CALL MYFUNC n<7:0> (literal) 12 11 0 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 2005 Microchip Technology Inc. 11 10 0 BRA MYFUNC n<10:0> (literal) 8 7 n<7:0> (literal) 0 BC MYFUNC DS39612B-page 277 PIC18F6525/6621/8525/8621 TABLE 25-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a SUBWF SUBWFB f, d, a f, d, a SWAPF TSTFSZ XORWF f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 1 1 0101 11da 0101 10da ffff ffff ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N 1, 2 1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da ffff ffff ffff ffff None ffff None ffff Z, N 4 1, 2 1 1 1 (2 or 3) 1 (2 or 3) 1 ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1, 2 1, 2 3, 4 3, 4 1, 2 None None C, DC, Z, OV, N 1, 2 C, Z, N Z, N 1, 2 C, Z, N Z, N None C, DC, Z, OV, N 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS BTG Note 1: 2: 3: 4: 5: f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39612B-page 278 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO -- -- n NOP NOP POP PUSH RCALL RESET RETFIE -- -- -- -- n RETLW RETURN SLEEP Note 1: 2: 3: 4: 5: 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable k s -- Return with literal in WREG Return from Subroutine Go into Standby mode 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 2 2 1 0000 1100 0000 0000 0000 0000 kkkk 0001 0000 1 1 2 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. 2005 Microchip Technology Inc. DS39612B-page 279 PIC18F6525/6621/8525/8621 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None None None None None C, DC, Z, OV, N Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: 2: 3: 4: 5: Table Read 2 Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write 2 (5) Table Write with post-increment Table Write with post-decrement Table Write with pre-increment When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39612B-page 280 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 25.1 Instruction Set ADDLW Add Literal to W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: k 1111 kkkk 1 Cycles: 1 Add W to f Syntax: [ label ] ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z kkkk The contents of W are added to the 8-bit literal `k' and the result is placed in W. Words: ADDWF Encoding: 0010 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to W Example: 01da ffff ffff Description: Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR is used. Words: 1 Cycles: 1 Q Cycle Activity: Decode f [,d [,a] f [,d [,a] Q Cycle Activity: ADDLW 0x15 Before Instruction W = 0x10 After Instruction W = 0x25 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWF Before Instruction W = REG = After Instruction W = REG = 2005 Microchip Technology Inc. REG, 0, 0 0x17 0xC2 0xD9 0xC2 DS39612B-page 281 PIC18F6525/6621/8525/8621 ADDWFC Add W and Carry bit to f ANDLW Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f [,d [,a] Operation: (W) + (f) + (C) dest Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 00da Encoding: ffff ffff Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden. Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination ADDWFC Before Instruction Carry bit = REG = W = 1 0x02 0x4D After Instruction Carry bit = REG = W = 0 0x02 0x50 DS39612B-page 282 0000 k 1011 kkkk kkkk Description: The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: Q Cycle Activity: Example: AND Literal with W ANDLW Before Instruction W = After Instruction W = 0x5F 0xA3 0x03 REG, 0, 1 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a] BC Branch if Carry Syntax: [ label ] BC Operands: -128 n 127 Operation: if Carry bit is `1' (PC) + 2 + 2n PC None Operation: (W) .AND. (f) dest Status Affected: Status Affected: N, Z Encoding: Encoding: 0001 01da ffff ffff Description: The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `d' (default). If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ANDWF Before Instruction W = REG = After Instruction W = REG = 1110 Description: 0x02 0xC2 1 Cycles: 1(2) nnnn nnnn Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Carry PC If Carry PC 2005 Microchip Technology Inc. 0010 If the Carry bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: REG, 0, 0 0x17 0xC2 n BC 5 = address (HERE) = = = = 1; address (HERE + 12) 0; address (HERE + 2) DS39612B-page 283 PIC18F6525/6621/8525/8621 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 255 0b7 a [0,1] f,b[,a] BN Branch if Negative Syntax: [ label ] BN Operands: -128 n 127 Operation: if Negative bit is `1' (PC) + 2 + 2n PC None Operation: 0 f<b> Status Affected: Status Affected: None Encoding: Encoding: 1001 bbba ffff ffff Description: Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BCF Before Instruction FLAG_REG After Instruction FLAG_REG FLAG_REG, = 0xC7 = 0x47 7, 0 1110 Description: 0110 nnnn nnnn If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC DS39612B-page 284 n BN Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is `0' (PC) + 2 + 2n PC Operation: if Negative bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0011 nnnn nnnn Encoding: 1110 If the Carry bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Description: Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: n 0111 nnnn nnnn If the Negative bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: Example: If No Jump: HERE Before Instruction PC After Instruction If Carry = PC = If Carry = PC = = BNC Jump address (HERE) 0; address (Jump) 1; address (HERE + 2) 2005 Microchip Technology Inc. Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC BNN Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) DS39612B-page 285 PIC18F6525/6621/8525/8621 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is `0' (PC) + 2 + 2n PC Operation: if Zero bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0101 nnnn nnnn Encoding: 1110 If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Description: Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: n 0001 nnnn nnnn If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: If No Jump: Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC DS39612B-page 286 BNOV Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) Example: HERE Before Instruction PC After Instruction If Zero = PC = If Zero = PC = = BNZ Jump address (HERE) 0; address (Jump) 1; address (HERE + 2) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 BRA Unconditional Branch BSF Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation Bit Set f Operation: 1 f<b> Status Affected: None Encoding: HERE Before Instruction PC = After Instruction PC = BRA Jump address (HERE) bbba ffff ffff Description: Bit `b' in register `f' is set. If `a' is `0', Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: Example: 1000 f,b[,a] BSF Before Instruction FLAG_REG After Instruction FLAG_REG FLAG_REG, 7, 1 = 0x0A = 0x8A address (Jump) 2005 Microchip Technology Inc. DS39612B-page 287 PIC18F6525/6621/8525/8621 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Description: If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation Decode Read register `f' Process Data No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC DS39612B-page 288 BTFSC : : FLAG, 1, 0 = address (HERE) = = = = 0; address (TRUE) 1; address (FALSE) Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC BTFSS : : FLAG, 1, 0 = address (HERE) = = = = 0; address (FALSE) 1; address (TRUE) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is `1' (PC) + 2 + 2n PC None Operation: (f<b>) f<b> Status Affected: Status Affected: None Encoding: Encoding: 0111 bbba ffff ffff Description: Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BTG PORTC, 4, 0 Before Instruction: PORTC = 0111 0101 [0x75] After Instruction: PORTC = 0110 0101 [0x65] 1110 Description: 0100 nnnn nnnn If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC 2005 Microchip Technology Inc. n BOV Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) DS39612B-page 289 PIC18F6525/6621/8525/8621 BZ Branch if Zero CALL Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 n 127 Operands: Operation: if Zero bit is `1' (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS; k PC<20:1> if s = 1 (W) WS; (STATUS) STATUSS; (BSR) BSRS Status Affected: None Status Affected: n Subroutine Call None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Q1 Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation If No Jump: Example: HERE Before Instruction PC = After Instruction If Zero = PC = If Zero = PC = DS39612B-page 290 BZ k7kkk kkkk 110s k19kkk Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, Push PC to stack Read literal `k'<19:8>, Write to PC No operation No operation No operation No operation Jump address (HERE) 1; address (Jump) 0; address (HERE + 2) kkkk0 kkkk8 Description: Q Cycle Activity: If Jump: Decode 1110 1111 Example: HERE Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS= CALL THERE,1 address (HERE) address (THERE) address (HERE + 4) W BSR STATUS 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f; 1Z Status Affected: Z Encoding: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT; 000h WDT postscaler; 1 TO; 1 PD Status Affected: TO, PD Clears the contents of the specified register. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Encoding: Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Description: Q Cycle Activity: 0000 0000 0000 0100 Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Decode No operation Process Data No operation Example: CLRF Before Instruction FLAG_REG After Instruction FLAG_REG FLAG_REG,1 = 0x5A = 0x00 2005 Microchip Technology Inc. Example: CLRWDT Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD = ? = = = = 0x00 0 1 1 DS39612B-page 291 PIC18F6525/6621/8525/8621 COMF Complement f Syntax: [ label ] COMF Operands: 0 f 255 d [0,1] a [0,1] Operation: ( f ) dest Status Affected: N, Z Encoding: 0001 Description: CPFSEQ f [,d [,a] 11da ffff ffff The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: COMF Before Instruction REG = After Instruction REG = W = REG, 0, 0 Syntax: [ label ] CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) - (W); skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 Description: 001a f [,a] ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: 0x13 0x13 0xEC Compare f with W, Skip if f = W Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: DS39612B-page 292 HERE NEQUAL EQUAL CPFSEQ REG, 0 : : Before Instruction PC Address W REG = = = HERE ? ? After Instruction If REG PC If REG PC = = = W; Address (EQUAL) W; Address (NEQUAL) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 CPFSGT Compare f with W, Skip if f > W CPFSLT Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) - (W); skip if (f) > (W) (unsigned comparison) Operation: (f) - (W); skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: f [,a] 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Encoding: Q1 Q2 Q3 Q4 Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: 0110 Description: 1 Cycles: 1(2) Note: Q2 Q3 Q4 Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation HERE NGREATER GREATER CPFSGT REG, 0 : : 2005 Microchip Technology Inc. 3 cycles if skip and followed by a 2-word instruction. Read register `f' No operation W; Address (GREATER) W; Address (NGREATER) ffff Q1 Q1 Address (HERE) ? ffff Decode No operation Before Instruction PC = W = After Instruction If REG > PC = If REG PC = 000a Q Cycle Activity: No operation Example: f [,a] Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected. If `a' is `1', the BSR will not be overridden (default). Words: Q Cycle Activity: Decode Compare f with W, Skip if f < W Example: HERE NLESS LESS Before Instruction PC = W = After Instruction If REG < PC = If REG PC = CPFSLT REG, 1 : : Address (HERE) ? W; Address (LESS) W; Address (NLESS) DS39612B-page 293 PIC18F6525/6621/8525/8621 DAW Decimal Adjust W Register DECF Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a] Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4> Status Affected: Decrement f 0000 0000 Description: 0000 0000 ffff Words: 1 Cycles: 1 0111 DAW adjusts the eight-bit value in W resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. ffff Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). C Encoding: 01da Description: Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read register `f' Process Data Write to destination Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example 1: DAW Before Instruction W = C = DC = 0xA5 0 0 After Instruction W = C = DC = 0x05 1 0 Example: DECF Before Instruction CNT = Z = 0x01 0 After Instruction CNT = Z = 0x00 1 CNT, 1, 0 Example 2: Before Instruction W = C = DC = 0xCE 0 0 After Instruction W = C = DC = 0x34 1 0 DS39612B-page 294 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DECFSZ Decrement f, Skip if 0 DCFSNZ Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest; skip if result = 0 Operation: (f) - 1 dest; skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff Decrement f, Skip if Not 0 Encoding: 0100 The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Description: Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: 11da f [,d [,a] ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation DECFSZ GOTO CNT, 1, 1 LOOP Example: HERE CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) 2005 Microchip Technology Inc. Example: HERE ZERO NZERO Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC DCFSNZ : : TEMP, 1, 0 = ? = = = = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) DS39612B-page 295 PIC18F6525/6621/8525/8621 GOTO Unconditional Branch INCF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, No operation Read literal `k'<19:8>, Write to PC No operation No operation Example: No operation GOTO THERE After Instruction PC = Address (THERE) DS39612B-page 296 No operation Increment f Encoding: 0010 INCF f [,d [,a] 10da ffff ffff Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: INCF Before Instruction CNT = Z = C = DC = 0xFF 0 ? ? After Instruction CNT = Z = C = DC = 0x00 1 1 1 CNT, 1, 0 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest; skip if result = 0 Operation: (f) + 1 dest; skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: INCFSZ f [,d [,a] 11da ffff ffff Increment f, Skip if Not 0 Encoding: 0100 The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Description: Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: INFSNZ f [,d [,a] 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = INCFSZ : : Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) 2005 Microchip Technology Inc. CNT, 1, 0 Example: HERE ZERO NZERO Before Instruction PC = After Instruction REG = If REG PC = If REG = PC = INFSNZ REG, 1, 0 Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) DS39612B-page 297 PIC18F6525/6621/8525/8621 IORLW Inclusive OR Literal with W IORWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: IORLW k 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Inclusive OR W with f Encoding: 0001 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to W Example: IORLW Before Instruction W = 0x9A After Instruction W = 0xBF 0x35 ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: IORWF Before Instruction RESULT = W = After Instruction RESULT = W = DS39612B-page 298 00da f [,d [,a] Description: Q Cycle Activity: Decode IORWF RESULT, 0, 1 0x13 0x91 0x13 0x93 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 LFSR Load FSR MOVF Syntax: [ label ] Syntax: [ label ] Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal `k' is loaded into the file select register pointed to by `f'. Words: 2 Cycles: 2 Move f Operation: f dest Status Affected: N, Z Encoding: 0101 Q1 Q2 Q3 Q4 Read literal `k' MSB Process Data Write literal `k' MSB to FSRfH Decode Read literal `k' LSB Process Data Write literal `k' to FSRfL f [,d [,a] 00da ffff ffff Description: The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Decode MOVF Q Cycle Activity: Example: After Instruction FSR2H = FSR2L = LFSR 2, 0x3AB Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write W 0x03 0xAB Example: MOVF Before Instruction REG = W = After Instruction REG = W = 2005 Microchip Technology Inc. REG, 0, 0 0x22 0xFF 0x22 0x22 DS39612B-page 299 PIC18F6525/6621/8525/8621 MOVFF Move f to f MOVLB Syntax: [ label ] Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: (fs) fd k BSR Operation: Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) MOVFF fs,fd 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Move Literal to Low Nibble in BSR MOVLB k 0000 0001 kkkk kkkk Description: The 8-bit literal `k' is loaded into the Bank Select Register (BSR). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write literal `k' to BSR Example: MOVLB Before Instruction BSR register After Instruction BSR register 5 = 0x02 = 0x05 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' (src) Process Data No operation Decode No operation No operation Write register `f' (dest) No dummy read Example: MOVFF REG1, REG2 Before Instruction REG1 REG2 = = 0x33 0x11 After Instruction REG1 REG2 = = 0x33 0x33 DS39612B-page 300 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 MOVLW Move Literal to W MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 MOVLW k 1110 kkkk kkkk Description: The eight-bit literal `k' is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write to W Example: MOVLW 0x5A After Instruction W = 0x5A ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: MOVWF Before Instruction W = REG = After Instruction W = REG = 2005 Microchip Technology Inc. 111a f [,a] Description: Q Cycle Activity: Decode MOVWF REG, 0 0x4F 0xFF 0x4F 0x4F DS39612B-page 301 PIC18F6525/6621/8525/8621 MULLW Multiply Literal with W Syntax: [ label ] Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: 0000 Description: MULLW MULWF k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words: 1 Cycles: 1 Multiply W with f Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write registers PRODH: PRODL Example: MULLW 0xC4 Before Instruction W PRODH PRODL = = = 0xE2 ? ? After Instruction W PRODH PRODL = = = 0xE2 0xAD 0x08 DS39612B-page 302 001a f [,a] ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Decode MULWF Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W REG PRODH PRODL = = = = 0xC4 0xB5 ? ? After Instruction W REG PRODH PRODL = = = = 0xC4 0xB5 0x8A 0x94 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 NEGF Negate f Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: NEGF f [,a] 1 Cycles: 1 ffff Syntax: [ label ] Operands: None NOP Operation: No operation Status Affected: None 0000 1111 ffff 0000 xxxx Description: No operation. Words: 1 Cycles: 1 0000 xxxx 0000 xxxx Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: No Operation Encoding: 110a Location `f' is negated using 2's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. Words: NOP NEGF Before Instruction REG = After Instruction REG = None. REG, 1 0011 1010 [0x3A] 1100 0110 [0xC6] 2005 Microchip Technology Inc. DS39612B-page 303 PIC18F6525/6621/8525/8621 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: POP 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Encoding: Q2 Q3 Q4 Decode No operation POP TOS value No operation POP GOTO NEW 0000 0101 Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode PUSH PC + 2 onto return stack No operation No operation Example: Before Instruction TOS = Stack (1 level down)= DS39612B-page 304 0000 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Q Cycle Activity: Q1 After Instruction TOS PC 0000 Description: Q Cycle Activity: Example: PUSH = = 0031A2h 014332h 014332h NEW PUSH Before Instruction TOS PC = = 00345Ah 000124h After Instruction PC = TOS = Stack (1 level down)= 000126h 000126h 00345Ah 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 RCALL Relative Call Syntax: [ label ] RCALL Operands: -1024 n 1023 Operation: (PC) + 2 TOS; (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: n 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 RESET Reset Syntax: [ label ] Operands: None Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: All Encoding: 0000 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation 0000 1111 1111 Description: This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: Q Cycle Activity: RESET After Instruction Registers = Flags* = RESET Reset Value Reset Value Push PC to stack No operation Example: No operation HERE Before Instruction PC = After Instruction PC = TOS = RCALL Jump Address (HERE) Address (Jump) Address (HERE + 2) 2005 Microchip Technology Inc. DS39612B-page 305 PIC18F6525/6621/8525/8621 RETFIE Return from Interrupt RETLW Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC; 1 GIE/GIEH or PEIE/GIEL if s = 1 (WS) W; (STATUSS) STATUS; (BSRS) BSR; PCLATU, PCLATH are unchanged Operation: k W; (TOS) PC; PCLATU, PCLATH are unchanged Status Affected: None Status Affected: RETFIE [s] Encoding: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: 1100 kkkk kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). RETLW k Description: GIE/GIEH, PEIE/GIEL. Encoding: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Pop PC from stack, Write to W No operation No operation No operation No operation Example: Q1 Q2 Q3 Q4 Decode No operation No operation Pop PC from stack Set GIEH or GIEL No operation Return Literal to W No operation Example: RETFIE After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL DS39612B-page 306 No operation No operation 1 = = = = = TOS WS BSRS STATUSS 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W = W contains table offset value W now has table value W = offset Begin table End of table 0x07 value of kn 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 RETURN Return from Subroutine RLCF Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1 (WS) W; (STATUSS) STATUS; (BSRS) BSR; PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>; (f<7>) C; (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: RETURN [s] Rotate Left f through Carry Encoding: 0000 0001 001s 0011 Description: f [,d [,a] 01da ffff ffff The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). register f C Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: RLCF Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode No operation Process Data Pop PC from stack Decode Read register `f' Process Data Write to destination No operation No operation No operation No operation Example: RETURN After Interrupt PC = TOS 2005 Microchip Technology Inc. Example: RLCF REG, 0, 0 Before Instruction REG = C = 1110 0110 0 After Instruction REG = W = C = 1110 0110 1100 1100 1 DS39612B-page 307 PIC18F6525/6621/8525/8621 RLNCF Rotate Left f (No Carry) RRCF Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>; (f<7>) dest<0> Operation: Status Affected: N, Z (f<n>) dest<n - 1>; (f<0>) C; (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a] ffff ffff The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Rotate Right f through Carry Encoding: 0011 Description: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: Before Instruction REG = After Instruction REG = DS39612B-page 308 00da RLNCF Words: 1 Cycles: 1 0101 0111 ffff Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 1010 1011 ffff register f C Q Cycle Activity: f [,d [,a] The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). register f Words: RRCF Example: RRCF REG, 0, 0 Before Instruction REG = C = 1110 0110 0 After Instruction REG = W = C = 1110 0110 0111 0011 0 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 RRNCF Rotate Right f (No Carry) SETF Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f<n>) dest<n - 1>; (f<0>) dest<7> FFh f Operation: Status Affected: None Status Affected: f [,d [,a] Encoding: N, Z Encoding: 0100 Description: RRNCF 00da Set f ffff ffff The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example 1: RRNCF Before Instruction REG = After Instruction REG = Example 2: ffff Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' SETF Before Instruction REG After Instruction REG REG,1 = 0x5A = 0xFF REG, 1, 0 1101 0111 1110 1011 RRNCF Before Instruction W = REG = After Instruction W = REG = ffff The contents of the specified register are set to FFh. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Example: Q Cycle Activity: 100a Description: register f Words: 0110 f [,a] REG, 0, 0 ? 1101 0111 1110 1011 1101 0111 2005 Microchip Technology Inc. DS39612B-page 309 PIC18F6525/6621/8525/8621 SLEEP Enter Sleep Mode SUBFWB Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: 00h WDT; 0 WDT postscaler; 1 TO; 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z Status Affected: SLEEP TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep Example: Subtract f from W with Borrow 0101 After Instruction 1 TO = 0 PD = If WDT causes wake-up, this bit is cleared. ffff ffff Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = DS39612B-page 310 01da f [,d [,a] Description: SLEEP Before Instruction TO = ? ? PD = SUBFWB SUBFWB REG, 1, 0 3 2 1 FF 2 0 0 1 ; result is negative SUBFWB REG, 0, 0 2 5 1 2 3 1 0 0 ; result is positive SUBFWB REG, 1, 0 1 2 0 0 2 1 1 0 ; result is zero 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z SUBLW k Operands: 0 k 255 Operation: k - (W) W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk SUBWF f [,d [,a] Description: W is subtracted from the eight-bit literal `k'. The result is placed in W. Encoding: Words: 1 Description: Cycles: 1 Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 0101 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: SUBLW 1 ? 1 1 0 0 SUBLW Before Instruction W = C = 2 ? After Instruction W = C = Z = N = 0 1 1 0 Example 3: 0x02 SUBLW 11da ffff ffff Q Cycle Activity: ; result is positive 0x02 ; result is zero 0x02 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination SUBWF REG, 1, 0 Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction W = C = 3 ? After Instruction W = C = Z = N = FF ; (2's complement) 0 ; result is negative 0 1 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = 2005 Microchip Technology Inc. 3 2 ? 1 2 1 0 0 SUBWF ; result is positive REG, 0, 0 2 2 ? 2 0 1 1 0 SUBWF ; result is zero REG, 1, 0 1 2 ? FFh ;(2's complement) 2 0 ; result is negative 0 1 DS39612B-page 311 PIC18F6525/6621/8525/8621 SUBWFB Subtract W from f with Borrow SWAPF Syntax: [ label ] Syntax: [ label ] 0 f 255 d [0,1] a [0,1] SUBWFB f [,d [,a] Swap f SWAPF f [,d [,a] Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) - (W) - (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>; (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: 10da ffff ffff Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example 1: SUBWFB Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: 0011 10da ffff ffff Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 Example: 0x19 0x0D 1 (0001 1001) (0000 1101) 0x0C 0x0D 1 0 0 (0000 1011) (0000 1101) SWAPF Before Instruction REG = After Instruction REG = REG, 1, 0 0x53 0x35 ; result is positive SUBWFB REG, 0, 0 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: 0x1B 0x1A 0 (0001 1011) (0001 1010) 0x1B 0x00 1 1 0 (0001 1011) SUBWFB Before Instruction REG = W = C = After Instruction REG = W C Z N Encoding: = = = = DS39612B-page 312 ; result is zero REG, 1, 0 0x03 0x0E 1 (0000 0011) (0000 1101) 0xF5 (1111 0100) ; [2's comp] (0000 1101) 0x0E 0 0 1 ; result is negative 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TBLRD Table Read Syntax: [ label ] Operands: None TBLRD ( *; *+; *-; +*) Operation: if TBLRD* (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change if TBLRD*+ (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD*(Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR if TBLRD+* (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: 1 Cycles: 2 TBLRD Table Read (Continued) Example 1: TBLRD *+ ; Before Instruction TABLAT TBLPTR MEMORY(0x00A356) After Instruction TABLAT TBLPTR Example 2: TBLRD = = = 0x55 0x00A356 0x34 = = 0x34 0x00A357 +* ; Before Instruction TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358) After Instruction TABLAT TBLPTR = = = = 0xAA 0x01A357 0x12 0x34 = = 0x34 0x01A358 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) 2005 Microchip Technology Inc. DS39612B-page 313 PIC18F6525/6621/8525/8621 TBLWT Table Write TBLWT Syntax: [ label ] Words: Operands: None Cycles: 2 Operation: if TBLWT* (TABLAT) Holding Register; TBLPTR - No Change if TBLWT*+ (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*(TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR if TBLWT+* (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Q Cycle Activity: TBLWT ( *; *+; *-; +*) Description: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 5.0 "Flash Program Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSB of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment DS39612B-page 314 1 Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read TABLAT) No operation No operation (Write to Holding Register ) Example 1: Status Affected: None Encoding: Table Write (Continued) TBLWT *+; Before Instruction TABLAT = 0x55 TBLPTR = 0x00A356 HOLDING REGISTER (0x00A356) = 0xFF After Instructions (table write completion) TABLAT = 0x55 TBLPTR = 0x00A357 HOLDING REGISTER (0x00A356) = 0x55 Example 2: TBLWT +*; Before Instruction TABLAT = 0x34 TBLPTR = 0x01389A HOLDING REGISTER (0x01389A) = 0xFF HOLDING REGISTER (0x01389B) = 0xFF After Instruction (table write completion) TABLAT = 0x34 TBLPTR = 0x01389B HOLDING REGISTER (0x01389A) = 0xFF HOLDING REGISTER (0x01389B) = 0x34 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 a [0,1] TSTFSZ f [,a] Operation: skip if f = 0 Status Affected: None Encoding: 0110 Description: ffff ffff If `f' = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Encoding: 011a Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation XORLW k 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction W = 0x1A If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC = After Instruction If CNT = PC = If CNT PC = TSTFSZ : : CNT, 1 Address (HERE) 0x00, Address (ZERO) 0x00, Address (NZERO) 2005 Microchip Technology Inc. DS39612B-page 315 PIC18F6525/6621/8525/8621 XORWF Exclusive OR W with f Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 XORWF 10da f [,d [,a] ffff ffff Description: Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: XORWF Before Instruction REG = W = After Instruction REG = W = DS39612B-page 316 REG, 1, 0 0xAF 0xB5 0x1A 0xB5 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 26.0 DEVELOPMENT SUPPORT The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) Evaluation and Programming Tools - PICDEM MSC - microID(R) Developer Kits - CAN - PowerSmart(R) Developer Kits - Analog 26.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - mixed assembly and C - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power. 26.2 MPASM Assembler The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects * User defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process 2005 Microchip Technology Inc. DS39612B-page 317 PIC18F6525/6621/8525/8621 26.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.5 MPLAB C30 C Compiler The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE. DS39612B-page 318 26.6 MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 26.7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 26.8 MPLAB SIM30 Software Simulator The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 2005 Microchip Technology Inc. 26.11 MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices. 26.12 PRO MATE II Universal Device Programmer The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. 26.13 MPLAB PM3 Device Programmer The MPLAB PM3 is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In StandAlone mode, the MPLAB PM3 device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. MPLAB PM3 connects to the host PC via an RS232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. DS39612B-page 319 PIC18F6525/6621/8525/8621 26.14 PICSTART Plus Development Programmer 26.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. The PICDEM 2 Plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers. 26.15 PICDEM 1 PICmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs. 26.16 PICDEM.net Internet/Ethernet Demonstration Board The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham DS39612B-page 320 26.18 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs. 26.19 PICDEM 4 8/14/18-Pin Demonstration Board The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2 x 16 liquid crystal display, PCB footprints for H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User's Guide. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 26.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. 26.21 PICDEM 18R PIC18C601/801 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801. 26.22 PICDEM LIN PIC16C43X Demonstration Board The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication. 26.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products. 26.25 Evaluation and Programming Tools In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and rfLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits. 26.23 PICkitTM 1 Flash Starter Kit A complete "development system in a box", the PICkitTM Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC(R) microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User's Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB(R) IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin Flash PIC(R) Microcontrollers" Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2005 Microchip Technology Inc. DS39612B-page 321 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 322 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to VSS ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2005 Microchip Technology Inc. DS39612B-page 323 PIC18F6525/6621/8525/8621 FIGURE 27-1: PIC18F6X2X/8X2X VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18F6525/6621/8525/8621 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz (Extended) 40 MHz (Industrial) Frequency FIGURE 27-2: PIC18LF6X2X/8X2X VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF6525/6621/8525/8621 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX 4 MHz Frequency For PIC18F6525/6621 and PIC18F8525/8621 in Microcontroller mode: FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz, if VDDAPPMIN 4.2V; FMAX = 40 MHz, if VDDAPPMIN > 4.2V. For PIC18F8525/8621 in modes other than Microcontroller mode: FMAX = (9.55 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz, if VDDAPPMIN 4.2V; FMAX = 25 MHz, if VDDAPPMIN > 4.2V. Note: DS39612B-page 324 VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 27.1 DC Characteristics: Supply Voltage PIC18F6X2X/8X2X (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X2X/8X2X (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D001 Symbol VDD Characteristic Min Typ Max Units PIC18LF6X2X/8X2X 2.0 -- 5.5 V PIC18F6X2X/8X2X 4.2 -- 5.5 V Supply Voltage D001A AVDD Analog Supply Voltage -0.3 -- +0.3 V D002 VDR RAM Data Retention Voltage(1) 1.5 -- -- V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal -- -- 0.7 V D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 -- -- D005 VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 1.96 -- 2.18 BORV1:BORV0 = 10 2.64 -- 2.92 V BORV1:BORV0 = 01 4.11 -- 4.55 V BORV1:BORV0 = 00 4.41 -- 4.87 V Legend: Note 1: Conditions See Section 3.1 "Power-on Reset (POR)" for details V/ms See Section 3.1 "Power-on Reset (POR)" for details V Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode or during a device Reset without losing RAM data. 2005 Microchip Technology Inc. DS39612B-page 325 PIC18F6525/6621/8525/8621 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6X2X/8X2X (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X2X/8X2X (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Power-Down Current (IPD)(1) PIC18LF6X2X/8X2X PIC18LF6X2X/8X2X All devices Legend: Note 1: 2: 3: 4: 0.2 1 A -40C 0.2 1 A +25C 5.0 10 A +85C 0.4 1 A -40C 0.4 1 A +25C 3.0 18 A +85C 0.7 2 A -40C 0.7 2 A +25C 15 32 A +85C VDD = 2.0V, (Sleep mode) VDD = 3.0V, (Sleep mode) VDD = 5.0V, (Sleep mode) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. The band gap reference is a shared resource used by both BOR and LVD modules. Enabling both modules will consume less than the specified sum current of the modules. DS39612B-page 326 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6X2X/8X2X (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) (Continued) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X2X/8X2X (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) D010 PIC18LF6X2X/8X2X PIC18LF6X2X/8X2X All devices PIC18LF6X2X/8X2X PIC18LF6X2X/8X2X All devices Legend: Note 1: 2: 3: 4: 300 500 A -40C 300 500 A +25C 850 1000 A +85C 500 900 A -40C 500 900 A +25C 1 1.5 mA +85C 1 2 mA -40C 1 2 mA +25C 1.3 3 mA +85C 1 2 mA -40C 1 2 mA +25C 1.5 2.5 mA +85C 1.5 2 mA -40C 1.5 2 mA +25C 2 2.5 mA +85C 3 5 mA -40C 3 5 mA +25C 4 6 mA +85C VDD = 2.0V VDD = 3.0V FOSC = 1 MHZ, EC oscillator VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz, EC oscillator VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. The band gap reference is a shared resource used by both BOR and LVD modules. Enabling both modules will consume less than the specified sum current of the modules. 2005 Microchip Technology Inc. DS39612B-page 327 PIC18F6525/6621/8525/8621 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6X2X/8X2X (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) (Continued) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X2X/8X2X (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 13 27 mA -40C 15 27 mA +25C 19 29 mA +85C 17 31 mA -40C 21 31 mA +25C 23 34 mA +85C 20 34 mA -40C 24 34 mA +25C 29 44 mA +85C 28 46 mA -40C 33 46 mA +25C 40 51 mA +85C 27 45 A -10C 30 50 A +25C 32 54 A +70C 33 55 A -10C 36 60 A +25C 39 65 A +70C 75 125 A -10C Supply Current (IDD)(2,3) PIC18F6X2X/8X2X PIC18F6X2X/8X2X PIC18F6X2X/8X2X PIC18F6X2X/8X2X D014 PIC18LF6X2X/8X2X PIC18LF6X2X/8X2X All devices Legend: Note 1: 2: 3: 4: 90 150 A +25C 113 188 A +70C VDD = 4.2V FOSC = 25 MHZ, EC oscillator VDD = 5.0V VDD = 4.2V FOSC = 40 MHZ, EC oscillator VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 32 kHz, Timer1 as clock VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. The band gap reference is a shared resource used by both BOR and LVD modules. Enabling both modules will consume less than the specified sum current of the modules. DS39612B-page 328 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6X2X/8X2X (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) (Continued) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X2X/8X2X (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 (IWDT) Watchdog Timer D022A (IBOR) Brown-out Reset(4) D022B (ILVD) (4) Low-Voltage Detect D025 (IOSCB) Timer1 Oscillator A/D Converter D026 (IAD) Legend: Note 1: 2: 3: 4: <1 2.0 A -40C <1 2 A +25C 5 20 A +85C 3 10 A -40C 3 20 A +25C 10 35 A +85C 12 25 A -40C 15 35 A +25C 20 50 A +85C 55 115 A -40C to +85C VDD = 3.0V 105 175 A -40C to +85C VDD = 5.0V VDD = 2.0V VDD = 3.0V VDD = 5.0V 45 125 A -40C to +85C VDD = 2.0V 45 150 A -40C to +85C VDD = 3.0V 45 225 A -40C to +85C VDD = 5.0V 20 27 A -10C 20 30 A +25C 25 35 A +70C 22 60 A -10C 22 65 A +25C 25 75 A +70C 30 75 A -10C 30 85 A +25C 35 100 A +70C <1 2 A +25C VDD = 2.0V <1 2 A +25C VDD = 3.0V <1 2 A +25C VDD = 5.0V VDD = 2.0V 32 kHz on Timer1 VDD = 3.0V 32 kHz on Timer1 VDD = 5.0V 32 kHz on Timer1 A/D on, not converting Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. The band gap reference is a shared resource used by both BOR and LVD modules. Enabling both modules will consume less than the specified sum current of the modules. 2005 Microchip Technology Inc. DS39612B-page 329 PIC18F6525/6621/8525/8621 27.3 DC Characteristics: PIC18F6X2X/8X2X (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions with TTL buffer VSS 0.15 VDD V VDD < 4.5V -- 0.8 V 4.5V VDD 5.5V with Schmitt Trigger buffer RC3 and RC4 VSS VSS 0.2 VDD 0.3 VDD V V VSS 0.2 VDD V Input Low Voltage I/O ports: D030 D030A D031 D032 MCLR D033 OSC1 VSS 0.3 VDD V HS, HS+PLL modes D033A OSC1 VSS 0.2 VDD V RC, EC modes D033B OSC1 VSS 0.3 V XT, LP modes D034 T1OSI VSS 0.3 V 0.25 VDD + 0.8V VDD V VDD < 4.5V 2.0 VDD V 4.5V VDD 5.5V 0.8 VDD 0.7 VDD VDD VDD V V MCLR, OSC1 (EC mode) 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HS+PLL modes D043A OSC1 0.8 VDD VDD V EC mode D043B OSC1 0.9 VDD VDD V RC mode(1) D043C OSC1 1.6 VDD V XT, LP modes 1.6 VDD V I/O ports -- 1 A D061 MCLR -- 5 A VSS VPIN VDD D063 OSC1 -- 5 A VSS VPIN VDD 50 400 A VDD = 5V, VPIN = VSS VIH Input High Voltage I/O ports: D040 with TTL buffer D040A D041 with Schmitt Trigger buffer RC3 and RC4 D042 D044 T13CKI IIL D060 D070 Note 1: 2: 3: 4: Input Leakage Current(2,3) IPU Weak Pull-up Current IPURB PORTB weak pull-up current VSS VPIN VDD, Pin at high-impedance In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. DS39612B-page 330 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 27.3 DC Characteristics: PIC18F6X2X/8X2X (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic D080A OSC2/CLKO (RC mode) D083A VOH D090 D090A OSC2/CLKO (RC mode) D092A D150 VOD Units Conditions -- 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C -- 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C -- 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C -- 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C VDD - 0.7 -- V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C VDD - 0.7 -- V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C VDD - 0.7 -- V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C VDD - 0.7 -- V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C -- 8.5 V RA4 pin Output High Voltage(3) I/O ports D092 Max Output Low Voltage I/O ports D083 Min Open-Drain High Voltage Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin -- 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (in RC mode) -- 50 pF To meet the AC Timing Specifications D102 CB SCL, SDA -- 400 pF In I2CTM mode Note 1: 2: 3: 4: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. 2005 Microchip Technology Inc. DS39612B-page 331 PIC18F6525/6621/8525/8621 TABLE 27-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage -- 5.0 10 mV D301 VICM Input Common Mode Voltage 0 -- VDD - 1.5 V D302 CMRR Common Mode Rejection Ratio 55 -- -- dB 300 300A TRESP Response Time -- 150 400 600 ns ns 301 TMC2OV Comparator Mode Change to Output Valid -- -- 10 s Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD. TABLE 27-2: (1) PIC18F6X2X/8X2X PIC18LF6X2X/8X2X VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated) Spec No. Sym Characteristics Min Typ Max Units VDD/24 -- VDD/32 LSb LSb D310 VRES Resolution D311 VRAA Absolute Accuracy -- -- 1/2 D312 VRUR Unit Resistor Value (R) -- 2k -- 310 TSET Time(1) -- -- 10 s Note 1: Settling Comments Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. DS39612B-page 332 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-3: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 27-3: LOW-VOLTAGE DETECT CHARACTERISTICS LOW-VOLTAGE DETECT CHARACTERISTICS Param Symbol No. D420 D423 VLVD VBG Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Min LVD Voltage on VDD LVV = 0000 transition high-to-low LVV = 0001 -- 1.96 LVV = 0010 2.16 LVV = 0011 2.35 LVV = 0100 LVV = 0101 Max Units -- -- V 2.06 2.16 V 2.27 2.38 V 2.47 2.59 V 2.46 2.58 2.71 V 2.64 2.78 2.92 V LVV = 0110 2.75 2.89 3.03 V LVV = 0111 2.95 3.10 3.26 V LVV = 1000 3.24 3.41 3.58 V LVV = 1001 3.43 3.61 3.79 V LVV = 1010 3.53 3.72 3.91 V LVV = 1011 3.72 3.92 4.12 V LVV = 1100 3.92 4.13 4.33 V LVV = 1101 4.11 4.33 4.55 V LVV = 1110 4.41 4.64 4.87 V -- 1.22 -- V Band Gap Reference Voltage Value Typ Conditions Production tested at TAMB = 25C. Specifications over temp. limits ensured by characterization. 2005 Microchip Technology Inc. DS39612B-page 333 PIC18F6525/6621/8525/8621 TABLE 27-4: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended DC Characteristics Param No. Sym Characteristic Min Typ Max Units V Conditions Internal Program Memory Programming Specifications VPP Voltage on MCLR/VPP pin 9.00 -- 13.25 D112 IPP Current into MCLR/VPP pin -- -- 300 A D113 IDDP Supply Current during Programming -- -- 1.0 mA E/W -40C to +85C E/W -40C to +125C D110 (Note 2) Data EEPROM Memory D120 ED Byte Endurance 100K 10K 1M 100K -- -- D121 VDRW VDD for Read/Write VMIN -- 5.5 D122 TDEW Erase/Write Cycle Time -- 4 -- D123 TRETD Characteristic Retention 40 -- -- Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write Cycles before Refresh(1) 1M 100K 10M 1M -- -- E/W -40C to +85C E/W -40C to +125C E/W -40C to +85C E/W -40C to +125C V Using EECON to read/write VMIN = Minimum operating voltage ms Program Flash Memory D130 EP Cell Endurance 10K 1K 100K 10K -- -- D131 VPR VDD for Read VMIN -- 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 -- 5.5 V Using ICSPTM port D132A VIW VDD for Externally Timed Erase or Write 4.5 -- 5.5 V Using ICSP port D132B VPEW VDD for Self-Timed Write and Row Erase VMIN -- 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time -- 4 -- ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time (externally timed) 1 -- -- ms VDD > 4.5V D133A TIW D134 Self-Timed Write Cycle Time TRETD Characteristic Retention -- 2 -- 40 -- -- ms Year Provided no other specifications are violated Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section 7.8 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 2: Required only if Low-Voltage Programming is disabled. DS39612B-page 334 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 27.4 27.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low 2 I C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 2005 Microchip Technology Inc. 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance High Low High Low SU Setup STO Stop condition DS39612B-page 335 PIC18F6525/6621/8525/8621 27.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-5 apply to all timing specifications, unless otherwise noted. Figure 27-4 specifies the load conditions for the timing specifications. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS FIGURE 27-4: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 27.1 and Section 27.3. LF parts operate for industrial temperatures only. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS DS39612B-page 336 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 27-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 25 MHz EC, ECIO(2) (-40C to +85C) DC 40 MHz EC, ECIO DC 25 MHz EC, ECIO (+85C to +125C) DC 4 MHz RC oscillator Oscillator Frequency(1) 1 TOSC External CLKI Period(1) Oscillator Period(1) Conditions 0.1 4 MHz XT oscillator 4 25 MHz HS oscillator 4 10 MHz HS + PLL oscillator 4 6.25 MHz HS + PLL oscillator(2) 5 33 kHz 25 -- ns EC, ECIO LP Oscillator mode 40 -- ns EC, ECIO(2) 40 -- ns EC, ECIO (+85C to +125C) 250 -- ns RC oscillator 250 10,000 ns XT oscillator 40 100 160 250 250 250 ns ns ns HS oscillator HS + PLL oscillator HS + PLL oscillator(2) 30 200 s LP oscillator 2 TCY Instruction Cycle Time(1) 100 -- ns TCY = 4/FOSC 3 TosL, TosH External Clock in (OSC1) High or Low Time 30 -- ns XT oscillator 2.5 -- s LP oscillator 10 -- ns HS oscillator TosR, TosF External Clock in (OSC1) Rise or Fall Time -- 20 ns XT oscillator 4 Note 1: 2: -- 50 ns LP oscillator -- 7.5 ns HS oscillator Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. PIC18F6525/6621/8525/8621 devices using external memory interface. 2005 Microchip Technology Inc. DS39612B-page 337 PIC18F6525/6621/8525/8621 TABLE 27-7: Param. No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Sym Characteristic Min Typ Max Units FOSC FSYS Oscillator Frequency Range On-Chip VCO System Frequency 4 16 -- -- 10 40 trc PLL Start-up Time (Lock Time) -- -- 2 ms CLK CLKO Stability (Jitter) -2 -- +2 % Conditions MHz HS mode MHz HS mode Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 27-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 12 19 18 16 I/O pin (input) 15 17 I/O pin (output) 20, 21 Refer to Figure 27-4 for load conditions. Note: TABLE 27-8: Param No. New Value Old Value CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 to CLKO -- 75 200 ns (Note 1) 11 TosH2ckH OSC1 to CLKO -- 75 200 ns (Note 1) 12 TckR CLKO Rise Time -- 35 100 ns (Note 1) 13 TckF CLKO Fall Time -- 35 100 ns (Note 1) -- -- 0.5 TCY + 20 ns (Note 1) 0.25 TCY + 25 -- -- ns (Note 1) (Note 1) 14 TckL2ioV CLKO to Port Out Valid 15 TioV2ckH Port In Valid before CLKO 16 TckH2ioI Port In Hold after CLKO 0 -- -- ns 17 TosH2ioV OSC1 (Q1 cycle) to Port Out Valid -- 50 150 ns 18 TosH2ioI OSC1 (Q2 cycle) to Port PIC18F6X2X/8X2X Input Invalid (I/O in hold time) PIC18LF6X2X/8X2X 18A 100 -- -- ns 200 -- -- ns 19 TioV2osH Port Input Valid to OSC1 (I/O in setup time) 0 -- -- ns 20 TioR Port Output Rise Time PIC18F6X2X/8X2X -- 10 25 ns PIC18LF6X2X/8X2X -- -- 60 ns TioF Port Output Fall Time PIC18F6X2X/8X2X -- 10 25 ns PIC18LF6X2X/8X2X -- -- 60 ns ns 20A 21 21A 22 TINP INT pin High or Low Time TCY -- -- 23 TRBP RB7:RB4 Change INT High or Low Time TCY -- -- 24 TRCP RC7:RC4 Change INT High or Low Time 20 Note 1: ns ns These parameters are asynchronous events not related to any internal clock edges. Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39612B-page 338 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-7: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address Address AD<15:0> Data from External 150 151 Address 163 160 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 5.5V, -40C < TA < +125C unless otherwise stated. TABLE 27-9: Param. No PROGRAM MEMORY READ TIMING REQUIREMENTS Symbol Characteristics Min Typ Max Units 0.25 TCY - 10 -- -- ns 150 TadV2alL Address Out Valid to ALE (address setup time) 151 TalL2adl ALE to Address Out Invalid (address hold time) 5 -- -- ns 155 TalL2oeL ALE to OE 10 0.125 TCY -- ns 160 TadZ2oeL AD high-Z to OE (bus release to OE) 0 -- -- ns 161 ToeH2adD OE to AD Driven 0.125 TCY - 5 -- -- ns 162 TadV2oeH LS Data Valid before OE (data setup time) 20 -- -- ns 163 ToeH2adl OE to Data In Invalid (data hold time) 0 -- -- ns 164 TalH2alL ALE Pulse Width -- 0.25 TCY -- ns 165 ToeL2oeH OE Pulse Width 0.5 TCY - 5 0.5 TCY -- ns 166 TalH2alH ALE to ALE (cycle time) 40 ns TCY -- ns 167 Tacc Address Valid to Data Valid 0.75 TCY - 25 -- -- ns -- 0.5 TCY - 25 ns 0.625 TCY - 10 -- 0.625 TCY + 10 ns -- -- 10 ns 0.25 TCY - 20 -- -- ns 168 Toe OE to Data Valid 169 TalL2oeH ALE to OE 171 TalH2csL Chip Enable Active to ALE 171A TubL2oeH AD Valid to Chip Enable Active 2005 Microchip Technology Inc. DS39612B-page 339 PIC18F6525/6621/8525/8621 FIGURE 27-8: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address 166 Data Address AD<15:0> Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB Operating Conditions: 2.0V < VCC < 5.5V, -40C < TA < +125C unless otherwise stated. TABLE 27-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.25 TCY - 10 -- -- ns 151 TalL2adl ALE to Address Out Invalid (address hold time) 5 -- -- ns 153 TwrH2adl WRn to Data Out Invalid (data hold time) 5 -- -- ns 154 TwrL WRn Pulse Width 0.5 TCY - 5 0.5 TCY -- ns 156 TadV2wrH Data Valid before WRn (data setup time) 0.5 TCY - 10 -- -- ns 157 TbsV2wrL Byte Select Valid before WRn (byte select setup time) 0.25 TCY -- -- ns 157A TwrH2bsI WRn to Byte Select Invalid (byte select hold time) 166 TalH2alH ALE to ALE (cycle time) 171 TalH2csL Chip Enable Active to ALE 171A TubL2oeH AD Valid to Chip Enable Active DS39612B-page 340 0.125 TCY - 5 -- -- ns -- TCY -- ns -- -- 10 ns 0.25 TCY - 20 -- -- ns 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 27-4 for load conditions. FIGURE 27-10: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No. Symbol Characteristic Min Typ Max Units 30 TmcL MCLR Pulse Width (low) 2 -- -- s 31 TWDT Watchdog Timer Time-out Period (no postscaler) 7 18 33 ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC -- 1024 TOSC -- 33 TPWRT Power-up Timer Period 28 72 132 ms 34 TIOZ I/O High-impedance from MCLR Low or Watchdog Timer Reset -- 2 -- s 35 TBOR Brown-out Reset Pulse Width 200 -- -- s 36 TIRVST Time for Internal Reference Voltage to become stable -- 20 50 s 37 TLVD Low-Voltage Detect Pulse Width 200 -- -- s 2005 Microchip Technology Inc. Conditions TOSC = OSC1 period VDD BVDD (see D005) VDD VLVD DS39612B-page 341 PIC18F6525/6621/8525/8621 FIGURE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 27-4 for load conditions. TABLE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param. Symbol No. 40 Tt0H Characteristic T0CKI High Pulse Width No prescaler With prescaler 41 Tt0L T0CKI Low Pulse Width No prescaler With prescaler 42 Tt0P T0CKI Period No prescaler With prescaler 45 Tt1H T13CKI High Time Synchronous, no prescaler Synchronous, PIC18F6X2X/8X2X with prescaler PIC18LF6X2X/8X2X Asynchronous PIC18F6X2X/8X2X PIC18LF6X2X/8X2X 46 Tt1L T13CKI Low Time Synchronous, no prescaler Synchronous, PIC18F6X2X/8X2X with prescaler PIC18LF6X2X/8X2X Asynchronous PIC18F6X2X/8X2X PIC18LF6X2X/8X2X 47 48 Legend: Min Max Units 0.5 TCY + 20 -- ns 10 -- ns 0.5 TCY + 20 -- ns 10 -- ns TCY + 10 -- ns Greater of: 20 ns or TCY + 40 N -- ns 0.5 TCY + 20 -- ns 10 -- ns 25 -- ns 30 -- ns 50 -- ns 0.5 TCY + 5 -- ns 10 -- ns 25 -- ns 30 -- ns TBD TBD ns Greater of: 20 ns or TCY + 40 N -- ns Tt1P T13CKI Synchronous Input Period Asynchronous 60 -- ns Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz 2 TOSC 7 TOSC -- Tcke2tmrI Delay from External T13CKI Clock Edge to Timer Increment Conditions N = prescale value (1, 2, 4,..., 256) N = prescale value (1, 2, 4, 8) TBD = To Be Determined DS39612B-page 342 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-12: CAPTURE/COMPARE/PWM TIMINGS (ALL ECCP/CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 27-4 for load conditions. TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL ECCP/CCP MODULES) Param. Symbol No. 50 51 TccL TccH Characteristic CCPx Input Low Time CCPx Input High Time No prescaler With prescaler PIC18F6X2X/8X2X PIC18LF6X2X/8X2X Max Units 0.5 TCY + 20 -- ns 10 -- ns 20 -- ns 0.5 TCY + 20 -- ns PIC18F6X2X/8X2X 10 -- ns PIC18LF6X2X/8X2X 20 -- ns 3 TCY + 40 N -- ns ns No prescaler With prescaler Min 52 TccP CCPx Input Period 53 TccR CCPx Output Rise Time PIC18F6X2X/8X2X -- 25 PIC18LF6X2X/8X2X -- 45 ns 54 TccF CCPx Output Fall Time PIC18F6X2X/8X2X -- 25 ns PIC18LF6X2X/8X2X -- 45 ns 2005 Microchip Technology Inc. Conditions N = prescale value (1,4 or 16) DS39612B-page 343 PIC18F6525/6621/8525/8621 FIGURE 27-13: PARALLEL SLAVE PORT TIMING (PIC18F8525/8621) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 27-4 for load conditions. TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8525/8621) Param. No. 62 63 64 Symbol Characteristic TdtV2wrH Data In Valid before WR or CS (setup time) TwrH2dtI WR or CS to Data-in PIC18F6X2X/8X2X Invalid (hold time) PIC18LF6X2X/8X2X TrdL2dtV RD and CS to Data-out Valid Min Max Units Conditions 20 25 -- -- ns ns Extended Temp. range 20 -- ns 35 -- ns -- -- 80 90 ns ns ns 65 TrdH2dtI RD or CS to Data-out Invalid 10 30 66 TibfINH Inhibit of the IBF Flag bit being cleared from WR or CS -- 3 TCY DS39612B-page 344 Extended Temp. range 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-14: EXAMPLE SPITM MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-4 for load conditions. TABLE 27-15: EXAMPLE SPITM MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No. Symbol Characteristic Min Max Units TCY -- ns 70 TssL2scH, TssL2scL SS to SCK or SCK Input 71 TscH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns 100 -- ns 1.5 TCY + 40 -- ns 100 -- ns PIC18F6X2X/8X2X -- 25 ns PIC18LF6X2X/8X2X -- 45 ns -- 25 ns PIC18F6X2X/8X2X -- 25 ns PIC18LF6X2X/8X2X -- 45 ns 25 ns 71A 72 TscL 72A 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 73A T B 2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 75 TdoR SDO Data Output Rise Time 76 TdoF SDO Data Output Fall Time 78 TscR SCK Output Rise Time (Master mode) 79 TscF SCK Output Fall Time (Master mode) -- 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge PIC18F6X2X/8X2X -- 50 ns PIC18LF6X2X/8X2X -- 100 ns Note 1: 2: Conditions (Note 1) (Note 1) (Note 2) Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. 2005 Microchip Technology Inc. DS39612B-page 345 PIC18F6525/6621/8525/8621 FIGURE 27-15: EXAMPLE SPITM MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI bit 6 - - - -1 MSb In LSb In 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-16: EXAMPLE SPITM MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Characteristic Min Max Units SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns TscL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 -- ns 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 73A T B 2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 75 TdoR SDO Data Output Rise Time PIC18F6X2X/8X2X 71 TscH 71A 72 72A Single Byte 40 -- ns 100 -- ns 1.5 TCY + 40 -- ns 100 -- ns -- 25 ns 45 ns PIC18LF6X2X/8X2X 76 TdoF SDO Data Output Fall Time 78 TscR SCK Output Rise Time (Master mode) 79 TscF SCK Output Fall Time (Master mode) -- 25 ns 80 TscH2doV, TscL2doV SDO Data Output Valid after PIC18F6X2X/8X2X SCK Edge PIC18LF6X2X/8X2X -- 50 ns 100 ns 81 TdoV2scH, SDO Data Output Setup to SCK Edge TdoV2scL -- ns Note 1: 2: PIC18F6X2X/8X2X -- 25 ns -- 25 ns 45 ns PIC18LF6X2X/8X2X TCY Conditions (Note 1) (Note 1) (Note 2) Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. DS39612B-page 346 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-16: EXAMPLE SPITM SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-4 for load conditions. TABLE 27-17: EXAMPLE SPITM MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param. No. Symbol Characteristic 70 TssL2scH, SS to SCK or SCK Input TssL2scL 71 TscH SCK Input High Time (Slave mode) TscL SCK Input Low Time (Slave mode) 71A 72 72A Min Max TCY -- ns 1.25 TCY + 30 -- ns Single Byte 40 -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns 100 -- ns 1.5 TCY + 40 -- ns 100 -- ns -- 25 ns Continuous Units Conditions 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge TdiV2scL 73A T B 2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 75 TdoR SDO Data Output Rise Time 45 ns 76 TdoF SDO Data Output Fall Time -- 25 ns 77 TssH2doZ SS to SDO Output High-impedance 10 50 ns 78 TscR SCK Output Rise Time (Master mode) PIC18F6X2X/8X2X -- 25 ns 45 ns -- 25 ns -- 50 ns 100 ns -- ns PIC18F6X2X/8X2X PIC18F6X2X/8X2X PIC18F6X2X/8X2X 79 TscF 80 TscH2doV, SDO Data Output Valid after SCK TscL2doV Edge 83 SCK Output Fall Time (Master mode) TscH2ssH, SS after SCK Edge TscL2ssH PIC18F6X2X/8X2X PIC18F6X2X/8X2X 1.5 TCY + 40 (Note 1) (Note 1) (Note 2) Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. 2005 Microchip Technology Inc. DS39612B-page 347 PIC18F6525/6621/8525/8621 FIGURE 27-17: EXAMPLE SPITM SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-18: EXAMPLE SPITM SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic 70 TssL2scH, SS to SCK or SCK Input TssL2scL 71 TscH 71A 72 TscL 72A Min Max Units Conditions TCY -- ns SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns (Note 1) (Note 2) 73A TB2B 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge TscL2diL Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 75 TdoR SDO Data Output Rise Time 76 TdoF SDO Data Output Fall Time 77 TssH2doZ SS to SDO Output High-impedance 78 TscR PIC18F6X2X/8X2X -- ns 100 -- ns -- 25 ns 45 ns -- 25 ns 10 50 ns PIC18LF6X2X/8X2X SCK Output Rise Time (Master mode) PIC18F6X2X/8X2X -- 25 ns PIC18LF6X2X/8X2X -- 45 ns -- 25 ns -- 50 ns -- 100 ns -- 50 ns -- 100 ns 1.5 TCY + 40 -- ns 79 TscF 80 TscH2doV, SDO Data Output Valid after SCK PIC18F6X2X/8X2X TscL2doV Edge PIC18LF6X2X/8X2X SCK Output Fall Time (Master mode) 82 TssL2doV 83 TscH2ssH, SS after SCK Edge TscL2ssH SDO Data Output Valid after SS Edge PIC18F6X2X/8X2X PIC18LF6X2X/8X2X (Note 1) Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39612B-page 348 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 I2CTM BUS START/STOP BITS TIMING FIGURE 27-18: SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-19: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. Characteristic 90 TSU:STA Start Condition 91 THD:STA 92 TSU:STO 93 THD:STO Stop Condition Max Units Conditions 4700 -- ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Setup Time 400 kHz mode 600 -- Start Condition 100 kHz mode 4000 -- Hold Time 400 kHz mode 600 -- Stop Condition 100 kHz mode 4700 -- Setup Time Hold Time FIGURE 27-19: 100 kHz mode Min 400 kHz mode 600 -- 100 kHz mode 4000 -- 400 kHz mode 600 -- ns ns I2CTM BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 27-4 for load conditions. 2005 Microchip Technology Inc. DS39612B-page 349 PIC18F6525/6621/8525/8621 TABLE 27-20: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR 103 TF TSU:STA 90 91 THD:STA 106 THD:DAT TSU:DAT 107 92 TSU:STO 109 TAA 110 TBUF D102 CB Note 1: 2: Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 -- s PIC18F6X2X/8X2X must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s PIC18F6X2X/8X2X must operate at a minimum of 10 MHz MSSP module 1.5 TCY -- 100 kHz mode 4.7 -- s PIC18F6X2X/8X2X must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s PIC18F6X2X/8X2X must operate at a minimum of 10 MHz MSSP module 1.5 TCY -- -- 1000 ns 20 + 0.1 CB 300 ns SDA and SCL Rise 100 kHz mode Time 400 kHz mode Conditions CB is specified to be from 10 to 400 pF SDA and SCL Fall Time 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF Start Condition Setup Time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Only relevant for Repeated Start condition Start Condition Hold Time 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s Data Input Hold Time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s Data Input Setup Time 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns Stop Condition Setup Time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Output Valid from Clock 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns Bus Free Time 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF Bus Capacitive Loading After this period, the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line. TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. DS39612B-page 350 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 MASTER SSP I2CTM BUS START/STOP BITS TIMING WAVEFORMS FIGURE 27-20: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-21: MASTER SSP I2CTM BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 91 92 93 Note 1: TSU:STA Characteristic Start Condition Setup Time THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time Min Max Units 100 kHz mode 2(TOSC)(BRG + 1) -- ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- Conditions ns ns Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 27-21: MASTER SSP I2CTM BUS DATA TIMING 103 102 100 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure 27-4 for load conditions. 2005 Microchip Technology Inc. DS39612B-page 351 PIC18F6525/6621/8525/8621 TABLE 27-22: MASTER SSP I2CTM BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms (1) Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 300 ns 1 MHz mode 102 103 90 91 106 107 92 109 110 D102 TR TF TSU:STA SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Setup Time THD:STA Start Condition Hold Time THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time TSU:STO Stop Condition Setup Time TAA TBUF CB Output Valid from Clock Bus Free Time 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 100 ns 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD -- ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode(1) TBD -- ns 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode -- 3500 ns 400 kHz mode -- 1000 ns (1) 1 MHz mode -- -- ns 100 kHz mode 4.7 -- ms 400 kHz mode 1.3 -- ms 1 MHz mode(1) TBD -- ms -- 400 pF Bus Capacitive Loading Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated (Note 2) Time the bus must be free before a new transmission can start Legend: TBD = To Be Determined Note 1: Maximum pin capacitance = 10 pF for all I2CTM pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line, parameter #102.+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released. DS39612B-page 352 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-22: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 121 121 RC7/RX1/DT1 pin 120 Note: 122 Refer to Figure 27-4 for load conditions. TABLE 27-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol No. 120 Characteristic TckH2dtV SYNC XMIT (Master and Slave) Clock High to Data Out Valid PIC18F6X2X/8X2X Min Max Units -- 40 ns PIC18LF6X2X/8X2X -- 100 ns 121 Tckrf Clock Out Rise Time and Fall Time PIC18F6X2X/8X2X (Master mode) PIC18LF6X2X/8X2X -- 20 ns -- 50 ns 122 Tdtrf Data Out Rise Time and Fall Time PIC18F6X2X/8X2X -- 20 ns PIC18LF6X2X/8X2X -- 50 ns FIGURE 27-23: Conditions EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 125 RC7/RX1/DT1 pin 126 Note: Refer to Figure 27-4 for load conditions. TABLE 27-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. 125 126 Symbol TdtV2ckl TckL2dtl Characteristic Min Max Units SYNC RCV (Master and Slave) Data Hold before CKx (DTx hold time) 10 -- ns Data Hold after CKx (DTx hold time) 15 -- ns 2005 Microchip Technology Inc. Conditions DS39612B-page 353 PIC18F6525/6621/8525/8621 TABLE 27-25: A/D CONVERTER CHARACTERISTICS:PIC18F6X2X/8X2X (INDUSTRIAL, EXTENDED) PIC18LF6X2X/8X2X (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units Conditions A01 NR Resolution -- -- -- -- 10 TBD bit bit VREF = VDD 3.0V VREF = VDD < 3.0V A03 EIL Integral Linearity Error -- -- -- -- <1 TBD LSb LSb VREF = VDD 3.0V VREF = VDD < 3.0V A04 EDL Differential Linearity Error -- -- -- -- <1 TBD LSb LSb VREF = VDD 3.0V VREF = VDD < 3.0V A05 EFS Full Scale Error -- -- -- -- <1 TBD LSb LSb VREF = VDD 3.0V VREF = VDD < 3.0V A06 EOFF Offset Error -- -- -- -- <1 TBD LSb LSb VREF = VDD 3.0V VREF = VDD < 3.0V A10 -- Monotonicity -- VSS VAIN VREF A20 VREF Reference Voltage (VREFH - VREFL) A21 VREFH Reference Voltage High A22 VREFL Reference Voltage Low A20A guaranteed(3) 0V -- -- V 3V AVSS -- -- V -- AVDD + 0.3V V AVSS - 0.3V -- AVDD V A25 VAIN Analog Input Voltage AVSS - 0.3V -- VREF + 0.3V V A30 ZAIN Recommended Impedance of Analog Voltage Source -- -- 10.0 k A40 IAD A/D Conversion PIC18F6X2X/8X2X Current (VDD) PIC18LF6X2X/8X2X -- 180 -- A -- 90 -- A -- -- -- -- 5 150 A A A50 IREF Legend: Note 1: 2: 3: VREF Input Current (Note 2) For 10-bit resolution Average current consumption when A/D is on (Note 1) During VAIN acquisition. During A/D conversion cycle. TBD = To Be Determined When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected as reference input. Vss VAIN VREF The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. DS39612B-page 354 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 27-24: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input. TABLE 27-26: A/D CONVERSION REQUIREMENTS Param. Symbol No. 130 TAD Characteristic A/D Clock Period Min Max Units Conditions PIC18F6X2X/8X2X 1.6 20(5) s TOSC based, VREF 3.0V PIC18LF6X2X/8X2X 3.0 20(5) s TOSC based, VREF full range PIC18F6X2X/8X2X 2.0 6.0 s A/D RC mode PIC18LF6X2X/8X2X 3.0 9.0 s A/D RC mode 131 TCNV Conversion Time (not including acquisition time) (Note 1) 11 12 TAD 132 TACQ Acquisition Time (Note 3) 15 10 -- -- s s -40C Temp +125C 0C Temp +125C 135 TSWC Switching Time from Convert Sample -- (Note 4) 136 TAMP Amplifier Settling Time (Note 2) 1 -- s This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: 2: 3: 4: 5: ADRES register may be read on the following TCY cycle. See Section 20.0 "10-Bit Analog-to-Digital Converter (A/D) Module" for minimum conditions when input voltage has changed more than 1 LSb. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50. On the next Q4 cycle of the device clock. The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2005 Microchip Technology Inc. DS39612B-page 355 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 356 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 28.0 Note: DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. "Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range. FIGURE 28-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 40 5.5V 36 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +85C) Minimum: mean - 3 (-40C to +85C) IDD (mA) 32 5.0V 28 4.5V 24 4.0V 20 3.5V 16 12 3.0V 8 2.5V 4 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 28-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 48 44 5.5V Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +85C) Minimum: mean - 3 (-40C to +85C) 40 IDD (mA) 36 5.0V 32 4.5V 28 4.0V 24 20 3.5V 16 3.0V 12 8 2.5V 4 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) 2005 Microchip Technology Inc. DS39612B-page 357 PIC18F6525/6621/8525/8621 FIGURE 28-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 40 36 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +85C) Minimum: mean - 3 (-40C to +85C) 32 28 5.5V IDD (mA) 24 5.0V 20 4.5V 4.2V 16 12 8 4 0 4 5 6 7 8 9 10 9 10 FOSC (MHz) FIGURE 28-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) 45 40 35 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +85C) Minimum: mean - 3 (-40C to +85C) 30 5.5V IDD (mA) 5.0V 25 4.5V 4.2V 20 15 10 5 0 4 5 6 7 8 FOSC (MHz) DS39612B-page 358 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 28-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 5 5.5V Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 4 5.0V 4.5V 4.0V 3 IDD (mA) 3.5V 3.0V 2 2.5V 2.0V 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 FOSC (MHz) FIGURE 28-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 7 5.5V 6 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 5.0V 4.5V 5 4.0V IDD (mA) 4 3.5V 3 3.0V 2.5V 2 2.0V 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 FOSC (MHz) 2005 Microchip Technology Inc. DS39612B-page 359 PIC18F6525/6621/8525/8621 FIGURE 28-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) LP mode, 25C 1 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 0.9 5.5V 0.8 5.0V 4.5V IDD (mA) 0.7 4.0V 0.6 3.5V 0.5 3.0V 2.5V 0.4 2.0V 0.3 0.2 20 30 40 50 60 70 80 90 100 80 90 100 FOSC (kHz) FIGURE 28-8: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 6 5.5V 5 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 5.0V IDD (mA) 4 4.5V 3 4.0V 2 3.5V 3.0V 1 2.5V 2.0V 0 20 30 40 50 60 70 FOSC (kHz) DS39612B-page 360 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 28-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 40 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +85C) Minimum: mean - 3 (-40C to +85C) 36 5.5V 32 5.0V 28 4.5V 4.2V IDD (mA) 24 4.0V 20 16 3.5V 12 3.0V 8 4 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 28-10: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 48 44 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +85C) Minimum: mean - 3 (-40C to +85C) 40 5.5V 5.0V 36 4.5V 32 4.2V IDD (mA) 28 4.0V 24 20 3.5V 16 12 3.0V 8 2.5V 4 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) 2005 Microchip Technology Inc. DS39612B-page 361 PIC18F6525/6621/8525/8621 FIGURE 28-11: TYPICAL AND MAXIMUM IT1OSC vs. VDD (TIMER1 AS SYSTEM CLOCK) 240 Typical: statistical mean @ 25C Maximum: mean + 3 (-10C to +70C) Minimum: mean - 3 (-10C to +70C) 220 200 180 160 IDD (uA) 140 120 100 80 Max (70C) 60 Typ (25C) 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-12: AVERAGE FOSC vs. VDD FOR VARIOUS Rs (RC MODE, C = 20 pF, TEMP = 25C) 6,000 Operation above 4 MHz is not recomended. 5,000 3.3k 3.3 3.3kk Freq (kHz) 4,000 5.1 k 5.1k 3,000 2,000 10 k 10k 1,000 100 k 100k 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39612B-page 362 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 28-13: 100 k AVERAGE FOSC vs. VDD FOR VARIOUS Rs (RC MODE, C = 100 pF, TEMP = 25C) 2,200 2,000 1,800 3.3 3.3kk 1,600 Freq (kHz) 1,400 5.1 5.1kk 1,200 1,000 800 10 10kk 600 400 200 100 100kk 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-14: AVERAGE FOSC vs. VDD FOR VARIOUS Rs (RC MODE, C = 300 pF, TEMP = 25C) 800 700 3.3 3.3kk 600 5.1 5.1kk Freq (MHz) 500 400 300 10 10kk 200 100 100 100kk 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2005 Microchip Technology Inc. DS39612B-page 363 PIC18F6525/6621/8525/8621 FIGURE 28-15: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 1000 Max (-40C to +125C) 100 Max (85C) IPD (uA) 10 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 1 Typ (25C) 0.1 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-16: TYPICAL AND MAXIMUM IBOR vs. VDD OVER TEMPERATURE, VBOR = 2.00-2.16V 300 Device Held in Reset 250 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) Max (+125C) IDD (uA) 200 Max (+85C) 150 Typ (+25C) 100 Device in Sleep 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39612B-page 364 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 28-17: IT1OSC vs. VDD (SLEEP MODE, TIMER1 AND OSCILLATOR ENABLED) 80 Typical: statistical mean @ 25C Maximum: mean + 3 (-10C to +70C) Minimum: mean - 3 (-10C to +70C) 70 Max (70C) 60 IPD (uA) 50 40 30 20 Typ (25C) 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-18: IPD vs. VDD (SLEEP MODE, WDT ENABLED) 1000 Max (-40C to +125C) Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 100 IPD (uA) Max (85C) 10 1 Typ (25C) 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2005 Microchip Technology Inc. DS39612B-page 365 PIC18F6525/6621/8525/8621 FIGURE 28-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD 40 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 35 Max (125C) WDT Period (ms) 30 Max (85C) 25 20 Typ (25C) 15 10 Min (-40C) 5 0 2.5 3.0 FIGURE 28-20: 3.5 4.0 VDD (V) 4.5 5.0 5.5 ILVD vs. VDD OVER TEMPERATURE, VLVD = 4.5-4.78V 250 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) Max (125C) 200 Max (125C) 150 IDD (A) LVDIF state is unknown Typ (25C) 100 LVDIF can be cleared by firmware 50 Typ (25C) LVDIF is set by hardware 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39612B-page 366 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 28-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.5 5.0 4.5 Max Max 4.0 Typ Typ(+25C) (25C) VOH (V) 3.5 3.0 Min Min 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 28-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.0 2.5 2.0 VOH (V) Max Max 1.5 Typ Typ(+25C) (25C) 1.0 Min Min 0.5 0.0 0 5 10 15 20 25 IOH (-mA) 2005 Microchip Technology Inc. DS39612B-page 367 PIC18F6525/6621/8525/8621 FIGURE 28-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.8 1.6 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 1.4 VOL (V) 1.2 1.0 Max Max 0.8 0.6 0.4 Typ (+25C) Typ (25C) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 28-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 2.5 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 2.0 VOL (V) 1.5 1.0 Max Max Typ Typ(+25C) (25C) 0.5 0.0 0 5 10 15 20 25 IOL (-mA) DS39612B-page 368 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 28-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.0 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 3.5 VIH Max 3.0 2.5 VIN (V) VIH Min 2.0 VIL Max 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C) 1.6 Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 1.4 VTH (Max) 1.2 VTH (Min) VIN (V) 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2005 Microchip Technology Inc. DS39612B-page 369 PIC18F6525/6621/8525/8621 MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C) FIGURE 28-27: 3.5 VIH Max Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C) 3.0 2.5 2.0 VIN (V) VVILILMax VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-28: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) 4 3.5 Differential or Integral Nonlinearity (LSB) -40C -40C 3 +25C 25C 2.5 +85C 85C 2 1.5 1 0.5 +125C 125C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) DS39612B-page 370 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 28-29: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125C) Max (-40C (-40C toto125C) 1 Typ Typ (+25C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) 2005 Microchip Technology Inc. DS39612B-page 371 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 372 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F6621 -I/PT e3 0410017 Example 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: PIC18F8621 -E/PT e3 0410017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2005 Microchip Technology Inc. DS39612B-page 373 PIC18F6525/6621/8525/8621 29.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A2 A1 (F) Units Dimension Limits n p MIN INCHES NOM 64 .020 16 .043 .039 .006 .024 .039 3.5 .472 .472 .394 .394 .007 .009 .035 10 10 MAX MILLIMETERS* NOM 64 0.50 16 1.00 1.10 0.95 1.00 0.05 0.15 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.13 0.18 0.17 0.22 0.64 0.89 5 10 5 10 MIN Number of Pins Pitch Pins per Side n1 Overall Height A .039 .047 Molded Package Thickness A2 .037 .041 Standoff A1 .002 .010 Foot Length L .018 .030 (F) Footprint (Reference) Foot Angle 0 7 Overall Width E .463 .482 Overall Length D .463 .482 Molded Package Width E1 .390 .398 Molded Package Length D1 .390 .398 c Lead Thickness .005 .009 Lead Width B .007 .011 Pin 1 Corner Chamfer CH .025 .045 Mold Draft Angle Top 5 15 Mold Draft Angle Bottom 5 15 *Controlling Parameter Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.20 1.05 0.25 0.75 7 12.25 12.25 10.10 10.10 0.23 0.27 1.14 15 15 JEDEC Equivalent: MS-026 Drawing No. C04-085 DS39612B-page 374 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A2 A1 (F) Units Dimension Limits n p MIN INCHES NOM 80 .020 20 .043 .039 .004 .024 .039 3.5 .551 .551 .472 .472 .006 .009 .035 10 10 MAX MILLIMETERS* NOM 80 0.50 20 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 13.75 14.00 13.75 14.00 11.75 12.00 11.75 12.00 0.09 0.15 0.17 0.22 0.64 0.89 5 10 5 10 MIN Number of Pins Pitch Pins per Side n1 Overall Height A .047 .039 Molded Package Thickness A2 .037 .041 Standoff A1 .002 .006 Foot Length L .018 .030 (F) Footprint (Reference) Foot Angle 0 7 Overall Width E .541 .561 Overall Length D .541 .561 Molded Package Width E1 .463 .482 Molded Package Length D1 .463 .482 c Lead Thickness .004 .008 Lead Width B .007 .011 Pin 1 Corner Chamfer CH .025 .045 Mold Draft Angle Top 5 15 Mold Draft Angle Bottom 5 15 *Controlling Parameter Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.20 1.05 0.15 0.75 7 14.25 14.25 12.25 12.25 0.20 0.27 1.14 15 15 JEDEC Equivalent: MS-026 Drawing No. C04-092 2005 Microchip Technology Inc. DS39612B-page 375 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 376 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 APPENDIX A: REVISION HISTORY Revision A (July 2003) Original data sheet for PIC18F6525/6621/8525/8621 family. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (August 2004) This revision includes updates to the Electrical Specifications in Section 27.0, the DC and AC Characteristics Graphs and Tables in Section 28.0 have been added and includes minor corrections to the data sheet text. TABLE B-1: DEVICE DIFFERENCES Feature PIC18F6525 PIC18F6621 PIC18F8525 PIC18F8621 On-chip Program Memory (Kbytes) 48K 64K 48K 64K Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J I/O Ports A/D Channels 12 12 16 16 External Memory Interface No No Yes Yes 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP Package Types 2005 Microchip Technology Inc. DS39612B-page 377 PIC18F6525/6621/8525/8621 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC17C756 to a PIC18F8720. Not Applicable APPENDIX D: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442." The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716. DS39612B-page 378 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration." This Application Note is available as Literature Number DS00726. 2005 Microchip Technology Inc. DS39612B-page 379 PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 380 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 INDEX A A/D .................................................................................... 233 Acquisition Requirements ......................................... 238 Acquisition Time........................................................ 238 ADCON0 Register..................................................... 233 ADCON1 Register..................................................... 233 ADCON2 Register..................................................... 233 ADRESH Register............................................. 233, 236 ADRESL Register ............................................. 233, 236 Analog Port Pins ....................................................... 128 Analog Port Pins, Configuring................................... 240 Associated Register Summary.................................. 241 Automatic Acquisition Time....................................... 239 Calculating Minimum Required Acquisition Time ............................................... 238 Configuring the Module............................................. 237 Conversion Clock (TAD) ............................................ 239 Conversion Status (GO/DONE Bit) ........................... 236 Conversion TAD Cycles............................................. 240 Conversions .............................................................. 240 Converter Characteristics ......................................... 354 Converter Interrupt, Configuring ............................... 237 ECCP2 Special Event Trigger................................... 241 Equations .................................................................. 238 Minimum Charging Time........................................... 238 Selecting and Configuring Acquisition Time ............................................... 239 Special Event Trigger (ECCP) .................................. 160 TAD vs. Device Operating Frequencies (table) ........................................... 239 Absolute Maximum Ratings .............................................. 323 AC (Timing) Characteristics .............................................. 335 Load Conditions for Device Timing Specifications ........................................ 336 Parameter Symbology .............................................. 335 Temperature and Voltage Specifications.................................................... 336 Timing Conditions ..................................................... 336 ACKSTAT ......................................................................... 203 ACKSTAT Status Flag ...................................................... 203 ADCON0 Register............................................................. 233 GO/DONE Bit............................................................ 236 ADCON1 Register............................................................. 233 ADCON2 Register............................................................. 233 ADDLW ............................................................................. 281 ADDWF ............................................................................. 281 ADDWFC .......................................................................... 282 ADRESH Register..................................................... 233, 236 ADRESL Register ..................................................... 233, 236 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................. 282 ANDWF ............................................................................. 283 Assembler MPASM Assembler................................................... 317 Auto-Wake-up on Sync Break Character .......................... 225 B Baud Rate Generator ........................................................ 199 BC ..................................................................................... 283 BCF ................................................................................... 284 BF ..................................................................................... 203 BF Status Flag .................................................................. 203 2005 Microchip Technology Inc. Block Diagrams 16-Bit Byte Select Mode ............................................. 75 16-Bit Byte Write Mode............................................... 73 16-Bit Word Write Mode ............................................. 74 A/D............................................................................ 236 Analog Input Model................................................... 237 Baud Rate Generator ............................................... 199 Capture Mode Operation .......................................... 151 Comparator Analog Input Model............................... 247 Comparator I/O Operating Modes ............................ 244 Comparator Output................................................... 246 Comparator Voltage Reference................................ 250 Comparator Voltage Reference Output Buffer Example ..................................... 251 Compare Mode Operation ........................................ 152 Enhanced PWM........................................................ 161 EUSART Receive ..................................................... 223 EUSART Transmit .................................................... 221 Low-Voltage Detect (LVD)........................................ 254 Low-Voltage Detect with External Input.................... 254 MCLR/VPP/RG5 Pin.................................................. 121 MSSP (I2C Master Mode)......................................... 197 MSSP (I2C Mode)..................................................... 182 MSSP (SPI Mode) .................................................... 173 On-Chip Reset Circuit................................................. 29 PIC18F6525/6621 ........................................................ 9 PIC18F8525/8621 ...................................................... 10 PLL ............................................................................. 23 Port/LAT/TRIS Operation ......................................... 103 PORTC (Peripheral Output Override)....................... 109 PORTD and PORTE (Parallel Slave Port)................ 128 PORTD in I/O Port Mode.......................................... 111 PORTD in System Bus Mode ................................... 112 PORTE in I/O Mode.................................................. 115 PORTE in System Bus Mode ................................... 115 PORTG (Peripheral Output Override) ...................... 120 PORTJ in I/O Mode .................................................. 125 PWM Operation (Simplified) ..................................... 154 RA3:RA0 and RA5 Pins............................................ 104 RA4/T0CKI Pin ......................................................... 104 RA6 Pin (Enabled as I/O) ......................................... 104 RB2:RB0 Pins........................................................... 107 RB3 Pin .................................................................... 107 RB7:RB4 Pins........................................................... 106 Reads from Flash Program Memory .......................... 65 RF1/AN6/C2OUT and RF2/AN7/C1OUT Pins.......... 117 RF6:RF3 and RF0 Pins ............................................ 118 RF7 Pin..................................................................... 118 RH3:RH0 Pins in I/O Mode....................................... 122 RH3:RH0 Pins in System Bus Mode ........................ 123 RH7:RH4 Pins in I/O Mode....................................... 122 RJ4:RJ0 Pins in System Bus Mode.......................... 126 RJ7:RJ6 Pins in System Bus Mode.......................... 126 Single Comparator.................................................... 245 Table Read Operation ................................................ 61 Table Write Operation ................................................ 62 Table Writes to Flash Program Memory ..................... 67 Timer0 in 16-Bit Mode .............................................. 132 Timer0 in 8-Bit Mode ................................................ 132 Timer1 ...................................................................... 136 Timer1 (16-Bit Read/Write Mode)............................. 136 Timer2 ...................................................................... 142 DS39612B-page 381 PIC18F6525/6621/8525/8621 Timer3 ....................................................................... 144 Timer3 (16-Bit Read/Write Mode) ............................. 144 Timer4 ....................................................................... 148 Watchdog Timer........................................................ 268 BN ..................................................................................... 284 BNC................................................................................... 285 BNN................................................................................... 285 BNOV ................................................................................ 286 BNZ ................................................................................... 286 BOR. See Brown-out Reset. BOV................................................................................... 289 BRA................................................................................... 287 Break Character (12-Bit) Transmit and Receive ............... 226 BRG. See Baud Rate Generator. Brown-out Reset (BOR) .............................................. 30, 259 BSF ................................................................................... 287 BTFSC .............................................................................. 288 BTFSS............................................................................... 288 BTG................................................................................... 289 BZ...................................................................................... 290 C C Compilers MPLAB C17 .............................................................. 318 MPLAB C18 .............................................................. 318 MPLAB C30 .............................................................. 318 CALL ................................................................................. 290 Capture (CCP Module)...................................................... 151 Associated Registers ................................................ 153 CCP Pin Configuration .............................................. 151 CCPR4H:CCPR4L Registers .................................... 151 Software Interrupt ..................................................... 151 Timer1/Timer3 Mode Selection ................................. 151 Capture (ECCP Module) ................................................... 160 Capture/Compare/PWM (CCP)......................................... 149 Capture Mode. See Capture. CCP Mode and Timer Resources ............................. 150 CCPRxH Register ..................................................... 150 CCPRxL Register...................................................... 150 Compare Mode. See Compare. Interconnect Configurations ...................................... 150 Module Configuration ................................................ 150 PWM Mode. See PWM. Clocking Scheme/Instruction Cycle..................................... 44 CLRF................................................................................. 291 CLRWDT........................................................................... 291 Code Examples 16 x 16 Signed Multiply Routine ................................. 86 16 x 16 Unsigned Multiply Routine ............................. 86 8 x 8 Signed Multiply Routine ..................................... 85 8 x 8 Unsigned Multiply Routine ................................. 85 Changing Between Capture Prescalers .................... 151 Computed GOTO Using an Offset Value .................... 46 Data EEPROM Read .................................................. 81 Data EEPROM Refresh Routine ................................. 82 Data EEPROM Write .................................................. 81 Erasing a Flash Program Memory Row ...................... 66 Fast Register Stack..................................................... 44 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................. 56 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ................................... 138 Initializing PORTA ..................................................... 103 Initializing PORTB ..................................................... 106 Initializing PORTC..................................................... 109 Initializing PORTD..................................................... 111 DS39612B-page 382 Initializing PORTE..................................................... 114 Initializing PORTF..................................................... 117 Initializing PORTG .................................................... 120 Initializing PORTH .................................................... 122 Initializing PORTJ ..................................................... 125 Loading the SSPBUF (SSPSR) Register.................. 176 Reading a Flash Program Memory Word ................... 65 Saving STATUS, WREG and BSR Registers in RAM ..................................... 102 Writing to Flash Program Memory ........................ 68-69 Code Protection ........................................................ 259, 270 Associated Registers ................................................ 271 Configuration Register Protection............................. 273 Data EEPROM.......................................................... 273 Program Memory ...................................................... 271 COMF ............................................................................... 292 Comparator....................................................................... 243 Analog Input Connection Considerations ................. 247 Associated Registers ................................................ 248 Configuration ............................................................ 244 Effects of a Reset ..................................................... 247 Interrupts .................................................................. 246 Operation .................................................................. 245 Operation During Sleep ............................................ 247 Outputs ..................................................................... 245 Reference ................................................................. 245 External Signal ................................................. 245 Internal Signal................................................... 245 Response Time......................................................... 245 Comparator Specifications................................................ 332 Comparator Voltage Reference ........................................ 249 Accuracy and Error ................................................... 250 Associated Registers ................................................ 251 Configuring ............................................................... 249 Connection Considerations....................................... 250 Effects of a Reset ..................................................... 250 Operation During Sleep ............................................ 250 Compare (CCP Module) ................................................... 152 Associated Registers ................................................ 153 CCP Pin Configuration.............................................. 152 CCPR1 Register ....................................................... 152 Software Interrupt ..................................................... 152 Special Event Trigger ............................................... 152 Timer1/Timer3 Mode Selection................................. 152 Compare (ECCP Module)................................................. 160 Special Event Trigger ............................... 137, 145, 160 Configuration Bits ............................................................. 259 Context Saving During Interrupts...................................... 102 Control Registers EECON1 and EECON2 .............................................. 62 TABLAT (Table Latch) Register.................................. 64 TBLPTR (Table Pointer) Register............................... 64 Conversion Considerations............................................... 378 CPFSEQ ........................................................................... 292 CPFSGT ........................................................................... 293 CPFSLT ............................................................................ 293 D Data EEPROM Memory...................................................... 79 Associated Registers .................................................. 83 EEADR Register ......................................................... 79 EEADRH Register ...................................................... 79 EECON1 Register....................................................... 79 EECON2 Register....................................................... 79 Operation During Code-Protect .................................. 82 Protection Against Spurious Write .............................. 82 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Reading....................................................................... 81 Using........................................................................... 82 Write Verify ................................................................. 82 Writing To.................................................................... 81 Data Memory ...................................................................... 47 General Purpose Registers......................................... 47 Map for PIC18F6X2X/8X2X Devices .......................... 48 Special Function Registers ......................................... 47 DAW.................................................................................. 294 DC and AC Characteristics Graphs and Tables ................................................... 357 DC Characteristics ............................................................ 330 Power-Down and Supply Current ............................. 326 Supply Voltage.......................................................... 325 DCFSNZ ........................................................................... 295 DECF ................................................................................ 294 DECFSZ............................................................................ 295 Demonstration Boards PICDEM 1 ................................................................. 320 PICDEM 17 ............................................................... 321 PICDEM 18R ............................................................ 321 PICDEM 2 Plus ......................................................... 320 PICDEM 3 ................................................................. 320 PICDEM 4 ................................................................. 320 PICDEM LIN ............................................................. 321 PICDEM USB............................................................ 321 PICDEM.net Internet/Ethernet .................................. 320 Development Support ....................................................... 317 Device Differences ............................................................ 377 Direct Addressing................................................................ 57 Direct Addressing........................................................ 55 E ECCP Capture and Compare Modes................................... 160 Standard PWM Mode................................................ 160 Electrical Characteristics................................................... 323 Enhanced Capture/Compare/PWM (ECCP) ..................... 157 and Program Memory modes ................................... 158 Capture Mode. See Capture (ECCP Module). Outputs and Configuration ........................................ 158 Pin Configurations for ECCP1 .................................. 158 Pin Configurations for ECCP2 .................................. 159 Pin Configurations for ECCP3 .................................. 159 PWM Mode. See PWM (ECCP Module). Timer Resources....................................................... 160 Use with CCP4 and CCP5 ........................................ 158 Enhanced PWM Mode. See PWM (ECCP Module). Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................... 213 Errata .................................................................................... 5 EUSART Asynchronous Mode ................................................. 221 12-Bit Break Transmit and Receive .................. 226 Associated Registers, Receive ......................... 224 Associated Registers, Transmit ........................ 222 Auto-Wake-up on Sync Break .......................... 225 Receiver............................................................ 223 Setting Up 9-Bit Mode with Address Detect ......................................... 223 Transmitter........................................................ 221 2005 Microchip Technology Inc. Baud Rate Generator (BRG) .................................... 217 Associated Registers........................................ 217 Auto-Baud Rate Detect..................................... 220 Baud Rate Error, Calculating............................ 217 Baud Rates, Asynchronous Modes .................. 218 High Baud Rate Select (BRGH Bit) .................. 217 Sampling .......................................................... 217 Synchronous Master Mode....................................... 227 Associated Registers, Receive......................... 230 Associated Registers, Transmit........................ 228 Reception ......................................................... 229 Transmission .................................................... 227 Synchronous Slave Mode......................................... 231 Associated Registers, Receive......................... 232 Associated Registers, Transmit........................ 231 Reception ......................................................... 232 Transmission .................................................... 231 Evaluation and Programming Tools.................................. 321 Extended Microcontroller Mode .......................................... 71 External Memory Interface.................................................. 71 16-Bit Byte Select Mode ............................................. 75 16-Bit Byte Write Mode............................................... 73 16-Bit Mode ................................................................ 73 16-Bit Mode Timing .................................................... 76 16-Bit Word Write Mode ............................................. 74 PIC18F8X2X External Bus I/O Port Functions............................................... 72 Program Memory Modes and External Memory Interface................................................ 71 F Flash Program Memory ...................................................... 61 Associated Registers.................................................. 69 Control Registers........................................................ 62 Erase Sequence ......................................................... 66 Erasing ....................................................................... 66 Operation During Code-Protect .................................. 69 Reading ...................................................................... 65 Table Pointer Boundaries Based on Operation ........................ 64 Table Pointer Boundaries ........................................... 64 Table Reads and Table Writes ................................... 61 Write Sequence .......................................................... 67 Writing To ................................................................... 67 Protection Against Spurious Writes .................... 69 Unexpected Termination .................................... 69 Write Verify ......................................................... 69 G General Call Address Support .......................................... 196 GOTO ............................................................................... 296 H Hardware Multiplier............................................................. 85 Introduction................................................................. 85 Operation.................................................................... 85 Performance Comparison........................................... 85 DS39612B-page 383 PIC18F6525/6621/8525/8621 I I/O Ports ............................................................................ 103 I2C Mode Associated Registers ................................................ 212 General Call Address Support .................................. 196 Master Mode Operation .......................................................... 198 Master Mode Transmit Sequence ............................. 198 Read/Write Bit Information (R/W Bit) ................ 186, 187 Serial Clock (RC3/SCK/SCL) .................................... 187 ID Locations .............................................................. 259, 274 INCF.................................................................................. 296 INCFSZ ............................................................................. 297 In-Circuit Debugger ........................................................... 274 Resources (table)...................................................... 274 In-Circuit Serial Programming (ICSP) ....................... 259, 274 Indirect Addressing ............................................................. 57 INDF and FSR Registers ............................................ 56 Operation .................................................................... 56 Indirect Addressing Operation............................................. 57 Indirect File Operand........................................................... 47 INFSNZ ............................................................................. 297 Initialization Conditions for All Registers ....................... 32-36 Instruction Flow/Pipelining .................................................. 45 Instruction Set ADDLW ..................................................................... 281 ADDWF ..................................................................... 281 ADDWFC .................................................................. 282 ANDLW ..................................................................... 282 ANDWF ..................................................................... 283 BC ............................................................................. 283 BCF ........................................................................... 284 BN ............................................................................. 284 BNC .......................................................................... 285 BNN .......................................................................... 285 BNOV ........................................................................ 286 BNZ ........................................................................... 286 BOV .......................................................................... 289 BRA........................................................................... 287 BSF ........................................................................... 287 BTFSC ...................................................................... 288 BTFSS ...................................................................... 288 BTG........................................................................... 289 BZ ............................................................................. 290 CALL ......................................................................... 290 CLRF......................................................................... 291 CLRWDT................................................................... 291 COMF ....................................................................... 292 CPFSEQ ................................................................... 292 CPFSGT ................................................................... 293 CPFSLT .................................................................... 293 DAW.......................................................................... 294 DCFSNZ ................................................................... 295 DECF ........................................................................ 294 DECFSZ.................................................................... 295 Firmware Instructions................................................ 275 General Format ......................................................... 277 GOTO ....................................................................... 296 INCF.......................................................................... 296 INCFSZ ..................................................................... 297 INFSNZ ..................................................................... 297 IORLW ...................................................................... 298 IORWF ...................................................................... 298 LFSR ......................................................................... 299 DS39612B-page 384 MOVF ....................................................................... 299 MOVFF ..................................................................... 300 MOVLB ..................................................................... 300 MOVLW .................................................................... 301 MOVWF .................................................................... 301 MULLW..................................................................... 302 MULWF..................................................................... 302 NEGF........................................................................ 303 NOP .......................................................................... 303 Opcode Field Descriptions........................................ 276 POP .......................................................................... 304 PUSH........................................................................ 304 RCALL ...................................................................... 305 RESET...................................................................... 305 RETFIE ..................................................................... 306 RETLW ..................................................................... 306 RETURN................................................................... 307 RLCF ........................................................................ 307 RLNCF...................................................................... 308 RRCF........................................................................ 308 RRNCF ..................................................................... 309 SETF ........................................................................ 309 SLEEP ...................................................................... 310 SUBFWB .................................................................. 310 SUBLW ..................................................................... 311 SUBWF..................................................................... 311 SUBWFB .................................................................. 312 SWAPF ..................................................................... 312 TBLRD ...................................................................... 313 TBLWT ..................................................................... 314 TSTFSZ .................................................................... 315 XORLW .................................................................... 315 XORWF .................................................................... 316 Summary Table ........................................................ 278 INT Interrupt (RB3/INT3:RB0/INT0). See Interrupt Sources. INTCON Registers.............................................................. 89 Inter-Integrated Circuit. See I2C. Interrupt Logic (diagram) .................................................... 88 Interrupt Sources .............................................................. 259 A/D Conversion Complete ........................................ 237 Capture Complete (CCP).......................................... 151 Compare Complete (CCP)........................................ 152 INT0 .......................................................................... 102 Interrupt-on-Change (RB7:RB4) ............................... 106 PORTB, Interrupt-on-Change ................................... 102 RB3/INT3:RB0/INT0/FLT0 Pins, External................. 102 TMR0 ........................................................................ 102 TMR0 Overflow......................................................... 133 TMR1 Overflow................................................. 135, 137 TMR2 to PR2 Match ................................................. 142 TMR2 to PR2 Match (PWM) ..................... 141, 154, 160 TMR3 Overflow................................................. 143, 145 TMR4 to PR4 Match ................................................. 148 TMR4 to PR4 Match (PWM) ..................................... 147 Interrupts............................................................................. 87 Control Registers ........................................................ 89 Enable Registers ........................................................ 95 Flag Registers............................................................. 92 Priority Registers ........................................................ 98 Reset Control Registers............................................ 101 IORLW .............................................................................. 298 IORWF .............................................................................. 298 IPR Registers...................................................................... 98 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 K Key Features Easy Migration .............................................................. 7 Expanded Memory........................................................ 7 External Memory Interface............................................ 7 Other Special Features ................................................. 7 L LFSR ................................................................................. 299 Low-Voltage Detect........................................................... 253 Characteristics .......................................................... 333 Converter Characteristics ......................................... 333 Effects of a Reset...................................................... 257 Operation .................................................................. 256 Current Consumption........................................ 257 During Sleep ..................................................... 257 Reference Voltage Set Point ............................ 257 Typical Application .................................................... 253 Low-Voltage ICSP Programming ...................................... 274 LVD. See Low-Voltage Detect. M Master SSP (MSSP) Module Overview ............................ 173 Master Synchronous Serial Port (MSSP). See MSSP. Master Synchronous Serial Port. See MSSP Memory Mode Memory Access ................................................ 40 Memory Maps for PIC18F6X2X/8X2X Program Memory Modes ............................................ 41 Memory Organization Data Memory .............................................................. 47 Program Memory ........................................................ 39 Modes ................................................................. 39 Memory Programming Requirements ............................... 334 Microcontroller Mode .......................................................... 71 Microprocessor Mode ......................................................... 71 Microprocessor with Boot Block Mode ................................ 71 Migration from High-End to Enhanced Devices .................................................... 379 Migration from Mid-Range to Enhanced Devices .................................................... 378 MOVF................................................................................ 299 MOVFF ............................................................................. 300 MOVLB ............................................................................. 300 MOVLW ............................................................................ 301 MOVWF ............................................................................ 301 MPLAB ASM30 Assembler, Linker, Librarian ................... 318 MPLAB ICD 2 In-Circuit Debugger ................................... 319 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................... 319 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator .................................... 319 MPLAB Integrated Development Environment Software............................................... 317 MPLAB PM3 Device Programmer .................................... 319 MPLINK Object Linker/MPLIB Object Librarian ................ 318 MSSP ................................................................................ 173 ACK Pulse......................................................... 186, 187 Clock Stretching........................................................ 192 10-Bit Slave Receive Mode (SEN = 1).............. 192 10-Bit Slave Transmit Mode ............................. 192 7-Bit Slave Receive Mode (SEN = 1)................ 192 7-Bit Slave Transmit Mode ............................... 192 Clock Synchronization and the CKP bit (SEN = 1)............................................. 193 2005 Microchip Technology Inc. Control Registers (general) ...................................... 173 Enabling SPI I/O ....................................................... 177 I2C Mode .................................................................. 182 Acknowledge Sequence Timing ....................... 206 Baud Rate Generator ....................................... 199 Bus Collision During a Repeated Start Condition.................................. 210 Bus Collision During a Start Condition ............. 208 Bus Collision During a Stop Condition.............. 211 Clock Arbitration ............................................... 200 Effect of a Reset ............................................... 207 I2C Clock Rate w/BRG ..................................... 199 Master Mode..................................................... 197 Reception ................................................. 203 Repeated Start Condition Timing ............. 202 Start Condition Timing.............................. 201 Transmission ............................................ 203 Multi-Master Communication, Bus Collision and Arbitration ........................... 207 Multi-Master Mode............................................ 207 Registers .......................................................... 182 Sleep Operation ............................................... 207 Stop Condition Timing ...................................... 206 Module Operation ..................................................... 186 Operation.................................................................. 176 Slave Mode............................................................... 186 Addressing ....................................................... 186 Reception ......................................................... 187 Transmission .................................................... 187 SPI Master Mode...................................................... 178 SPI Mode.................................................................. 173 SPI Slave Mode........................................................ 179 SSPBUF ................................................................... 178 SSPSR ..................................................................... 178 TMR2 Output for Clock Shift............................. 141, 142 TMR4 Output for Clock Shift..................................... 148 Typical Connection ................................................... 177 MSSP Module SPI Master/Slave Connection................................... 177 MULLW............................................................................. 302 MULWF............................................................................. 302 N NEGF................................................................................ 303 NOP .................................................................................. 303 O Oscillator Configuration ...................................................... 21 EC............................................................................... 21 ECIO........................................................................... 21 ECIO+PLL .................................................................. 21 ECIO+SPLL ................................................................ 21 HS............................................................................... 21 HS+PLL ...................................................................... 21 HS+SPLL.................................................................... 21 LP ............................................................................... 21 RC .............................................................................. 21 RCIO........................................................................... 21 XT ............................................................................... 21 Oscillator Selection ........................................................... 259 Oscillator, Timer1.............................................. 135, 137, 145 Oscillator, Timer3.............................................................. 143 Oscillator, WDT................................................................. 267 DS39612B-page 385 PIC18F6525/6621/8525/8621 P Packaging ......................................................................... 373 Details ....................................................................... 374 Marking ..................................................................... 373 Parallel Slave Port (PSP) .......................................... 111, 128 Associated Registers ................................................ 130 RE0/AD8/RD/P2D Pin............................................... 128 RE1/AD9/WR/P2C Pin .............................................. 128 RE2/AD10/CS/P2B Pin ............................................. 128 Select (PSPMODE Bit) ..................................... 111, 128 Phase Locked Loop (PLL)................................................... 23 PICkit 1 Flash Starter Kit................................................... 321 PICSTART Plus Development Programmer ..................... 320 PIE Registers ...................................................................... 95 Pin Functions AVDD ........................................................................... 20 AVSS ........................................................................... 20 MCLR/VPP/RG5 .......................................................... 11 OSC1/CLKI ................................................................. 11 OSC2/CLKO/RA6 ....................................................... 11 RA0/AN0 ..................................................................... 12 RA1/AN1 ..................................................................... 12 RA2/AN2/VREF-........................................................... 12 RA3/AN3/VREF+.......................................................... 12 RA4/T0CKI .................................................................. 12 RA5/AN4/LVDIN ......................................................... 12 RA6 ............................................................................. 12 RB0/INT0/FLT0 ........................................................... 13 RB1/INT1 .................................................................... 13 RB2/INT2 .................................................................... 13 RB3/INT3/ECCP2/P2A ............................................... 13 RB4/KBI0 .................................................................... 13 RB5/KBI1/PGM ........................................................... 13 RB6/KBI2/PGC ........................................................... 13 RB7/KBI3/PGD ........................................................... 13 RC0/T1OSO/T13CKI .................................................. 14 RC1/T1OSI/ECCP2/P2A............................................. 14 RC2/ECCP1/P1A ........................................................ 14 RC3/SCK/SCL ............................................................ 14 RC4/SDI/SDA ............................................................. 14 RC5/SDO .................................................................... 14 RC6/TX1/CK1 ............................................................. 14 RC7/RX1/DT1 ............................................................. 14 RD0/AD0/PSP0........................................................... 15 RD1/AD1/PSP1........................................................... 15 RD2/AD2/PSP2........................................................... 15 RD3/AD3/PSP3........................................................... 15 RD4/AD4/PSP4........................................................... 15 RD5/AD5/PSP5........................................................... 15 RD6/AD6/PSP6........................................................... 15 RD7/AD7/PSP7........................................................... 15 RE0/AD8/RD/P2D ....................................................... 16 RE1/AD9/WR/P2C ...................................................... 16 RE2/AD10/CS/P2B ..................................................... 16 RE3/AD11/P3C ........................................................... 16 RE4/AD12/P3B ........................................................... 16 RE5/AD13/P1C ........................................................... 16 RE6/AD14/P1B ........................................................... 16 RE7/AD15/ECCP2/P2A .............................................. 16 RF0/AN5 ..................................................................... 17 RF1/AN6/C2OUT ........................................................ 17 RF2/AN7/C1OUT ........................................................ 17 DS39612B-page 386 RF3/AN8 ..................................................................... 17 RF4/AN9 ..................................................................... 17 RF5/AN10/CVREF ....................................................... 17 RF6/AN11 ................................................................... 17 RF7/SS ....................................................................... 17 RG0/ECCP3/P3A........................................................ 18 RG1/TX2/CK2............................................................. 18 RG2/RX2/DT2............................................................. 18 RG3/CCP4/P3D.......................................................... 18 RG4/CCP5/P1D.......................................................... 18 RH0/A16 ..................................................................... 19 RH1/A17 ..................................................................... 19 RH2/A18 ..................................................................... 19 RH3/A19 ..................................................................... 19 RH4/AN12/P3C........................................................... 19 RH5/AN13/P3B........................................................... 19 RH6/AN14/P1C........................................................... 19 RH7/AN15/P1B........................................................... 19 RJ0/ALE ..................................................................... 20 RJ1/OE ....................................................................... 20 RJ2/WRL .................................................................... 20 RJ3/WRH.................................................................... 20 RJ4/BA0 ..................................................................... 20 RJ5/CE ....................................................................... 20 RJ6/LB ........................................................................ 20 RJ7/UB ....................................................................... 20 VDD ............................................................................. 20 VSS ............................................................................. 20 Pinout I/O Descriptions ....................................................... 11 PIR Registers...................................................................... 92 PLL Lock Time-out.............................................................. 30 Pointer, FSR ....................................................................... 56 POP .................................................................................. 304 POR. See Power-on Reset. PORTA Associated Registers ................................................ 105 Functions .................................................................. 105 LATA Register .......................................................... 103 PORTA Register ....................................................... 103 TRISA Register......................................................... 103 PORTB Associated Registers ................................................ 108 Functions .................................................................. 108 LATB Register .......................................................... 106 PORTB Register ....................................................... 106 RB3/INT3:RB0/INT0/FLT0 Pins, External................. 102 TRISB Register......................................................... 106 PORTC Associated Registers ................................................ 110 Functions .................................................................. 110 LATC Register .......................................................... 109 PORTC Register....................................................... 109 RC3/SCK/SCL Pin .................................................... 187 TRISC Register......................................................... 109 PORTD ............................................................................. 128 Associated Registers ................................................ 113 Functions .................................................................. 113 LATD Register .......................................................... 111 Parallel Slave Port (PSP) Function........................... 111 PORTD Register....................................................... 111 TRISD Register......................................................... 111 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 PORTE Analog Port Pins ....................................................... 128 Associated Registers ................................................ 116 Functions .................................................................. 116 LATE Register........................................................... 114 PORTE Register ....................................................... 114 PSP Mode Select (PSPMODE Bit) ................... 111, 128 RE0/AD8/RD/P2D Pin............................................... 128 RE1/AD9/WR/P2C Pin.............................................. 128 RE2/AD10/CS/P2B Pin ............................................. 128 TRISE Register ......................................................... 114 PORTF Associated Registers ................................................ 119 Functions .................................................................. 119 LATF Register........................................................... 117 PORTF Register ....................................................... 117 TRISF Register ......................................................... 117 PORTG Associated Registers ................................................ 121 Functions .................................................................. 121 LATG Register .......................................................... 120 PORTG Register....................................................... 120 TRISG Register......................................................... 120 PORTH Associated Registers ................................................ 124 Functions .................................................................. 124 LATH Register .......................................................... 122 PORTH Register ....................................................... 122 TRISH Register......................................................... 122 PORTJ Associated Registers ................................................ 127 Functions .................................................................. 127 LATJ Register ........................................................... 125 PORTJ Register........................................................ 125 TRISJ Register.......................................................... 125 Postscaler, WDT Assignment (PSA Bit) ............................................... 133 Rate Select (T0PS2:T0PS0 Bits) .............................. 133 Switching Between Timer0 and WDT ....................... 133 Power-Down Mode. See Sleep. Power-on Reset (POR) ............................................... 30, 259 Oscillator Start-up Timer (OST) .......................... 30, 259 Power-up Timer (PWRT) .................................... 30, 259 Time-out Sequence..................................................... 30 Prescaler Timer2....................................................................... 161 Prescaler, Capture ............................................................ 151 Prescaler, Timer0.............................................................. 133 Assignment (PSA Bit) ............................................... 133 Rate Select (T0PS2:T0PS0 Bits) .............................. 133 Switching Between Timer0 and WDT ....................... 133 Prescaler, Timer2.............................................................. 154 PRO MATE II Universal Device Programmer ................... 319 Product Identification System ........................................... 393 Program Counter PCL, PCLATH and PCLATU Register ........................ 44 Program Memory Extended Microcontroller Mode .................................. 39 Instructions.................................................................. 45 Two-Word ........................................................... 46 Interrupt Vector ........................................................... 39 Map and Stack for PIC18FX525 ................................. 40 Map and Stack for PIC18FX621 ................................. 40 Microcontroller Mode .................................................. 39 Microprocessor Mode ................................................. 39 Microprocessor with Boot Block Mode........................ 39 Reset Vector ............................................................... 39 2005 Microchip Technology Inc. Program Verification ......................................................... 270 Programming, Device Instructions.................................... 275 PSP. See Parallel Slave Port. Pulse-Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH................................................................................ 304 PWM (CCP Module) ......................................................... 154 Associated Registers................................................ 156 CCPR4H:CCPR4L Registers ................................... 154 Duty Cycle ................................................................ 154 Example Frequencies/Resolutions ........................... 155 Period ....................................................................... 154 Setup for PWM Operation ........................................ 155 TMR2 to PR2 Match ......................................... 141, 154 TMR4 to PR4 Match ................................................. 147 PWM (ECCP Module)....................................................... 160 Associated Registers................................................ 172 CCPR1H:CCPR1L Registers ................................... 160 Direction Change in Full-Bridge Output Mode..................................................... 166 Duty Cycle ................................................................ 161 Effects of a Reset ..................................................... 171 Enhanced PWM Auto-Shutdown .............................. 168 Example Frequencies/Resolutions ........................... 161 Full-Bridge Application Example............................... 166 Full-Bridge Mode ...................................................... 165 Half-Bridge Mode...................................................... 163 Half-Bridge Output Mode Applications Example ....................................... 164 Output Configurations............................................... 162 Output Relationships (Active-High) .......................... 162 Output Relationships (Active-Low) ........................... 163 Period ....................................................................... 160 Programmable Dead-Band Delay............................. 168 Setup for PWM Operation ........................................ 171 Start-up Considerations ............................................ 170 TMR2 to PR2 Match ................................................. 160 Q Q Clock ..................................................................... 154, 161 R RAM. See Data Memory. RC Oscillator....................................................................... 22 RCALL .............................................................................. 305 RCON Registers ............................................................... 101 Register File........................................................................ 47 Registers ADCON0 (A/D Control 0).......................................... 233 ADCON1 (A/D Control 1).......................................... 234 ADCON2 (A/D Control 2).......................................... 235 BAUDCONx (Baud Rate Control)............................. 216 CCPxCON (Capture/Compare/PWM Control - CCP4, CCP5) .................................... 149 CCPxCON (Capture/Compare/PWM Control ECCP1, ECCP2, ECCP3 Modules).................. 157 CMCON (Comparator Control) ................................. 243 CONFIG1H (Configuration 1 High)........................... 260 CONFIG2H (Configuration 2 High)........................... 261 CONFIG2L (Configuration 2 Low) ............................ 261 CONFIG3H (Configuration 3 High)........................... 262 CONFIG3L (Configuration 3 Low) ...................... 41, 262 CONFIG4L (Configuration 4 Low) ............................ 263 CONFIG5H (Configuration 5 High)........................... 264 CONFIG5L (Configuration 5 Low) ............................ 263 CONFIG6H (Configuration 6 High)........................... 265 CONFIG6L (Configuration 6 Low) ............................ 264 DS39612B-page 387 PIC18F6525/6621/8525/8621 CONFIG7H (Configuration 7 High) ........................... 266 CONFIG7L (Configuration 7 Low)............................. 265 CVRCON (Comparator Voltage Reference Control)............................................ 249 Device ID Register 2 ................................................. 266 DEVID1 (Device ID Register 1)................................. 266 ECCPxAS (ECCP Auto-Shutdown Control) .............. 169 ECCPxDEL (PWM Configuration)............................. 168 EECON1 (Data EEPROM Control 1) .................... 63, 80 INTCON (Interrupt Control) ......................................... 89 INTCON2 (Interrupt Control 2) .................................... 90 INTCON3 (Interrupt Control 3) .................................... 91 IPR1 (Peripheral Interrupt Priority 1)........................... 98 IPR2 (Peripheral Interrupt Priority 2)........................... 99 IPR3 (Peripheral Interrupt Priority 3)......................... 100 LVDCON (Low-Voltage Detect Control).................... 255 MEMCON (Memory Control)....................................... 71 OSCCON (Oscillator Control) ..................................... 25 PIE1 (Peripheral Interrupt Enable 1) ........................... 95 PIE2 (Peripheral Interrupt Enable 2) ........................... 96 PIE3 (Peripheral Interrupt Enable 3) ........................... 97 PIR1 (Peripheral Interrupt Request (Flag) 1) ................................................ 92 PIR2 (Peripheral Interrupt Request (Flag) 2) ................................................ 93 PIR3 (Peripheral Interrupt Request (Flag) 3) ................................................ 94 PSPCON (Parallel Slave Port Control) ..................... 129 RCON (Reset Control) ........................................ 59, 101 RCSTAx (Receive Status and Control) ..................... 215 SSPCON1 (MSSP Control 1, I2C Mode) .................. 184 SSPCON1 (MSSP Control 1, SPI Mode) .................. 175 SSPCON2 (MSSP Control 2, I2C Mode) .................. 185 SSPSTAT (MSSP Status, I2C Mode)........................ 183 SSPSTAT (MSSP Status, SPI Mode) ....................... 174 STATUS ...................................................................... 58 STKPTR (Stack Pointer) ............................................. 43 Summary............................................................... 51-54 T0CON (Timer0 Control)........................................... 131 T1CON (Timer 1 Control).......................................... 135 T2CON (Timer 2 Control).......................................... 141 T3CON (Timer3 Control)........................................... 143 T4CON (Timer 4 Control).......................................... 147 TXSTAx (Transmit Status and Control) .................... 214 WDTCON (Watchdog Timer Control)........................ 267 RESET .............................................................................. 305 Reset........................................................................... 29, 259 MCLR Reset (normal operation) ................................. 29 MCLR Reset (Sleep) ................................................... 29 Power-on Reset .......................................................... 29 Programmable Brown-out Reset (BOR) ..................... 29 RESET Instruction ...................................................... 29 Stack Full Reset .......................................................... 29 Stack Underflow Reset ............................................... 29 Watchdog Timer (WDT) Reset.................................... 29 RETFIE ............................................................................. 306 RETLW.............................................................................. 306 RETURN ........................................................................... 307 Return Address Stack ......................................................... 42 and Associated Registers ........................................... 43 Revision History ................................................................ 377 RLCF................................................................................. 307 RLNCF .............................................................................. 308 RRCF ................................................................................ 308 RRNCF.............................................................................. 309 DS39612B-page 388 S SCK .................................................................................. 173 SDI.................................................................................... 173 SDO .................................................................................. 173 Serial Clock, SCK ............................................................. 173 Serial Data In (SDI)........................................................... 173 Serial Data Out (SDO) ...................................................... 173 Serial Peripheral Interface. See SPI Mode. SETF................................................................................. 309 Slave Select (SS).............................................................. 173 Slave Select Synchronization ........................................... 179 SLEEP .............................................................................. 310 Sleep......................................................................... 259, 269 Software Simulator (MPLAB SIM) .................................... 318 Software Simulator (MPLAB SIM30) ................................ 318 Special Event Trigger. See Compare (ECCP Mode). Special Event Trigger. See Compare (ECCP Module). Special Features of the CPU ............................................ 259 Configuration Registers .................................... 260-266 Special Function Registers ................................................. 47 Map............................................................................. 49 SPI Mode Associated Registers ................................................ 181 Bus Mode Compatibility ............................................ 181 Effects of a Reset ..................................................... 181 Master Mode............................................................. 178 Master/Slave Connection.......................................... 177 Serial Clock............................................................... 173 Serial Data In ............................................................ 173 Serial Data Out ......................................................... 173 Slave Mode............................................................... 179 Slave Select.............................................................. 173 Slave Select Synchronization ................................... 179 Sleep Operation........................................................ 181 SPI Clock .................................................................. 178 SS ..................................................................................... 173 SSPOV ............................................................................. 203 SSPOV Status Flag .......................................................... 203 SSPSTAT Register R/W Bit ............................................................. 186, 187 Status Bits Significance and Initialization Condition for RCON Register ............................................. 31 SUBFWB .......................................................................... 310 SUBLW ............................................................................. 311 SUBWF............................................................................. 311 SUBWFB .......................................................................... 312 SWAPF ............................................................................. 312 T T0CON Register PSA Bit ..................................................................... 133 T0CS Bit ................................................................... 133 T0PS2:T0PS0 Bits.................................................... 133 T0SE Bit ................................................................... 133 Table Pointer Operations (table)......................................... 64 TBLRD .............................................................................. 313 TBLWT.............................................................................. 314 Time-out in Various Situations............................................ 31 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Timer0 ............................................................................... 131 16-Bit Mode Timer Reads and Writes....................... 133 Associated Registers ................................................ 133 Clock Source Edge Select (T0SE Bit)....................... 133 Clock Source Select (T0CS Bit)................................ 133 Operation .................................................................. 133 Overflow Interrupt ..................................................... 133 Prescaler. See Prescaler, Timer0. Timer1 ............................................................................... 135 16-Bit Read/Write Mode............................................ 137 Associated Registers ................................................ 139 Operation .................................................................. 136 Oscillator ........................................................... 135, 137 Overflow Interrupt ............................................. 135, 137 Special Event Trigger (ECCP) .......................... 137, 160 TMR1H Register ....................................................... 135 TMR1L Register........................................................ 135 Use as a Real-Time Clock ........................................ 138 Timer2 ............................................................................... 141 Associated Registers ................................................ 142 MSSP Clock Shift.............................................. 141, 142 Operation .................................................................. 141 Postscaler. See Postscaler, Timer2. PR2 Register............................................. 141, 154, 160 Prescaler. See Prescaler, Timer2. TMR2 Register.......................................................... 141 TMR2 to PR2 Match Interrupt ........... 141, 142, 154, 160 Timer3 ............................................................................... 143 Associated Registers ................................................ 145 Operation .................................................................. 144 Oscillator ........................................................... 143, 145 Overflow Interrupt ............................................. 143, 145 Special Event Trigger (ECCP) .................................. 145 TMR3H Register ....................................................... 143 TMR3L Register........................................................ 143 Timer4 ............................................................................... 147 Associated Registers ................................................ 148 MSSP Clock Shift...................................................... 148 Operation .................................................................. 147 Postscaler. See Postscaler, Timer4. PR4 Register............................................................. 147 Prescaler. See Prescaler, Timer4. TMR4 Register.......................................................... 147 TMR4 to PR4 Match Interrupt ........................... 147, 148 Timing Diagrams A/D Conversion......................................................... 355 Acknowledge Sequence ........................................... 206 Asynchronous Reception .......................................... 224 Asynchronous Transmission..................................... 222 Asynchronous Transmission (Back to Back) .................................................. 222 Automatic Baud Rate Calculation ............................. 220 Auto-Wake-up Bit (WUE) During Normal Operation ............................................. 225 Auto-Wake-up Bit (WUE) During Sleep .................... 225 Baud Rate Generator with Clock Arbitration ............. 200 BRG Reset Due to SDA Arbitration During Start Condition ...................................... 209 Brown-out Reset (BOR) ............................................ 341 Bus Collision During a Repeated Start Condition (Case 1) ............................................ 210 Bus Collision During a Repeated Start Condition (Case 2) ............................................ 210 Bus Collision During a Start Condition (SCL = 0) .......................................... 209 2005 Microchip Technology Inc. Bus Collision During a Stop Condition (Case 1)............................................ 211 Bus Collision During a Stop Condition (Case 2)............................................ 211 Bus Collision During Start Condition (SDA Only) ....................................... 208 Bus Collision for Transmit and Acknowledge .................................................... 207 Capture/Compare/PWM (All ECCP/CCP Modules) ................................. 343 CLKO and I/O ........................................................... 338 Clock Synchronization .............................................. 193 Clock/Instruction Cycle ............................................... 44 EUSART Synchronous Receive (Master/Slave) .................................... 353 EUSART Synchronous Transmission (Master/Slave)............................ 353 Example SPI Master Mode (CKE = 0) ...................... 345 Example SPI Master Mode (CKE = 1) ...................... 346 Example SPI Slave Mode (CKE = 0) ........................ 347 Example SPI Slave Mode (CKE = 1) ........................ 348 External Clock (All Modes Except PLL).................... 337 External Memory Bus Timing for Sleep (Microprocessor Mode)....................................... 77 External Memory Bus Timing for TBLRD (Extended Microcontroller Mode) ....................... 76 External Memory Bus Timing for TBLRD (Microprocessor Mode)....................................... 76 Full-Bridge PWM Output........................................... 165 Half-Bridge Output.................................................... 163 I2C Bus Data............................................................. 349 I2C Bus Start/Stop Bits ............................................. 349 I2C Master Mode (7 or 10-Bit Transmission) ................................ 204 I2C Master Mode (7-Bit Reception) .......................... 205 I2C Master Mode First Start Bit Timing ..................... 201 I2C Slave Mode (10-Bit Reception, SEN = 0) ........... 190 I2C Slave Mode (10-Bit Reception, SEN = 1) ........... 195 I2C Slave Mode (10-Bit Transmission) ..................... 191 I2C Slave Mode (7-Bit Reception, SEN = 0) ............. 188 I2C Slave Mode (7-Bit Reception, SEN = 1) ............. 194 I2C Slave Mode (7-Bit Transmission) ....................... 189 Low-Voltage Detect .................................................. 256 Master SSP I2C Bus Data ........................................ 351 Master SSP I2C Bus Start/Stop Bits ......................... 351 Parallel Slave Port (PSP) ......................................... 344 Parallel Slave Port (PSP) Read................................ 130 Parallel Slave Port (PSP) Write ................................ 129 Program Memory Read ............................................ 339 Program Memory Write ............................................ 340 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) ..................................... 170 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ...................................... 170 PWM Direction Change ............................................ 167 PWM Direction Change at Near 100% Duty Cycle .............................................. 167 PWM Output ............................................................. 154 Repeated Start Condition ......................................... 202 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ........................... 341 Send Break Character Sequence............................. 226 Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) .............................. 196 DS39612B-page 389 PIC18F6525/6621/8525/8621 Slave Synchronization .............................................. 179 Slow Rise Time (MCLR Tied to VDD via 1 k Resistor)................................................ 38 SPI Mode (Master Mode) .......................................... 178 SPI Mode (Slave Mode with CKE = 0) ...................... 180 SPI Mode (Slave Mode with CKE = 1) ...................... 180 Stop Condition Receive or Transmit Mode ............... 206 Synchronous Reception (Master Mode, SREN)....................................... 229 Synchronous Transmission....................................... 227 Synchronous Transmission (Through TXEN) ........... 228 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD via 1 k Resistor) ............... 38 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 1 .................................... 37 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 2 .................................... 37 Time-out Sequence on Power-up (MCLR Tied to VDD via 1 k Resistor) ............................ 37 Timer0 and Timer1 External Clock ........................... 342 Timing for Transition Between Timer1 and OSC1 (EC with PLL Active, SCS1 = 1)............... 27 Timing for Transition Between Timer1 and OSC1 (HS with PLL Active, SCS1 = 1)............... 27 Transition Between Timer1 and OSC1 (HS, XT, LP)............................................. 26 Transition Between Timer1 and OSC1 (RC, EC)................................................... 28 Transition from OSC1 to Timer1 Oscillator ................. 26 Wake-up from Sleep via Interrupt ............................. 270 Timing Specifications ........................................................ 337 A/D Conversion Requirements ................................. 355 Capture/Compare/PWM Requirements .................... 343 CLKO and I/O Requirements .................................... 338 EUSART Synchronous Receive Requirements.................................................... 353 EUSART Synchronous Transmission Requirements.................................................... 353 Example SPI Mode Requirements (Master Mode, CKE = 0) ................................... 345 Example SPI Mode Requirements (Master Mode, CKE = 1) ................................... 346 Example SPI Mode Requirements (Slave Mode, CKE = 0) ..................................... 347 Example SPI Slave Mode Requirements (CKE = 1)................................... 348 DS39612B-page 390 External Clock Requirements ................................... 337 I2C Bus Data Requirements (Slave Mode) ............... 350 I2C Bus Start/Stop Bits Requirements (Slave Mode) .................................................... 349 Master SSP I2C Bus Data Requirements ................. 352 Master SSP I2C Bus Start/Stop Bits Requirements ................................................... 351 Parallel Slave Port Requirements............................. 344 PLL Clock ................................................................. 338 Program Memory Read Requirements ..................... 339 Program Memory Write Requirements ..................... 340 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ................ 341 Timer0 and Timer1 External Clock Requirements ......................................... 342 TRISE Register PSPMODE Bit................................................... 111, 128 TSTFSZ ............................................................................ 315 Two-Word Instructions Example Cases........................................................... 46 TXSTAx Register BRGH Bit .................................................................. 217 V Voltage Reference Specifications..................................... 332 W Wake-up from Sleep ................................................. 259, 269 Using Interrupts ........................................................ 269 Watchdog Timer (WDT)............................................ 259, 267 Associated Registers ................................................ 268 Control Register........................................................ 267 Postscaler ................................................................. 268 Programming Considerations ................................... 267 RC Oscillator............................................................. 267 Time-out Period ........................................................ 267 WCOL ....................................................... 201, 202, 203, 206 WCOL Status Flag.................................... 201, 202, 203, 206 WWW, On-Line Support ....................................................... 5 X XORLW............................................................................. 315 XORWF ............................................................................ 316 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com In addition, there is a Development Systems Information Line which lists the latest versions of Microchip's development systems software products. This line also provides information on how customers can receive currently available upgrade kits. The Development numbers are: Systems Information Line 1-800-755-2345 - United States and most of Canada 1-480-792-7302 - Other International Locations To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. 2005 Microchip Technology Inc. DS39612B-page 391 PIC18F6525/6621/8525/8621 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F6525/6621/8525/8621 Literature Number: DS39612B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39612B-page 392 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 PIC18F6525/6621/8525/8621 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. - PART NO. Device X Temperature Range /XX XXX Package Pattern Device PIC18F6525/6621/8525/8621(1), PIC18F6525/6621/8525/8621T(2); VDD range 4.2V to 5.5V PIC18LF6X2X/8X2X(1), PIC18LF6X2X/8X2XT(2); VDD range 2.0V to 5.5V Temperature Range I E Package PT = Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) = = -40C to +85C (Industrial) -40C to +125C (Extended) TQFP (Thin Quad Flatpack) 2005 Microchip Technology Inc. Examples: a) b) PIC18LF6621-I/PT 301 = Industrial temp., TQFP package, Extended VDD limits, QTP pattern #301. PIC18F8621-E/PT = Extended temp., TQFP package, standard VDD limits. Note 1: F LF 2: T = Standard Voltage Range = Extended Voltage Range = in tape and reel DS39612B-page 393 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 10/20/04 DS39612B-page 394 2005 Microchip Technology Inc.