@ TL input and outputs @ Delays stable and precise @ 8-pin DIP package @ Leads - thru-hole, J, Gull Wing or Tucked @ Available in delays from 10 to 500ns @ Output and four (4) taps - each isolated and with 10 TL fan-out capacity @ Fast rise time on all outputs design notes The "DIP Series" Logic Delay Modules developed by Engineered Components Company have been designed to provide precise tapped delays with required driving and pick-off circuitry contained in a single 14-pin DIP package compatible with FAST and Schottky TL circuits. These logic delay modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements, The MTBF on these modules, when calculated par MIL-HDBK-217 fara 50C ground fixed environment, is in excess of 2 million hours. Module design includes compensation for propagation delays and incorporates internal termination atthe output; no additional exter- nal components are needed to obtain the desired delay. The FXLDM-TTLisofferedin27 delays from 15to 1000ns witheach module incorporating total output and nine (9) taps. Delay tolerances are maintained as shown in the accompanying part number table, when tested under the Test Conditions shown. Delay time is 2 i engineered components company low profile TL COMPATIBLE 10-TAP measured at the +1.5 level an the leading edge. Rise time for all modules is 4ns maximum when measured fram 0.8 ta 2.0V. Temperature coefficient of delay is approximately +400 pepm"C over the operating temperature range of Oto +70C. These modules accept either logic "1* or logic "0" inputs and reproduce the logic at the output without inversion, The delay modules are intended primarily for use with positive going pulses and are calibrated to the tolerances shawn in the table on rising edge delay: where best accuracy is desired in appli- cations using falling edge timing, it is recommended that a special unit be calibrated for the specific application, Each module has the capability of driving up ta 20 Schottky T?L loads with a maximum of 10 loads on any one tap. These "DIP Series" modules are packaged in a 14-pin DIP housing, molded of flame-proof Dially| Phthalate per MIL-M-14, Type SDG-F, and are fully encapsulated in epoxy resin. Thru- hole, J, Gull Wing or Tucked Lead configurations are available on these modules (see Part Number Table note ta specify). Leads meet the solderability requirements of MIL-STD-202, Method 208, Corner standoffs on the housing of the thru-hole lead version and lead design of the surface mount versions provide pasitive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of salder-flux residues far improved reliability. Marking consists of manufacturer's nama, logo (EC*), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the perma- nancy of identification required by MIL-STD-202, Method 215. 3580 Sacramento Drive, P.O. Box 8121, San Luis Obispo, CA 93403-8121 Phone: (805) 544-3800 MECHANICAL DETAIL IS SHOWN BELOW Pin No. Boo 4613 12 1) WoO a Pin Ho. v2 4 6 8 OUT @ FXLDM- re 60 ~ ee [ _ a 130 5.00 L. aon Tele #0 TYP oog0g00a 6 at soesties Seemann | ie 2% jooo oo 6 ,. 3 *Thru-hole Lead a oo 20 TP a0 YP oa = }+-.100 Tr ag 2 x al | | ia iba TYP. *Gull Wing Lead po | 2 TYR J a a = : Feet | _ eee *Tucked Lead PART NUMBER TABLE Suffix Part Number with G (for Gull Wing Lead), J (for J Lead) , F (for Thru-hole Lead) or T (for Tucked Lead). Examples: FALDM-TTL-50G (Gull Wing), FXLOM-TTL-70J (J Lead), FXLOM-TTL-80F (Thru-hole Lead) or FXLOM- TTL-90T (Tucked Lead). BLOCK DIAGRAM IS SHOWN BELOW Woo TaP 2? TAP 4 TAP 6 TAP & OUT 14 13 2 1 ee J I ~*~ x INPUT DELAY LINE WITH I DRIVER TL PICKOFF | ! 1 l ! 1 2 3 4 5 6 7 INFUT TAP 1 TAP 3 TAPS TAP? TAP 9 GROUND TEST CONDITIONS 1. All measurements are made at 25C, 2. Veo supply voltage is maintained at 5.0 DC. 3. All units are tested using a Schottky: toggle-type positive input pulse and one Schottky load at the output being tested. Input pulse width used is 5 to 10ns longer than delay of module under test; spacing between pulses (falling edge to rising edge) is threa times the pulse widih used. OPERATING SPECIFICATIONS *Voco supply voltage: . we ee Vee supply current: Constant "0" in 4, 4.75 to 5.25V DC 4 | Constant yin 2 ee ee ee : a Logie 1 Input: Volaga.... a. BAe is 2V min.; Veco Max. Gurren sca ee een ween) &FV = 20UA max, 5.5 = imA max. Logic 0 Input: Vollage ...--22+-268 oeee es .OV max. Current... 2. seen eee eee) = =A Ma. Logic 1 Voltage out: . ww ee ee 2.7V min. Logic 0 Vollage out: ..... wee ee SV max. Operating temperature range: ..... Oto 70C Storage temperatures... 2... . 55 to +125C, * Delays increase or decrease approximately 2% for a respective increase or decrease of 5% in supply voltage, @ DELAYS AND TOLERANCES (in ns) PART NO. TAP 1 TAP 2 TAP 3 TAP 4 TAP 5 TAP 6 TAP 7 TAP 6 TAP 9 | OUTPUT FXLDM-TTL-15 Gal Tal B21 Sal 10 #1 lial 12 21 1321 1441 1521 FXLDM-TTL-19.5 621 T4521 Sai 10,5 21 12 #1 13.5 21 1541 16.5 21 18.41 19.541 FXLDM-TTL-24 621 821 10 1 W221 14 21 1621 18 21 20 21 22 #1 24 21 FXLDOM-TTL-28.5 621 84521 Wal 13.5 21 16 21 18.5 21 2121 23.5 21 26 21.5 28.5 21.5 FXLOM-TTL-33 621 Sxl W21 1521 16 21 2121 2421 27015 | DW2l5 | We5 FXLOM-TTL-42 Gal 10 +1 1421 181 22 21 2621.5 3215 | M215 38 22 42 =? FXLOM-TTL-50 S21 10 +1 15 #1 20 #1 26 215 30 21.5 35215 | 4022 45 22 SO a2 FXLDM-TTL-60 621 1241 18 +1 2421 3021.5 | 3621.5 42 +2 48 22 54 22 60 225 FXLOM-TTL-70 Tal 1441 2121 2021.5 3641.5 | 4222 49 42 56 22 Ge #2.5 70 +25 FXLDM-TTL-8o 82! 16 #1 2421 32 21.5 40 22 48 22 56 +2 64 22.5 Te 22.5 80 +3 FXLDM-TTL-& 921 18 #1 27215 | M25 | 4522 54 a? 63425 | 7222.5 | 8123 90 43 FXLDM-TTL: 100 1021 20 #1 3021.5 40 a2 50 a2 BO 22.5 70 22.6 60 23 9043 100 43 FXLDM-TTL-125 12.5 21 P5215 | 37.5 a2 50 22 62.5 22.5) 7542.5 B75 23 | 100 23 112.5 24] 125 24 FXLDM-TTL-150 1521 9021.5] 4542 60 22.5 75 a2.5 90 43 105 24 120 24 135 24 150 +5 FXLDM-TTL-175 7521 35 22 52.5 22 70 22.5 Or523 (105 44 1225 24 | 14025 157.545 |) 17545 FXLDM-TTL-200 20 21 40 22 6022.5 | 8023 100 43 120 +4 140 25 160 +5 18026 | 20026 FXLDM-TTL-250 25 21,5 50 a2 7522.5 | 10023 125 24 150 25. 175 25 200 #6 225 af 250 28 FXLDM-TTL-300 20 21.5 Ga 5 |) ad 120 24 150 #5 180 26 210 a7 240 27 270 28 300 28 FXLDM-TTL-350 35 21,5 T0225 | 105 24 140 25 175 25 210 27 245 2B 200 29 315 210 | 350211 FXLDM-TTL-400 40 22 6023 120 #4 160 25 200 #6 240 27 280 29 220210 | 0211 | 400212 FXLDOM-TTL-450 45 22 90 23 135 24 180 26 225 #7 270 28 BS 210 | 360211 | 405212 | 450214 FRLOM-TTL-5S00 50 22 100 23 15025 [20026 | 25048 300 +9 360211 [400212 | 450214 | 500215 FXLDM-TTL-600 6027.5 | 12024 180 +5 240 27 300 +8 360 +11 420213 [480215 | 540216 | 600 218 FXLOM-TTL-700 TO 22.5 | 14045 210 47 280 9 350211 [420213 490215 |560217 | 630219 | 700 #20 FXLOM-TTL-800 80 43 16045 | 24027 [320210 | 400412 [480215 560217 [640219 | 720220 | B00 220 FXLOM-TTL-900 90 43 18026 | 27028 | 360411 | 450414 1540 216 690219 [720220 | 810220 | 900 222 FXLDM-TTL-1000 | 10043 20046 | 30029 [400212 | 500215 600 218 700 220 | 800420 | 900 222 | 1000 222 @ All modules can be operated with a minimum input pulse width of 20% of full delay or Sns min and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested thal the module be evaluated under the Intended specific operating conditions, Special modules can be readily manulactured to improve accuracies and/or provide customer specified random delay times for specific applications. Catalog No. C/112092