TLC2934 3.3 V 130 MHZ VCO, PHASE FREQUENCY DETECTOR SLAS306 - NOVEMBER 2000 D D D D D D Voltage-Controlled Oscillator (VCO) - Ring Oscillator Using Only One External Biasing Resistor (RBIAS) Recommended Lock Frequency PW PACKAGE (TOP VIEW) LOGIC VDD SELECT VCO OUT FIN -A FIN -B PFD OUT LOGIC GND - 100 MHz to 130 MHz - (VDD = 3.3 V + 5%, TA = -20C to 75C) Phase-Frequency Detector (PFD) Includes a High-Speed Edge-Triggered Detector With Internal Charge Pump Independent VCO, PFD Power-Down Mode Thin Small-Outline Package (14 Terminal) Compatible Pin Assignment to TLC2932, TLC2933 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCO VDD RBIAS VCO IN VCO GND VCO INHIBIT PFD INHIBIT TEST description The TLC2934, a mixed signal IC designed for phase-locked-loop (PLL) systems, is composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The internal VCO is based on the TLC2932 and TLC2933s ring oscillator. It oscillates in wider frequency with lower supply voltage, and it has stable oscillating performance. The oscillation function, provided by only one external resistor connection, supplies bias to the VCI internal circuit. Oscillator range is covered from 10 MHz to 130 MHz with a 3.3-V supply voltage. The VCO has an inhibit function to stop oscillation and for the power-down mode. The internal PFD, a high-speed rising edge triggered type, has an internal charge pump with a high-impedance output buffer. The PFD detects phase difference between the reference frequency input and the signal frequency input from the VCO output through an external counter device. This functions the same as TLC2932 and TLC2933. The PFD also has the inhibit function for stop phase comparison and for power-down mode. block diagram TLC29341PW VCO f(OSC) Through or 1/2 Ring Oscillator Bias Control Bias Supply Control Voltage VCO INHIBIT Reference Input PFD OUT Ring Oscillator PFD Comparison Input PFD INHIBIT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLC2934 3.3 V 130 MHZ VCO, PHASE FREQUENCY DETECTOR SLAS306 - NOVEMBER 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION I Frequency signal inputs for PFD. The reference frequency signal (fREF-IN) and the VCO output signal through the external counter device are applied to these terminals. When the LPF design is the lag-lead filter (passive filter and noninverting), f(REF-IN) is input to FIN-A, and the VCO output signal is to FIN-B. GND terminal for the internal logic circuit FIN-A, FIN-B 4 5 LOGIC GND 7 LOGIC VDD 1 PFD INHIBIT 9 I PFD INHIBIT (power-down) control signal input terminal PFD OUT 6 O PFD output terminal. When PFD INHIBIT is high, PFD OUT is in the high-impedance state. RBIAS 13 I Bias resistor (RBIAS) terminal. Connect a resistor between VCO GND and this terminal to supply bias to internal VCO circuit. TLC2934 bias resistor connection is different from TLC2932 and TLC2933, where bias resistor RBIAS is connected to VCO VDD. SELECT 2 I 1/2 divider select terminal. L=through output, H=1/2 output. Power supply terminal for the internal logic circuit. This power supply terminal separates from VCO VDD to reduce cross-coupling between supplies. TEST 8 VCO GND 11 VCO OUT 3 O VCO output terminal. When VCO INHIBIT = high, VCO OUT is low. VCO INHIBIT 10 I VCO INHIBIT (power-down) control signal input terminal VCO IN VCO VDD 12 I VCO control voltage input terminal. Normally, The external LPF is connected to this terminal. 14 Test terminal. Use for production test. Tie to GND when in normal use. GND terminal for internal VCO Power supply terminal for the internal VCO circuit. This power supply terminal should be separate from LOGIC VDD to reduce cross-coupling between supplies. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage (each supply), VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Input voltage range (each input), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Input current (each input), II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output current (each output), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous total power dissipation at (or below) TA = 25_C (see Note 2), PD . . . . . . . . . . . . . . . . . . . 700 mW Operating free-air temperature range. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20C to 75C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. For operation above 25C free-air temperature, derate linearly at the rate of 5.6 mW/C 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC2934 3.3 V 130 MHZ VCO, PHASE FREQUENCY DETECTOR SLAS306 - NOVEMBER 2000 recommended operating conditions Supply voltage (each supply, VDD (see Notes 3 and 4) MIN TYP MAX UNIT 3.15 3.3 3.45 V VDD 2 mA MHz Input voltage (each input except for VCO IN, VI 0 Output current (each output), IO 0 VCO control voltage, VCO IN 0.5 Lock frequency (through output) Lock frequency (1/2 output) RBIAS = 1 k 36 VDD 130 RBIAS = 1.8 k 28 90 RBIAS = 2.4 k 26 80 RBIAS = 3.3 k 20 60 RBIAS = 1 k 18 65 RBIAS = 1.8 k 14 45 RBIAS = 2.4 k 13 40 RBIAS = 3.3 k V V MHz 10 30 Bias resistor, RBIAS 1.0 3.3 K Operating temperature range, TA -20 75 _C VCO IN voltage at VCO INHIBIT, V(CINH) (see Note 5) 0 0.5 V NOTES: 3. It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and separated from each other. 4. A bypass capacitor is placed as close as possible to each supply terminal. 5. For stable restart of VCO, VCOIN is 0 V when VCO INHIBIT is pulled down to GND level to disable the VCO INHIBIT function. And also, VCO IN should be 0 V when the operation will be started by supplying the power. electrical characteristics over recommended operating free-air temperature range, VDD=3.3 V (unless otherwise noted) VCO PARAMETER VOH VOL High-level output voltage VIH VIL II ZV(CO IN) IDD(INH) IDD(VCO) TEST CONDITIONS MIN TYP MAX UNIT 3.1 Low-level output voltage IOH = -2 mA IOL= 2 mA V High-level input voltage Logic signal input 2.3 Low-level input voltage Logic signal input 1.0 V Input current at TEST, VCO INHIBIT 1 A Input impedance at VCOIN VI = VDD or GND VCOIN = 1/2 VDD VCO supply current (inhibit) See Note 6 0.01 1 A VCO supply current See Note 7 10 15 mA 0.2 V V 10 M NOTES: 6. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited. 7. Current into VCO VDD, when VCOIN = 1/2 VDD, RBIAS = 1 k, VCO INHIBIT = GND, PFD is inhibited. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TLC2934 3.3 V 130 MHZ VCO, PHASE FREQUENCY DETECTOR SLAS306 - NOVEMBER 2000 electrical characteristics over recommended operating free-air temperature range, VDD=3.3 V (unless otherwise noted) (continued) VCO PARAMETER VOH VOL TEST CONDITIONS High-level output voltage IOH = -2 mA IOL = 2 mA Low-level output voltage IOZ High-impedance state output current VIH VIL High-level input voltage at FIN-A,B V(TO) CI Positive input threshold voltage at PFD INHIBIT Z(IN) IDD(PFD) Input impedance at FIN-A,B MIN TYP MAX 3.1 V PFD INHIBIT = high, VO = VDD or GND 0.2 V 1 A 2.3 V Low-level input voltage at FIN-A,B 1.0 1.0 Input capacitance at FIN-A,B 1.65 2.3 5 See Note 8 1.5 V V pF 10 PFD supply current UNIT M 6.0 mA NOTE 8: Current into LOGIC VDD, when FIN-A, FIN-B=50 MHz (VI(pp) = 3.3V, rectangular wave), Test=GND, no load, and VCO OUT is inhibited. VCO PARAMETER TEST CONDITIONS MIN MAX UNIT f(OSC) t(STB) Operating oscillation frequency RBIAS = 1 k 90 113 MHz Time to stable oscillation See Note 9 0.7 10 s tr tf Rise time CL = 15 pF, See Figure 3 1.7 5 ns Fall time CL = 15 pF, See Figure 3 1.1 4 ns f(duty) Duty cycle at VCO OUT RBIAS = 1.0 k, VCO IN = 1/2 VDD RBIAS=1.0k, VCO IN = 1/2 VDD, TA = -20C to 75C 50% 55% Temperature coefficient of oscillation frequency Supply voltage coefficient of oscillation frequency 67 TYP 45% RBIAS = 1 k, VCO IN = 1.65 V, VDD = 3.15 V to 3.45 V Jitter absolute RBIAS = 1 k, VCO IN = 1/2 VDD NOTE 9: Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited. 0.03 %/C 0.02 %/mV 50 ps PFD AC PARAMETER TEST CONDITIONS MIN TYP MAX Maximum operating frequency 15.3 40 ns tPHZ tPZL PFD output disable time from high level 15.5 40 ns PFD output enable time from low level 2.4 10 ns tPZH tr PFD output enable time from high level 2.5 10 ns Rise time CL=15 pF (see Figure 3) 1.2 5 ns tf Fall time CL=15 pF (see Figure 3) 0.7 5 ns 4 50 UNIT fMAX tPLZ PFD output disable time from low level See Figures 4 and 5 and Table 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MHz TLC2934 3.3 V 130 MHZ VCO, PHASE FREQUENCY DETECTOR SLAS306 - NOVEMBER 2000 PARAMETER MEASUREMENT INFORMATION 90% 90% VCO OUT 10% 10% tr tf Figure 1. VCO Output Voltage Waveform FIN- A FIN- B VDD VDD GND GND VDD VDD GND GND VDD PFD INHIBIT VDD 50% 50% GND tr PFD OUT 10% 90% 50% GND tPHZ tPLZ tf VOH 50% 90% 50% 10% GND VDD 50% VOL tPZL tPZH (a) OUTPUT PULLDOWN (b) OUTPUT PULLUP (see Figure 3 and PFD Output Test Conditions Table) FIN-A and FIN-B are for reference phase only, not for timing. Figure 2. PFD Output Voltage Waveform PFD Output Test Conditions PARAMETER RL CL tPZH tPHZ tr tPZL tPLZ tf SL Open S2 S1 RL Close DUT 1 k VDD Test Point PFD OUT 15 pF Close CL Open S2 Figure 3. PFD Output Test Condition POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TLC2934 3.3 V 130 MHZ VCO, PHASE FREQUENCY DETECTOR SLAS306 - NOVEMBER 2000 TYPICAL CHARACTERISTICS VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE 120 -20 C VDD = 3.3 V, RBIAS = 1 k, 180 25 C 160 140 75 C 120 100 80 60 40 20 f osc- VCO Oscillation Frequency - MHz f osc- VCO Oscillation Frequency - MHz 200 VDD = 3.3 V, RBIAS = 2.4 k, 100 0 80 75 C 60 40 20 0.5 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 VCO IN - VCO Control Voltage - V VCO IN - VCO Control Voltage - V Figure 4 95 -20 C 25 C 75 C 60 40 20 0.5 1 1.5 2 2.5 3 f osc - VCO Oscillation Frequency - MHz f osc- VCO Oscillation Frequency - MHz VDD = 3.3 V, RBIAS = 3.3 k, VCO OSCILLATION FREQUENCY vs VCO SUPPLY VOLTAGE 80 0 RBIAS = 1 k VCOIN = 1.65 V, TA = 25 C 92.5 90 87.5 85 3.15 VCO IN - VCO Control Voltage - V Figure 6 6 3 Figure 5 VCO OSCILLATION FREQUENCY vs VCO CONTROL VOLTAGE 0 25 C 0 0 100 -20 C 3.30 VDD - VCO Supply Voltage - V Figure 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3.45 PACKAGE OPTION ADDENDUM www.ti.com 2-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLC2934IPW NRND TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2934IPWG4 NRND TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2934IPWR NRND TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC2934IPWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC2934IPWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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