1
Data sheet acquired from Harris Semiconductor
SCHS191A
Features
• Buffered Inputs
• Asynchronous Parallel Load
• Typical fMAX = 60MHz at VCC =5V,C
L= 15pF, TA=25
oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC597 and CD74HCT597 are high-speed silicon gate
CMOS devices that are pin-compatible with the LSTTL 597
devices. Each device consists of an 8-flip-flop input register
and an 8-bit parallel-in/serial-in, serial-out shift register. Each
register is controlled by its own clock. A “low” on the parallel
load input (PL) shifts parallel stored data asynchronously into
the shift register. A “low” master input (MR) clears the shift
register. Serial input data can also be synchronously shifted
through the shift register when PL is high.
Pinout
CD54HC597
(CERDIP)
CD74HC597, CD74HCT597
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD54HC597F3A -55 to 125 16 Ld CERDIP
CD74HC597E -55 to 125 16 Ld PDIP
CD74HC597M -55 to 125 16 Ld SOIC
CD74HCT597E -55 to 125 16 Ld PDIP
CD74HCT597M -55 to 125 16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local TI sales office or
customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D1
D2
D3
D4
D5
D6
GND
D7
VCC
DS
PL
STCP
SHCP
MR
Q7
D0
January 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
CD54/74HC597,
CD74HCT597
High Speed CMOS Logic
8-Bit Shift Register with Input Storage
[ /Title
(CD74
HC597
,
CD74
HCT59
7)
/
Sub-
j
ect
(High
Speed
CMOS
2
Functional Diagram
9
1
2
3
4
6
12
7
5
D1
D2
D3
D4
D5
D6
D7
STCP
Q7
11
13
10
15 14
D0
DS
SHCP
PL
MR
8 F/F
STORAGE
REG.
8-BIT
SHIFT
REG.
PARALLEL
DATA
INPUTS
FUNCTION TABLE
STCP SHCP PL MR FUNCTION
↑X X X Data Loaded to Input Flip-Flops
↑X L H Data Loaded from Inputs to Shift Register
No Clock Edge X L H Data Transferred from Input Flip-Flops to Shift Register
X X L L Invalid Logic, State of Shift Register Indeterminate when
Signals Removed
X X H L Shift Register Cleared
X↑H H Shift Register Clocked Qn = Qn-1, Q0 = DS
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High CP Level
CD54/74HC597, CD74HCT597
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54/74HC597, CD74HCT597
4
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
HCT Input Loading Table
INPUT UNIT LOADS
DS0.2
Dn0.3
PL, MR 1.5
STCP, SHCP 1.5
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 360µA max. at 25oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
SHCP Frequency fMAX 2 6 - - 5 - - 4 - - MHz
4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz
CD54/74HC597, CD74HCT597
5
SHCP Pulse Width tW2 80 - - 100 - - 120 - - ns
4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns
STCP Pulse Width tW260--75- -90--ns
4.5 12 - - 15 - - 18 - - ns
610--13- -15--ns
MR Pulse Width tW2 80 - - 100 - - 120 - - ns
4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns
PL Pulse Width tW2 70 - - 90 - - 105 - - ns
4.5 14 - - 18 - - 21 - - ns
612--15- -18--ns
STCP to SHCP Setup
Time tSU 2 100 - - 125 - - 150 - - ns
4.5 20 - - 25 - - 30 - - ns
617--21- -26--ns
DS to SHCP Setup Time
Dn to STCP Setup Time tSU 250- -65- -75--ns
4.5 10 - - 13 - - 15 - - ns
6 9 - - 11 - - 13 - - ns
STCP to SHCP Setup
Time tH20--0--0--ns
4.5 0 - - 0 - - 0 - - ns
60--0--0--ns
DS to SHCP Hold Time
Dn to STCP Hold Time tH23--3--3--ns
4.5 3 - - 3 - - 3 - - ns
63--3--3--ns
MR to SHCP Removal
Time tREM 23--3--3--ns
4.5 3 - - 3 - - 3 - - ns
63--3--3--ns
HCT TYPES
SHCP Frequency fMAX 4.5 25 - - 20 - - 16 - - MHz
SHCP Pulse Width tW4.5 20 - - 25 - - 30 - - ns
STCP Pulse Width tW4.5 13 - - 16 - - 20 - - ns
MR Pulse Width tW4.5 18 - - 23 - - 27 - - ns
PL Pulse Width tW4.5 16 - - 20 - - 24 - - ns
STCP to SHCP Setup
Time tSU 4.5 24 - - 30 - - 36 - - ns
Prerequisite for Switching Specifications (Continued)
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CD54/74HC597, CD74HCT597
6
DS to SHCP Setup Time
Dn to STCP Setup Time tH4.5 10 - - 13 - - 15 - - ns
STCP to SHCP Hold Time tH4.5 0 - - 0 - - 0 - - ns
DS to SHCP Hold Time
Dn to STCP Hold Time tH4.5 3 - - 3 - - 3 - - ns
MR to SHCP Removal
Time tREM 4.5 10 - - 13 - - 15 - - ns
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oCto85
oC -55oC to 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns
SHCP to Q7 4.5 - - 35 - 44 - 53 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns
PL to Q7 tPLH, tPHL CL= 50pF 2 - - 200 - 250 - 300 ns
4.5 - - 40 - 50 - 60 ns
CL=15pF 5 - 17 - - - - - ns
CL= 50pF 6 - - 34 - 43 - 51 ns
STCP to Q7 tPLH, tPHL CL= 50pF 2 - - 240 - 300 - 360 ns
4.5 - - 48 - 60 - 72 ns
CL=15pF 5 - 20 - - - - - ns
CL= 50pF 6 - - 41 - 51 - 61 ns
MR to Q7 tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns
4.5 - - 35 - 44 - 53 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns
Output Transition Time tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CICL= 50pF - - - 10 - 10 - 10 pF
Power Dissipation
Capacitance, (Notes 4, 5) CPD - 5 - 13.5 - - - - - pF
HCT
Propagation Delay tPLH, tPHL
SHCP to Q7 CL= 50pF 4.5 - - 38 - 48 - 57 ns
CL= 15pF 5 - 16 - - - - - ns
PL to Q7 tPLH, tPHL CL= 50pF 4.5 - - 48 60 72 ns
CL= 15pF 5 - 20 - - - - - ns
STCP to Q7 tPLH, tPHL CL= 50pF 4.5 - - 56 70 84 ns
CL= 15pF 5 - 23 - - - - - ns
Prerequisite for Switching Specifications (Continued)
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CD54/74HC597, CD74HCT597
7
MR to Q7 tPLH, tPHL CL= 50pF 4.5 - - 44 - 55 - 66 ns
CL= 15pF 5 - 18 - - - - - ns
Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CICL= 50pF - - - 10 - 10 - 10 pF
Power Dissipation
Capacitance, (Notes 4, 5) CPD - 5 - 18.5 - - - - - pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD=C
PD VCC2fi+Σ(CLVCC2fo) where: fi= Input Frequency, fo= Output Frequency, CL= Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oCto85
oC -55oC to 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54/74HC597, CD74HCT597
8
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
Test Circuits and Waveforms
(Continued)
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54/74HC597, CD74HCT597
9
Timing Diagram
SHIFT CLOCK
SHCP
SERIAL DATE
DS
MASTER RESET
MR
PARALLEL LOAD
PL
STORAGE CLOCK
STCP
D0
D1
D2
D3
D4
D5
D6
D7
Q7
PARALLEL
DATA
INPUTS
RESET
SHIFT
REGISTER SERIAL
SHIFT
L
H
H
H
H
H
HHHH H H H HH
L
L
LL L L L L LLL L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
L
H
LOAD
FLIP-FLOPS LOAD
FLIP-FLOPS
PARALLEL LOAD
SHIFT REGISTER PARALLEL LOAD
SHIFT REGISTER PARALLEL LOAD FLIP-FLOPS
AND SHIFT REGISTER
SERIAL
SHIFT SERIAL
SHIFT SERIAL
SHIFT
CD54/74HC597, CD74HCT597
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated