HV9308 HV9408 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs Ordering Information Package Options Device Recommended Operating VPP max 44 J-Lead Quad Plastic Chip Carrier Dice in Waffle Pack Chip Carrier HV9308 80V HV9308PJ HV9308X HV9408 80V HV9408PJ HV9408X Features General Description Processed with HVCMOS(R) technology The HV93 and HV94 are low voltage serial to high voltage parallel converters with push-pull outputs. These devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application requiring multiple output high voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum fluorescent, or large matrix LCD displays. Low power level shifting Shift register speed 8MHz Latched data outputs 5V CMOS compatible inputs Forward and reverse shifting options These devices consist of a 32-bit shift register, 32 latches, and control logic to enable outputs. HVOUT1 is connected to the first stage of the shift register through the Output Enable logic. Data is shifted through the shift register on the low to high transition of the clock. The HV94 shifts in the counterclockwise direction when viewed from the top of the package and the HV93 shifts in the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (32). Operation of the shift register is not affected by the LE (latch enable) or the OE (output enable) inputs. Transfer of data from the shift register to the latch occurs when the LE input is high. The data in the latch is retained when LE is low. Diode to VPP allows efficient power recovery 44-lead ceramic surface mount package Hi-Rel processing available Absolute Maximum Ratings1 Supply voltage, VDD2 -0.5V to +7V Supply voltage, VPP2 -0.5V to +90V Logic input Ground levels2 current3 Continuous total power dissipation4 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds -0.5 to VDD + 0.5V 1.5A 1200mW -40C to 85C -65C to +150C 260C Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to GND1. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25C ambient derate linearly to maximum operating temperature at 20mW/C. 02/96/022 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV9308/HV9408 Electrical Characteristics (VPP = 60V, VDD = 5V, TA =25C) DC Characteristics Symbol Parameter Min Max Units Conditions IPP VPP Supply Current 100 A HVOUT outputs HIGH to LOW IDDQ IDD Supply Current (Quiescent) 100 A All inputs = VDD or GND IDD IDD Supply Current (Operating) 15 mA VDD = VDD max, fCLK = 8 MHz VOH (Data) Shift Register Output Voltage VOL (Data) Shift Register Output Voltage IIH VDD-0.5 V IO = -100A 0.5 V IO = 100A Current Leakage, any input 1.0 A Input = VDD IIL Current Leakage, any input -1.0 A Input = GND VOC HVOUT Output Clamp Diode Voltage -1.5 V IOC = -5mA VOH HVOUT Output when Sourcing V IOH = -20mA, 0 to 70C VOL HVOUT Output when Sinking 4.0 V IOL = 5mA, 0 to 70C Max Units Conditions 8.0 MHz 52 AC Characteristics Symbol Parameter Min fCLK Clock Frequency tWL or tWH Clock width, HIGH or LOW 62 ns tSU Setup time before CLK rises 25 ns tH Hold time after CLK rises 10 ns tDLH (Data) Data Output Delay after L to H CLK 110 ns CL = 15pF tDHL (Data) Data Output Delay after H to L CLK 110 ns CL = 15pF tDLE LE Delay after L to H CLK 50 ns tWLE Width of LE Pulse 50 ns tSLE LE Setup Time before L to H CLK 50 ns tON Delay from LE to HVOUT, L to H 500 ns tOFF Delay from LE to HVOUT, H to L 500 ns Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic Voltage Supply 4.5 5.5 V VPP High Voltage Supply 8.0 80 V VIH Input HIGH Voltage VDD-0.5 VDD V VIL Input LOW Voltage 0 0.5 V fCLK Clock Frequency 0 8.0 MHz TA Operating Free-Air Temperature Plastic -40 +85 C Ceramic -55 +125 C Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. The VPP should not drop below VDD during operations. 2 HV9308/HV9408 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input HVOUT GND GND GND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms VIH Data Input 50% Data Valid 50% VIL tSU tH VIH Clock 50% 50% 50% tWL 50% VIL tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL Latch Enable VIH 50% 50% VOL tDLE tWLE tSLE 90% 10% HVOUT w/ S/R LOW VOH VOL tOFF HVOUT w/ S/R HIGH 10% tON 3 90% VOH VOL HV9308/HV9408 Functional Block Diagram Output Enable Latch Enable VDD Data Input HVOUT 1 Clock HVOUT 2 32 bit Static Shift Register 32 Latches * * * 32 Outputs Total * * * HVOUT 31 Data Out HVOUT 32 Function Tables Data Input CLK* H H L L X * Data Output No No Change = LOW-to-HIGH level transition Data Input LE OE HVOUT Output X X L All HVOUT = LOW X L H Previous Latched Data H H H H L H H L 4 HV9308/HV9408 Pin Configuration Package Outline HV93 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 17 HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Data Out N/C N/C N/C Clock 39 38 37 36 35 34 33 32 31 30 29 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function GND VPP VDD Latch Enable Data In Output Enable N/C HVOUT 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 HVOUT 23 HVOUT 22 HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function GND VPP VDD Latch Enable Data In Output Enable N/C HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10 HVOUT 11 HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15 40 28 41 27 42 26 43 25 44 24 1 23 2 22 3 21 4 20 5 19 6 18 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin J-Lead Package HV94 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 Data Out N/C N/C N/C Clock 02/06//02 (c)2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 5 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com Package Outline 44-Lead PLCC Package Outline (PJ) D D1 1 .048/.042 x 45O 6 .150 MAX .056/.042 x 45O 40 Note 1 (Index Area) .075 MAX E1 E Note 2 0.20max 3 Places Top View Side View View B A Base Plane A2 .020 MIN Seating Plane e A1 b Side View View B Note: 1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional. Symbol Dimension (inches) A A1 A2 b D D1 E E1 MIN .165 .090 .062 .013 .685 .650 .685 .650 NOM .172 .105 - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .695 .656 .695 .656 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale. Doc. #: DSPD-44PLCCPJ B041807 e .050 BSC