1
Ordering Information
Device Recommended 44 J-Lead Dice in
Operating Quad Plastic Waffle Pack
VPP max Chip Carrier Chip Carrier
HV9308 80V HV9308PJ HV9308X
HV9408 80V HV9408PJ HV9408X
Features
❏Processed with HVCMOS® technology
❏Low power level shifting
❏Shift register speed 8MHz
❏Latched data outputs
❏5V CMOS compatible inputs
❏Forward and reverse shifting options
❏Diode to VPP allows efficient power recovery
❏44-lead ceramic surface mount package
❏Hi-Rel processing available
General Description
The HV93 and HV94 are low voltage serial to high voltage parallel
converters with push-pull outputs. These devices have been
designed for use as drivers for AC-electroluminescent displays.
They can also be used in any application requiring multiple output
high voltage current sourcing and sinking capabilities such as
driving plasma panels, vacuum fluorescent, or large matrix LCD
displays.
These devices consist of a 32-bit shift register, 32 latches, and
control logic to enable outputs. HVOUT1 is connected to the first
stage of the shift register through the Output Enable logic. Data is
shifted through the shift register on the low to high transition of the
clock. The HV94 shifts in the counterclockwise direction when
viewed from the top of the package and the HV93 shifts in the
clockwise direction. A data output buffer is provided for cascading
devices. This output reflects the current status of the last bit of the
shift register (32). Operation of the shift register is not affected by
the LE (latch enable) or the OE (output enable) inputs. Transfer
of data from the shift register to the latch occurs when the LE input
is high. The data in the latch is retained when LE is low.
Absolute Maximum Ratings1
Supply voltage, VDD2-0.5V to +7V
Supply voltage, VPP2-0.5V to +90V
Logic input levels2-0.5 to VDD + 0.5V
Ground current31.5A
Continuous total power dissipation41200mW
Operating temperature range -40°C to 85°C
Storage temperature range -65°C to +150°C
Lead temperature 1.6mm (1/16 inch) 260°C
from case for 10 seconds
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to GND1.
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C.
HV9308
HV9408
32-Channel Serial To Parallel Converter
With High Voltage Push-Pull Outputs
Package Options
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
2
HV9308/HV9408
Recommended Operating Conditions
Symbol Parameter Min Max Units
VDD Logic Voltage Supply 4.5 5.5 V
VPP High Voltage Supply 8.0 80 V
VIH Input HIGH Voltage VDD-0.5 VDD V
VIL Input LOW Voltage 0 0.5 V
fCLK Clock Frequency 0 8.0 MHz
TAOperating Free-Air Temperature Plastic -40 +85 °C
Ceramic -55 +125 °C
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply VPP.
Power-down sequence should be the reverse of the above.
The VPP should not drop below VDD during operations.
Electrical Characteristics (VPP = 60V, VDD = 5V, TA =25°C)
DC Characteristics
Symbol Parameter Min Max Units Conditions
IPP VPP Supply Current 100 µAHV
OUT outputs HIGH to LOW
IDDQ IDD Supply Current (Quiescent) 100 µAAll inputs = VDD or GND
IDD IDD Supply Current (Operating) 15 mA VDD = VDD max,
fCLK = 8 MHz
VOH (Data) Shift Register Output Voltage VDD-0.5 V IO = -100µA
VOL (Data) Shift Register Output Voltage 0.5 V IO = 100µA
IIH Current Leakage, any input 1.0 µAInput = VDD
IIL Current Leakage, any input -1.0 µAInput = GND
VOC HVOUT Output Clamp Diode Voltage -1.5 V IOC = -5mA
VOH HVOUT Output when Sourcing 52 V IOH = -20mA, 0 to 70°C
VOL HVOUT Output when Sinking 4.0 V IOL = 5mA, 0 to 70°C
AC Characteristics
Symbol Parameter Min Max Units Conditions
fCLK Clock Frequency 8.0 MHz
tWL or tWH Clock width, HIGH or LOW 62 ns
tSU Setup time before CLK rises 25 ns
tHHold time after CLK rises 10 ns
tDLH (Data) Data Output Delay after L to H CLK 110 ns CL = 15pF
tDHL (Data) Data Output Delay after H to L CLK 110 ns CL = 15pF
tDLE LE Delay after L to H CLK 50 ns
tWLE Width of LE Pulse 50 ns
tSLE LE Setup Time before L to H CLK 50 ns
tON Delay from LE to HVOUT, L to H 500 ns
tOFF Delay from LE to HVOUT, H to L 500 ns
3
HV9308/HV9408
Latch Enable
HVOUT
w/ S/R LOW
Data Valid50% 50%Data Input
Clock
Data Out
50% 50% 50%
tSU tH
tWL tWH
50%
50%
tDLH
tDHL
50%
tWLE
tDLE tSLE
50% 50%
tON
10%
HVOUT
w/ S/R HIGH
90%
90%
10%
tOFF
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
VIH
VOL
VOH
VOL
VOH
VOL
VDD
Input
GND
VPP
GND
Logic Inputs
GND
Data Out
Logic Data Output High Voltage Outputs
VDD
HVOUT
Input and Output Equivalent Circuits
Switching Waveforms
4
HV9308/HV9408
•
•
•
32 Outputs Total
•
•
•
Output Enable
Latch Enable
Clock
32 bit
Static Shift
Register
32 Latches
VDD
HVOUT 1
Data Out
Data Input
HVOUT 2
HVOUT 31
HVOUT 32
Functional Block Diagram
Function Tables
Data Input CLK* Data Output
HH
LL
XNo No Change
* = LOW-to-HIGH level transition
Data Input LE OE HVOUT Output
XXLAll HVOUT = LOW
XLHPrevious Latched Data
HHHH
LHHL
5
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
02/06//02
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
HV9308/HV9408
Pin Configuration Package Outline
HV93
44 Pin J-Lead Package
Pin Function Pin Function
1HV
OUT 17 23 GND
2HV
OUT 16 24 VPP
3HV
OUT 15 25 VDD
4HV
OUT 14 26 Latch Enable
5HV
OUT 13 27 Data In
6HV
OUT 12 28 Output Enable
7HV
OUT 11 29 N/C
8HV
OUT 10 30 HVOUT 32
9HV
OUT 931HV
OUT 31
10 HVOUT 832HV
OUT 30
11 HVOUT 733HV
OUT 29
12 HVOUT 634HV
OUT 28
13 HVOUT 535HV
OUT 27
14 HVOUT 436HV
OUT 26
15 HVOUT 337HV
OUT 25
16 HVOUT 238HV
OUT 24
17 HVOUT 139HV
OUT 23
18 Data Out 40 HVOUT 22
19 N/C 41 HVOUT 21
20 N/C 42 HVOUT 20
21 N/C 43 HVOUT 19
22 Clock 44 HVOUT 18
HV94
44 Pin J-Lead Package
Pin Function Pin Function
1HV
OUT 16 23 GND
2HV
OUT 17 24 VPP
3HV
OUT 18 25 VDD
4HV
OUT 19 26 Latch Enable
5HV
OUT 20 27 Data In
6HV
OUT 21 28 Output Enable
7HV
OUT 22 29 N/C
8HV
OUT 23 30 HVOUT 1
9HV
OUT 24 31 HVOUT 2
10 HVOUT 25 32 HVOUT 3
11 HVOUT 26 33 HVOUT 4
12 HVOUT 27 34 HVOUT 5
13 HVOUT 28 35 HVOUT 6
14 HVOUT 29 36 HVOUT 7
15 HVOUT 30 37 HVOUT 8
16 HVOUT 31 38 HVOUT 9
17 HVOUT 32 39 HVOUT 10
18 Data Out 40 HVOUT 11
19 N/C 41 HVOUT 12
20 N/C 42 HVOUT 13
21 N/C 43 HVOUT 14
22 Clock 44 HVOUT 15
6
40
41
42
43
44
1
2
3
4
5
39 38 37 36 35 34 33 32 31 30 29
18
28
27
26
25
24
23
22
21
20
19
7 8 9 10 11 12 13 14 15 16 17
top view
44-pin J-Lead Package
Package Outline
44-Lead PLCC Package Outline (PJ)
Doc. #: DSPD-44PLCCPJ
B041807
Symbol A A1 A2 b D D1 E E1 e
Dimension
(inches)
MIN .165 .090 .062 .013 .685 .650 .685 .650
.050
BSC
NOM .172 .105 - - .690 .653 .690 .653
MAX .180 .120 .083 .021 .695 .656 .695 .656
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
Drawings are not to scale.
Note:
1. A Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.
2. Exact shape of this feature is optional.
.150 MAX
.048/.042
x 45O
1
.075 MAX
640
D
D1
E1 E
Top View
Side View
View B
AA2
A1
Seating
Plane
e
b
Note 1
(Index Area)
.056/.042
x 45O
0.20max
3 Places
Base
Plane
.020 MIN
Side View
View B
Note 2
