GN4121 x1 Lane PCI Express to Local Bridge Data Sheet GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 www.gennum.com 1 of 30 Proprietary & Confidential Revision History Version 0 ECR 152184 Date June 2009 Changes and Modifications Became Data Sheet. Added LCLK_MODE[3] to Table 3-12. A 150817 May 2009 New document. Contents 1. Introduction.....................................................................................................................................................3 1.1 Features ...............................................................................................................................................3 1.2 Live on Power-up ..............................................................................................................................4 1.3 FPGA On-the-Fly Configuration Loader ...................................................................................5 1.4 Local Bus Interface ...........................................................................................................................5 1.5 Virtual Channel Support ................................................................................................................6 1.6 PCI Express Application Layer ....................................................................................................6 1.7 Interrupt Controller .........................................................................................................................6 1.8 2-Wire Serial Controller .................................................................................................................6 1.9 Data Sheet Usage ..............................................................................................................................6 1.10 Getting Help from Gennum ........................................................................................................7 1.11 Getting Answers to PCI Express Related Questions ...........................................................7 2. Pin Descriptions .............................................................................................................................................8 2.1 Pin Assignments ................................................................................................................................8 2.2 Pin Descriptions ................................................................................................................................9 3. Electrical Characteristics ......................................................................................................................... 15 3.1 Absolute Maximum Ratings ....................................................................................................... 15 3.2 Operating Conditions ................................................................................................................... 15 3.3 DC Electrical Characteristics ..................................................................................................... 16 3.4 PCI Express Electrical Characteristics .................................................................................... 17 3.4.1 PCI Express Transmitter Characteristics ................................................................... 17 3.4.2 PCI Express Receiver Characteristics ......................................................................... 20 3.4.3 Local Bus Timing................................................................................................................ 21 3.4.4 Local Clocks' Pins Settings.............................................................................................. 23 4. Overview....................................................................................................................................................... 24 4.1 GN4121 Signals .............................................................................................................................. 25 5. Package & Ordering Information .......................................................................................................... 26 5.1 Package Dimensions ..................................................................................................................... 26 5.2 Packaging Data ............................................................................................................................... 27 5.3 Ordering Information ................................................................................................................... 27 GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 2 of 30 Proprietary & Confidential GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 1. Introduction For the past decade, PCI has been a dominant interconnect for both PC and embedded systems. With the shift to high-speed serial interfaces, PCI Express(R) is quickly replacing parallel PCI. As a leader in providing solutions for high-speed serial communications, Gennum has developed the GN412x family of PCI bridge controller components to complement FPGA devices. The GN4121 is specifically designed to take advantage of the architectural features of low-cost FPGA devices that do not have PCI Express capable SerDes on-chip. The result is a low-cost bridging solution for high-performance native PCI Express bridging. The GN4121 is a desirable companion to large FPGA devices, where the requirement for firmware upgrading and on-the-fly reconfiguration are required. The GN4121 is a single lane PCI Express to local bus bridge that is designed to work as a companion for FPGA devices to provide a complete bridging solution for general applications. In addition to a PCI Express compliant PHY interface, the GN4121 contains the link and transaction layers, and an applications interface that is ideally suited to FPGA interfacing using a small number of pins. Since the PCI Express transaction/link IP is hard-wired into the GN4121, there is no need to license PCIe IP. The level of integration and very low power operation of the GN4121 make it an ideal alternative to using a PIPE PHY, where IP licensing and the cost of FPGA resources and power consumption is unattractive by comparison. Using the GN4121, allows FPGA resources to be spent on what differentiates the product, rather than on implementing the PCI Express protocol. 1.1 Features * 1 Lane PCI Express interface Complies with PCI Express Base Specification 1.1 On-chip PHY, transaction, and link layer eliminates the cost of IP licensing One hardware virtual channel supported Payload size of up to 512 bytes with up to three outstanding transactions in each direction Supports 3x64-bit base address registers Provides flexible power management capability * Provides pin efficient local bus interface for easy attachment to popular low-cost FPGA devices Uses DDR SSTL I/O for high-speed data transfer (up to 500MB/s) GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 www.gennum.com 3 of 30 Proprietary & Confidential FPGA source code provided for 64-bit master/target read/write buses for easy user logic attachment Local bus may be operated asynchronously to the PCIe clock rate for power optimization * "Live" on power up On-chip type 0 PCI configuration space enables auto detection without FPGA activity On-chip extended configuration space supports power management, serial number, MSI, and PCIe capability registers * FPGA bitstream loader Allows easy configuration of the attached FPGA through PCIe Provides on-the-fly FPGA reconfiguration capability * 2-wire master/target Boot master mode allows PCI configuration space defaults to be loaded from a small EEPROM upon system reset General master mode allows attached 2-wire devices to be read/written Target mode allows internal registers to be accessed from an external circuit or processor A simplified block diagram of the GN4121 chip is shown in Figure 1-1. Figure 1-1: GN4121 with FPGA Simplified Block Diagram FPGA Pin Efficient Local Bus GN4121 Clock Boundary PCI Express Core TX Data Master DDR SSTL RX Data User Application IP Gennum Local Bus IP Target Streamlined Application Layer with Buffering Data Buffers Control SDR SSTL Local Clock Gen TL DLL PHY x1 Lane PCI Configuration and Extended Registers FPGA Cfg. Loader I 2C M/T GPIO Serial Programming Interface 1.2 Live on Power-up Since the GN4121 contains a complete type 0 PCI configuration space, it is live on power-up so that a plug-and-play BIOS can auto-detect it and enumerate it without an attached FPGA having to be configured. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 4 of 30 Proprietary & Confidential 1.3 FPGA On-the-Fly Configuration Loader An FPGA bitstream may be downloaded from the host system over PCIe to the attached FPGA using the on-chip FPGA configuration loader. This eliminates the expense of a dedicated FPGA ROM and makes on-the-fly reconfiguration and firmware upgrades simple. The ability to dynamically configure an attached FPGA over PCIe makes the GN4121 an ideal companion to all ranges of FPGA devices, including large SerDes capable devices, that require reconfiguration or firmware upgrades over PCIe. 1.4 Local Bus Interface The local bus interface uses a combination of single and dual data rate SSTL I/O to accomplish very high data rates in the fewest possible pins. A singe data rate clock is used for SSTL control signals and separate dual data rate source synchronous clocking is used for the DDR SSTL data. The SDR control signals operate at up to 125MHz and the DDR I/O operate at up to 250MT/s across 16 bits using a 125MHz DDR clock. This provides 500MB/s in each direction. The local bus may operate asynchronously from the PCI Express rate. In order to save power, the local bus clock can operate at the lowest possible rate required by an application. The local bus protocol facilitates four types of transactions: * PCIe-to-Local Target Writes: A PCIe agent (such as the host processor/root complex) writes data to the local bus. * PCIe-to-Local Target Reads: A PCIe agent reads data from the local bus. Reads are split into a request phase (address phase) and a completion phase (data phase). * Local-to-PCIe Master Writes: The attached FPGA writes data to a PCIe device (such as host memory via a root complex). * Local-to-PCIe Master Reads: The attached FPGA reads data from a PCIe device. The PCIe-to-Local transactions would typical involve a target controller implemented in the FPGA. Local-to-PCIe Master transactions allow a DMA controller in the FPGA to access PCI Express devices. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 5 of 30 Proprietary & Confidential 1.5 Virtual Channel Support The GN4121 has one virtual channel that support the eight PCIe defined traffic classes. 1.6 PCI Express Application Layer The on-chip applications layer transfers data between the PCI Express port and an attached FPGA using the local bus interface. It provides a mechanism to access internal registers through configuration space access and through one of the Base Address Registers (BAR4). The applications layer supports the transmission of message signalled interrupts. 1.7 Interrupt Controller A flexible interrupt controller automatically generates PCIe message signalled interrupts from either external pins (GPIO pins) or internally generated interrupt sources. The interrupt controller can route any interrupt source to up to four GPIO pins. 1.8 2-Wire Serial Controller An on-chip I2C compatible controller provides both a master and target mode. After device reset, default configuration register values, such as Subsystem Vendor ID and BAR sizes, can be automatically loaded from a small serial EEPROM. After initialization, an external 2-wire master can access on-chip registers to read/write them. 1.9 Data Sheet Usage The GN4121 Data Sheet includes detailed specifications on GN4121 device. However, there are other complementary documents to assist designers available on the Gennum Web site: www.gennum.com/mygennum. A complete set of documentation includes the following: * GN4121 Data Sheet (this document) * GN412x PCI Express Family Reference Manual (Document ID: 52624), which provides the details on functionality and the register map associated with the GN412x family of chips * GN4121 Master List of Documents & Electronic Files (Document ID: 52571), which provides a summary of the content of the documentation & electronic files, to help navigate the content on MyGennum * Reference Design Kit (RDK) board and the asssociated documentation Following chapters detail the specifications of the GN4121: * 2. Pin Descriptions * 3. Electrical Characteristics * 5. Package & Ordering Information GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 6 of 30 Proprietary & Confidential Before finalizing a system design based on the GN4121, please contact Gennum to verify that you have the most recent specifications. Gennum is constantly trying to improve the quality of its product documentation. If you have any questions or comments, please contact Gennum Technical Support. 1.10 Getting Help from Gennum For technical support, contact Gennum by telephone or e-mail. E-mail ensures the quickest response. The most up-to-date technical support information is also posted on the Gennum website. E-mail: vbapps@gennum.com. 1.11 Getting Answers to PCI Express Related Questions This data sheet assumes a basic understanding of the PCI Express Specification. If you are looking for a copy of the specification please contact the PCI Special Interest group at 503-619-0569 or visit their Web site at: http://www.pcisig.com. If you are not familiar with the PCI Express specification, a good place to start is by reading one of several books on the subject. One of the most popular is PCI Express System Architecture written by Tom Shanley, Don Anderson, and Ravi Budruk (published by MindShare Inc.). GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 7 of 30 Proprietary & Confidential 2. Pin Descriptions 2.1 Pin Assignments Figure 2-1: GN4121 Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A VSS_ PCIE PERn VSS_ PCIE DBG0 DBG7 GPIO15 GPIO9 SPRI_CLK TDI GPIO7 GPIO6 SPRI_ DONE GPIO4 TDO PLL_TEST _OUT VSS A B VDD_ PCIE PERp NC DBG2 DBG6 GPIO13 GPIO14 RSTIN GPIO8 SPRI_ DATAOUT SCLK TRST SPRI_XI_ SWAP SPRI_ STATUS VSS L2P_ DATA15 B C PETp VSS_ PCIE VDD_ PCIE VSS DBG5 DBG1 GPIO12 GPIO10 RSTOUT 33 GPIO2 SPRI_ CONFIG SDATA LB_REF_ CLK_MO VSS L2P_ DATA7 L2P_ DATA14 C D PETn VSS_ PCIE VDD_ PCIE VSS VDDC SCAN_EN DBG3 VDDC GPIO3 NC GPIO1 LB_REF_ CLK_MI VDDC NC L2P_ DATA6 VDDC D E VDDP NC VSS_ PCIE VCCO33 EEPROM TEST_EN _EN DBG4 VCCO33 VCCO33 VDDC GPIO5 GPIO0 VDDC NC L2P_ DATA5 L2P_ DATA13 E F VTT_AB NC VSS_ PCIE NC VDDW VDDC GPIO11 VCCO33 VCCO33 TMS TCK VDDC VDDC L2P_RDY L2P_ DATA4 L2P_ DATA12 F G NC VSS_ PCIE VDDAUX VSS PECLKINp VSS VSS VSS VSS VSS VSS VDDC NC L2P_EDB L2P_ CLKn L2P_ CLKp G H NC VSS_ PCIE PCIE_ VDDA VDDC PECLKINn VSS VSS VSS VSS VSS VCCO18 VCCO18 VSS L2P_ DFRAME VDDC L2P_ VALID H J NC VSS_ PCIE PCIE_ VDDA VSS VSS NC VSS VSS VSS VSS VCCO18 VCCO18 VDDC NC L2P_ DATA3 L2P_ DATA11 J K NC VSS_ PCIE VSS VDDP VDDW LCLK_ MODE3 VSS VSS VSS VSS VSS VSS NC L_WR_ RDY VDDC L2P_ DATA10 K L VSS NC VSS_ PCIE LCLK_ MODE2 VDDC VDDC NC VCCO18 VCCO18 VDDC VSS VSS VDDC NC L2P_ DATA2 L2P_ DATA9 L M VTT_CD NC VSS_ PCIE LCLK_ MODE1 LCLK_ MODE0 VDDC VSS VCCO18 VCCO18 VDDC VSS VSS NC P_RD_ D_RDY L2P_ DATA1 VDDC M N NC VSS_ PCIE VDD_ PCIE NC VSS RX_ ERROR NC VDDC NC P_WR _RDY PLL_ AVSS TX_ ERROR L2P_ DATA0 L2P_ DATA8 N P NC VSS_ PCIE VDD_ PCIE VSS P2L_ DATA15 VDDC P2L_ VALID NC NC VC_ RDY VDDC LCLK VDDC RSTOUT 18 P R VDD_PCIE NC VSS VREF P2L_ DATA10 P2L_ DATA9 P2L_ DATA8 NC VSS LCLKn R T VSS_PCIE NC VSS_PCIE VDDC P2L_ DATA7 P2L_ DATA6 P2L_ DATA5 P2L_ DATA4 P2L_ DATA3 P2L_ DATA2 P2L_ DATA1 VDDC P2L_ DATA0 PLL_ AVDD NC VSS T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P_WR _REQ VDDC P2L_CLKp P2L_RDY P2L_ P2L_ P2L_ P2L_ P2L_ P2L_CLKn DATA14 DATA13 DATA12 DFRAME DATA11 3.3V GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 1.8V 1.2V 900mV 0V 8 of 30 Proprietary & Confidential 2.2 Pin Descriptions Table 2-1: GN4121 Pin Descriptions Group Global Pin No. B8 No. of Pins 1 Pin Name RSTIN I/O I Description Global Asynchronous Reset (Active LOW). LVCMOS, 3.3V, input, hysteresis. C9 1 RSTOUT33 O Reset Output; 3.3V (Active LOW). 3.3 V LVCMOS, totem-pole. D12 1 LB_REF_CLK_MI I Local Bus Reference Clock Crystal or Oscillator Input. C13 1 LB_REF_CLK_MO O Local Bus Reference Clock Crystal feedback output. Functional mode only. H3, J3 2 PCIE_VDDA P Clock Reference Analog Supply. (1.2V) G5, H5 2 PECLKINp, PECLKINn I PCIe Reference Clock Signal. For a PCI Express add-in card, these signals should be driven by the card edge connector and AC coupled using 150nF capacitors. E5 1 EEPROM_EN I Used to report that EEPROM is present. (1 = present) LVCMOS, 3.3V, input. EEPROM_EN should be tied HIGH, to allow the internal GN4121 registers to load on power up from the EEPROM. Refer to Initialization from a 2-Wire EEPROM in the GN412x PCI Express Family Reference Manual on what is required for EEPROM boot up options. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 9 of 30 Proprietary & Confidential Group Global: Test Interface Pin No. A9 No. of Pins 1 Pin Name TDI I/O I Description JTAG Test Data Input. LVCMOS, 3.3V, input, pull-up. F10 1 TMS I JTAG Test Mode Select Input. LVCMOS, 3.3V, input, pull-up. F11 1 TCK I JTAG Test Clock. LVCMOS, 3.3V, input. B12 1 TRST I JTAG Test Reset. LVCMOS, 3.3V, input, hysteresis, pull-up. A14 1 TDO O JTAG Test Data Output. LVTTL, 3.3V, output, 6mA, tristate. D6 1 SCAN_EN I Scan Enable (Tied LOW for normal operations). LVCMOS, 3.3V, input, pull-down. E6 1 TEST_EN I Test Mode Enable (Tied LOW for normal operations). LVCMOS, 3.3V, input, pull-down. A15 1 PLL_TEST_OUT I/O PLL Test Output (No connect for normal operations). LVCMOS, 3.3V, bidirectional, 4mA, tristate. Global: 2-Wire Interface B11 1 SCLK I/O Two-wire Clock port. LVCMOS, 3.3V, bidirectional, 4mA, tristate. C12 1 SDATA I/O Two-wire Data port. LVCMOS, 3.3V, bidirectional, 4mA, tristate. Global: General Purpose Interface A6, B7, B6, C7, F7, C8, A7, B9, A10, A11, E11, A13, D9, C10, D11, E12 16 Global: Debug Interface A5, B5, C5, E7, D7, B4, C6, A4 8 GPIO[15:0] I/O General Purpose Input/Output. LVCMOS, 3.3V, bidirectional, 4mA, tristate. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 DBG[7:0] I Debug Bus Port (Tied LOW for normal operations). LVCMOS, 3.3V, input, pull-down. 10 of 30 Proprietary & Confidential Group Global: Serial Programming Interface Pin No. A8 No. of Pins 1 Pin Name SPRI_CLK I/O I/O Description Serial Programming Interface (FPGA Configuration Loader). LVCMOS, 3.3V, bidirectional, 12mA, tristate. B10 1 SPRI_DATAOUT I/O Serial Programming Interface (FPGA Configuration Loader). LVCMOS, 3.3V, bidirectional, 12mA, tristate. C11 1 SPRI_CONFIG I/O Serial Programming Interface (FPGA Configuration Loader). LVCMOS, 3.3V, bidirectional, 12mA, tristate. A12 1 SPRI_DONE I/O Serial Programming Interface (FPGA Configuration Loader). LVCMOS, 3.3V, bidirectional, 12mA, tristate. B13 1 SPRI_XI_SWAP I/O Serial Programming Interface (FPGA Configuration Loader). LVCMOS, 3.3V, bidirectional, 12mA, tristate. B14 1 SPRI_STATUS I/O Serial Programming Interface (FPGA Configuration Loader). LVCMOS, 3.3V, bidirectional, 12mA, tristate. PCI Express Link: PCIe x1 PHY interface A1, A3, C2, D2, E3, F3, G2, H2, J2, K2, L3, M3, N2, P2, T1, T3 16 VSS_PCIE G B1, C3, D3, N3, P3, R1 6 VDD_PCIE P G3 1 PHY VSS. PHY VDD. 1.2V (Core) VDDAUX P PHY VDDAUX. 1.2V F1 1 VTT_AB P PCIe PHY transmit termination lanes A/B. Driven to voltage VTT. 1.5V See Table 3-6. M1 1 VTT_CD P PCIe PHY transmit termination lanes C/D. Driven to voltage VTT. 1.5V See Table 3-6. PCI Express Link: PCIe Transmit [Output from the device] D1 PCI Express Link: PCIe Receive [Input to the device] A2 1 PETn O PCIe Transmit -Bus Lane A. CML C1 1 PETp O PCIe Transmit +Bus Lane A. CML 1 PERn I PCIe Receive -Bus Lane A. CML B2 1 GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 PERp I PCIe Receive +Bus Lane A. CML 11 of 30 Proprietary & Confidential Group Local Bus Pin No. P14, R16 No. of Pins 2 Pin Name LCLK, LCLKn I/O O Description Local Bus Clock. SSTL, 1.8V, differential K6, L4, M4, M5 4 LCLK_MODE[3:0] I Selects the clock mode. LVCMOS, 3.3V, input, pull-down. P16 1 RSTOUT18 O Reset Output; 1.8V (Active LOW). CMOS, 1.8V, output Local Bus: PCIe to Local [Inbound Data] P9 1 P2L_RDY I Rx Buffer Full Flag. SSTL, 1.8V, input. P5, R4, R5, R6, R9, R11, R12, R13, T5, T6, T7, T8, T9, T10, T11, T13 16 R7 1 P2L_DATA[15:0] O Parallel Receive Data. SSTL, 1.8V, output P2L_DFRAME O Receive Frame. SSTL, 1.8V, output P7 1 P2L_VALID O Receive Data Valid. SSTL, 1.8V, output P8, R8 Local Bus: Inbound Buffer Request/Status N9 2 1 P2L_CLKp, P2L_CLKn O P_WR_REQ O Receiver Source Synchronous Clock. SSTL, 1.8V, output, differential PCIe Write Request. SSTL, 1.8V, output N12 1 P_WR_RDY I PCIe Write Ready. SSTL, 1.8V, input. N6 1 RX_ERROR I Receive Error. SSTL, 1.8V, input. P12 1 VC_RDY O Virtual Channel Ready Status. This provides a VC_RDY output to indicate the DL_UP1 status of the Virtual Channel. This can be used to provide a synchronous reset to the external application in the event the Virtual Channel goes down e.g. hot reset initiated by PCIe host. SSTL, 1.8V, output GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 12 of 30 Proprietary & Confidential Group Local Bus: Local PCIe [Outbound Data] Pin No. No. of Pins B16, C16, E16, F16, J16, K16, L16, N16, C15, D15, E15, F15, J15, L15, M15, N15 16 H14 1 Pin Name L2P_DATA[15:0] I/O I Description Parallel Transmit Data. SSTL, 1.8V, input. L2P_DFRAME I Transmit Data Frame. SSTL, 1.8V, input. H16 1 L2P_VALID I Transmit Data Valid. SSTL, 1.8V, input. G14 1 L2P_EDB I End-of-Packet Bad Flag. When a packet is considered bad and is terminated with EDB. SSTL, 1.8V, input. G16, G15 Local Bus: Outbound Buffer Status F14 2 1 L2P_CLKp, L2P_CLKn I Transmitter Source Synchronous Clock. L2P_RDY O SSTL, 1.8V, input, differential. Tx Buffer Full Flag. SSTL, 1.8V, output K14 1 L_WR_RDY O Local-to-PCIe Write. SSTL, 1.8V, output M14 1 P_RD_D_RDY O PCIe-to-Local Read Response Data Ready. SSTL, 1.8V, output N14 1 TX_ERROR O Transmit Error. SSTL, 1.8V, output Power F5, K5 2 VDDW P 3.3V R10 1 VREF P 900mV reference voltage for SSTL I/O T14 1 PLL_AVDD P 1.2V PLL supply voltage D5, D8, D13, D16, E10, E13, F6, F12, F13, G12, H4, H15, J13, K15, L5, L6, L10, L13, M6, M10, M16, N8, N10, P6, P13, P15, T4, T12 28 VDDC P 1.2V core power E1, K4 2 VDDP P 3.3V H11, H12, J11, J12, L8, L9, M8, M9 8 VCCO18 P Power for 1.8V I/O E4, E8, E9, F8, F9 5 VCCO33 P Power for 3.3V I/O GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 13 of 30 Proprietary & Confidential Group Ground Pin No. N13 No. of Pins 1 Pin Name PLL_AVSS I/O G Description PLL Ground. This pin is internally connected to VSS and, for noise isolation, should not be connected to VSS externally. Refer to the Gullwing-x1 RDK schematics and PCB layout for proper implementation. No Connect A16, B15, C4, C14, D4, G4, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H13, J4, J5, J7, J8, J9, J10, K3, K7, K8, K9, K10, K11, K12, L1, L11, L12, M7, M11, M12, N5, P4, R3, R15, T16 43 VSS G Ground. B3, D10, D14, E2, E14, F2, F4, G1, G13, H1, J1, J6, J14, K1, K13, L2, L7, L14, M2, M13, N1, N4, N7, N11, P1, P10, P11, R2, R14, T2, T15 31 NC -- No Connect. 1. Data Link Layer indicates that a connection with the upstream devices has been established. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 14 of 30 Proprietary & Confidential 3. Electrical Characteristics 3.1 Absolute Maximum Ratings Table 3-1: Absolute Maximum Ratings Parameter Value Core Supply Voltage -0.5V to +1.8 VDC SSTL IO Supply Voltage -0.5V to +2.5 VDC LVCMOS IO Supply Voltage -0.5V to +4.6 VDC Input ESD Voltage (HBM) 2kV Storage Temperature Range -50C < Ts < 125C Solder Reflow Temperature 260C 3.2 Operating Conditions Table 3-2: Operating Conditions All electrical characteristics are valid over the range of these operating conditions, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Notes Core Supply Voltage on pins VDDC, VDD_PCIE, VDDAUX, PLL_AVDD, PCIE_VDDA VCORE - 1.14 1.2 1.26 V 5% SSTL IO Supply Voltage on pins VCCO18 VVCCO18 - 1.71 1.8 1.89 V 5% LVCMOS IO and 3.3V Core Supply Voltage: pins VCCO33, VDDW, VDDP VVCCO33 - 3.0 3.3 3.6 V 10% Operating Temperature Range TA Ambient 0 25 85 C GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 15 of 30 Proprietary & Confidential 3.3 DC Electrical Characteristics Table 3-3: DC Electrical Characteristics Power and current limits listed have been derived from design and characteristics data. They are not 100% tested in production. Parameter Symbol Conditions Min Typ Max Units Notes Power Consumption PD PCIe x1, LCLK=100MHz - 475 695 mW 1 Total Core Supply Current on pins VDDC, VDD_PCIE, VDDAUX, PLL_AVDD, PCIE_VDDA ICORE - - 702 - mA - SSTL IO Supply Current IVCCO18 - - 3204 - (See Note 3) mA - LVCMOS IO and 3.3V Core Supply Current: pins VCCO33, VDDW, VDDP IVCCO33 - - 405 - (See Note 3) mA - (See Note 3) 1. Data is based on an application circuit equivalent to that used on the GN4121 RDK board (Gullwing-x1), typical operating conditions, PCIe negotiated to 1 lane, default PCIe PHY settings, 100MHz local bus operation, and with concurrent data traffic at 75% bus utilization. Doesn't include power dissipated by components outside of the GN4121. 2. This information is intended to guide power supply design. Data is based on an application circuit equivalent to that used on the GN4121 RDK board (Gullwing-x1), typical operating conditions, 100MHz local bus operation, and with concurrent data traffic at 75% bus utilization. 3. Maximum supply current will vary greatly depending on the application circuit and device usage. A specific application's maximum current can be be predicted by measuring current under high temperature, high supply and full load conditions. To this resultant number, the following factors needed to be added: +25% for ICORE +35% for IVCCO18 +25% for IVCCO33 4. See Note 2. Based on use of 22-ohm serial termination and 51-ohm parallel termination in the application circuit. 5. See Note 2. Also includes current draw from an LDO used to power VTT_AB and VTT_CD. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 16 of 30 Proprietary & Confidential Table 3-4: DC Electrical Characteristics for LVCMOS Buffers Parameter Symbol Conditions Min Typ Max Units Notes High-level input voltage VIH - 2 - - V - Low-level input voltage VIL - - - 0.8 V - Input leakage current IL - - - 5 A - High-level output voltage VOH IOH = -100 A 2.8 - - V - Low-level output voltage VOL IOL = 100 A - - 0.2 V - Table 3-5: DC Electrical Characteristics for SSTL Buffers Parameter Symbol Conditions Min Typ Max Units Notes VREF input reference voltage VREF - 833 900 969 mV 1 SSTL termination voltage VTT - VREF-40 VREF VREF+40 mV 2 High-level input voltage (DC) VIH - VREF+125 - VVCCO18+ 300 mV - Low-level input voltage (DC) VIL - -300 - VREF-125 mV - High-level input voltage (AC) VIH - VREF+250 - - mV - Low-level input voltage (AC) VIL - - - VREF-250 mV - 1. Typically the value of VREF is expected to be 50% * VDDQ of the transmitting device. Peak to peak AC noise on VREF may not exceed +/- 2% of VREF. 2. The termination voltage VTT should track the reference voltage VREF. 3.4 PCI Express Electrical Characteristics 3.4.1 PCI Express Transmitter Characteristics Table 3-6: Transmitter Characteristics Symbol Description Min Typical Max Unit Voltage Parameters VTX-DIFF1 Output voltage compliance @ typical swing VTX-DIFFp (peak-to-peak, single ended) 400 500 600 mV VTX-DIFFpp (peak-to-peak, differential) 800 1000 1200 mV VTT Transmitter termination voltage 1.2 1.5 1.89 V VOL Low-level output voltage - VTT - 1.5 * VTX-DIFFp - V GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 17 of 30 Proprietary & Confidential Symbol Description Min Typical Max Unit VOH High-level output voltage - VTT - 0.5 * VTX-DIFFp - V VTX-DC-CM Transmit common-mode voltage 0 VTT - VTX-DIFFp 3.6 V VTX-CM-DCACTIVE- Absolute Delta of DC Common Mode Voltage During L0 and Electrical Idle. - - 100 mV VTX-DE-RATIO De-emphasized differential output voltage 0 -3.35 -7.96 dB2 VTX-IDLE-DIFFp Electric Idle differential peak voltage - - 20 mV VTX-RCV-DETECT Voltage change during Receive Detection - - 600 mV RLTX-DIFF Transmitter Differential Return loss 10 - - dB RLTX-CM Transmitter Common Mode Return loss 6 - - dB ZOSE Single-ended output impedance 40 50 60 ZTX-DIFF-DC DC Differential TX Impedance 80 100 120 TTX-RISE, TTX-FALL Rise / Fall time of TxP, TxN outputs .125 - UI Unit Interval 399.88 400 400.12 ps4 TTX-MAX-JITTER Transmitter total jitter (peak-to-peak) - - 0.305 UI TTX-EYE Minimum TX Eye Width (1 - TTX-MAX-JITTER) 0.70 - - UI TTX-EYE-MEDIAN-to-MAX- Maximum time between the jitter median and maximum deviation from the median - - 0.15 UI TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid electrical idle after sending an Electrical Idle ordered set - 4 6 ns TEIExit Time to exit Electrical Idle (L0s) state into L0 - 12 16 ns IDLEDELTA UI3 Jitter Parameters JITTER Timing Parameters 1. Measured with Vtt = 1.2V, PHY_CONTROL register bits HIDRV='0', LODRV='0' and DTX="0000"(1x). 2. The de-emphasis ratio is determined through the DEQ bits of the PHY_CONTROL register inside the GN4121. Typical value is based on recommended setting of the PHY_CONTROL register. 3. As measured between 20% and 80% points. 4. UI does not account for SSC dictated variations. 5. Measured using PCI Express Compliance Pattern. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 18 of 30 Proprietary & Confidential Figure 3-1: Typical Transition Signal Eye, De-emphasis Disabled, Default Drive Setting The eye diagram is generated from SIGtest Version 2.1 available from the PCI Special Interest Group. Figure 3-2: Typical Non-Transition Signal Eye, De-emphasis Disabled, Default Drive Setting GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 19 of 30 Proprietary & Confidential 3.4.2 PCI Express Receiver Characteristics Table 3-7: PCI Express Receiver Characteristics Symbol Description Min Typical Max Unit Voltage Parameters VRX-DIFFp-p Differential input voltage (peak-to-peak) 170 - 1200 mV VRX-IDLE-DET-DIFFp-p Differential input threshold voltage (peak-to-peak) to assert TxIdleDetect output 65 - 235 mV VRX-CM-AC Receiver common-mode voltage for AC-coupling - 0 150 mV TRX-RISE, TRX-FALL Rise time / Fall time of RxP, RxN inputs - - 160 ps ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 ZRX-COM-DC Single-ended input impedance 40 50 60 ZRX-COM-INITIAL-DC Initial input common mode impedance (DC) 5 50 60 ZRX-COM-HIGH-IMP-DC Powered down input common mode impedance (DC) 200k - - RLRX-DIFF Receiver Differential Return Loss1 10 - - dB RLRX-CM Receiver Common Mode Return Loss 6 - - dB TRX-MAX-JITTER Receiver maximum total jitter tolerance 0.65 - - UI TRX-EYE Minimum Receiver Eye Width 0.35 - - UI TRX-EYE-MEDIAN-to-MAX- Maximum time between jitter median and max deviation from median - - 0.325 UI Beacon-Activity on channel to 33 - 100 ns Jitter Parameters JITTER Timing Parameters TBDDly detection of Beacon2 TRX-IDLE_ENTER Delay from detection of Electrical Idle condition on the channel to assertion of TxIdleDetect output - 10 20 ns TRX-IDLE_EXIT Delay from detection of L0s to L0 transition to de-assertion of TxIdleDetect output - 5 10 ns 1. Over a frequency range of 50MHz to 1.25GHz. 2. This is a function of beacon frequency. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 20 of 30 Proprietary & Confidential Table 3-8: Reference Clock (PECLKINn) Requirements Symbol Description Min Typical Max VDD - 0.5 Unit VIL-RC Low-level CML/CMOS input voltage 0 - V VIH-RC High-level CML/CMOS input voltage - VDD FRefClk Clock frequency range 99.5 100 100.03 MHz1 D.C.RefClk Duty cycle 40 50 60 % TSkew-Ref Skew between PECLKINp/PECLKINn inputs - - 0.05 RCUI TCCJITTER Cycle to Cycle jitter - - 150 ps TRRef,TFRef Rise/Fall time of PECLKINp/PECLKINn inputs - 0.2 0.25 RCUI PPM PPM difference between reference clocks on different ends of a link -300 - +300 PPM V 1. Includes 0 to -0.5% spread spectrum clock range. 3.4.3 Local Bus Timing Figure 3-3 illustrates the timing relationships of the three local bus clock domains. Figure 3-3: Local Bus Timing TLCLK LCLK TCO TH LB Control (Output from GN4121) LB Control (Input to GN4121) TSU TLCLK-to-L2P_CLK TS TH TL2P_CLK TS L2P_CLK Lower Data Output from FPGA as Received by GN4121 L2P_DATA[15:0] Upper Data TH 0 TH 1 TSU TSU Data sampled by GN4121 90 from rising/falling of L2P_CLK L2P_FRAME, L2P_VALID, L2P_EDB TSU TH L2P_FRAME, L2P_VALID sampled by GN4121 90 from falling of L2P_CLK TLCLK-to-P2L_CLK TP2L_CLK P2L_CLK Output from GN4121 P2L_DATA[15:0] Lower Data 0 TSU Upper Data 1 TH TSU TH P2L_FRAME, P2L_VALID TSU GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 TH 21 of 30 Proprietary & Confidential Table 3-9: Local Bus Signal Timing for Single Data Rate SSTL Over Specified Operating Conditions (TARGET SPECIFICATION) Symbol Description Min Max Units TLCLK LCLK Cycle Time 8 10 ns TCO Clock to output delay for local bus control signals 0.7 5.0 ns1 TSU Required input set-up time to LCLK for local bus control inputs - 1.02 ns TH Required input hold time from LCLK for local bus control inputs - 0.7 ns 1. Local bus control signals received by an attached FPGA should be treated as asynchronous. See Local Bus Signals in the GN412x PCI Express Family Reference Manual for details. 2. Local bus control inputs are synchronized by the GN4121. Failure to meet setup time will simply delay the cycle in which the change is recognized. Table 3-10: Local Bus Timing for Source Synchronous SSTL Input Signals Over Specified Operating Conditions (TARGET SPECIFICATION) Input signals include L2P_CLK, L2P_DATA(15:0), L2P_DFRAME, and L2P_VALID. Symbol Description Min Max Units TL2P_CLK L2P_CLK Cycle Time or Unit Interval (UI) TLCLK ns IJTL2P_CLK L2P_CLK input jitter tolerance (cycle-to-cycle) - 100 ps TL2P_CLK_LOCK L2P_CLK input lock time - 1380 cycles TLCLK-to-L2P_CLK Delay from LCLK to L2P_CLK 0 TLCLK ns TS Sample point for data relative to L2P_CLK (rising and falling) L2P_CLK +90 TSU (L2P_DATA) Required input set-up time to L2P_CLK+TS (rising and falling) - 400 ps TH (L2P_DATA) Required input hold time from L2P_CLK+TS (rising and falling) - 400 ps Table 3-11: Local Bus Timing for Source Synchronous SSTL Output Signals Over Specified Operating Conditions (TARGET SPECIFICATION) Output signals include P2L_CLK, P2L_DATA(15:0), P2L_DFRAME, and P2L_VALID. Symbol Description Min Max Units TP2L_CLK P2L_CLK Cycle Time or Unit Interval (UI) TLCLK TLCLK-to-P2L_CLK Delay from LCLK to P2L_CLK TLCLK/2 - 1.2 TLCLK/2 +1.2 ns TSU (P2L_DATA) Output set-up time to P2L_CLK (rising and falling) 1200 - ps TH (P2L_DATA) Output hold time from P2L_CLK (rising and falling) 400 - ps TSKEW Skew between P2L_DATA lanes - 300 ps GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 ns 22 of 30 Proprietary & Confidential 3.4.4 Local Clocks' Pins Settings There are 3 local clocks used by the GN4121 and attached FPGA. They are: * LCLK/LCLKn: The primary clock generated by the GN4121 and driven to the FPGA in the form of a differential SSTL output. * P2L_CLKp/n: The source synchronous clock used by the GN4121 to communicate data to the FPGA. It is derived from the same source as LCLK/LCLKn. * L2P_CLKp/n: The source synchronous clock generated by the attached FPFA to communicate data to the GN4121. It is derived by the FPGA from LCLK/LCLKn. The local clock LCLK/LCLKn may be derived from either the PCI Express clock or a low frequency crystal oscillator. The options are described in Table 3-12. Table 3-12: GN4121 Clocks' Pins Settings Signal LCLK_MODE[3] Description Control IDDQ of the pads. Set to LOW for normal operation. LCLK_MODE[2] Controls PLL Bypass. `0' = LCLK is generated by the PLL, which is configurable. This is recommended for low and predictable LCLK clock jitter. `1' = LCLK is driven by 125MHz clock generated from the PCI Express link. LCLK_MODE[1] Resets the PLL test clock divider. `0' = Resets the PLL test clock divider, so that PLL_TEST_OUT = `0'. `1' = PLL_TEST_OUT pin outputs a clock with a frequency of the PLL clock divided by 1024. This is used for test purposes. LCLK_MODE[0] Selects the source for the LCLK PLL. `0' = LB_REF_CLK oscillator (20-40MHz). This is recommended for low and predictable LCLK clock jitter. `1' = 125MHz clock generated from the PCI Express link. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 23 of 30 Proprietary & Confidential 4. Overview A block diagram of the GN4121 is depicted in Figure 4-1. Figure 4-1: GN4121 Block Diagram Local Interface DDR DES Local Bus (to FPGA) GN4121 Tx Buffers Buffer Status and Throttle Control DDR SER Tx TL Tx Tx DLL PHY Rx TL Rx Rx DLL PHY PCIe Reference Clock (x1 Lane) Rx Buffers BAR4 and Config. Handler Local Clock FPGA Config. Loader PCI Express Core Type 0 Config. GPIO Extended Config. Interrupt Controller 2-Wire Controller MSI Ctrl. Master Control Reg. Boot Master Target Each of the internal blocks is described in detail in the following chapters. They are: * The PCI Express link is described in PCI Express Link section of the GN412x PCI Express Family Reference Manual. This includes a description of the PCI Express related configuration registers. * The Local bus is described in Local Bus Interface section of the GN412x PCI Express Family Reference Manual. * The interrupt controller is described in Interrupt Control Unit section of the GN412x PCI Express Family Reference Manual. * The boot master mode of the 2-wire controller is described in Initialization from a 2-Wire EEPROM section of the GN412x PCI Express Family Reference Manual. * General purpose master/target mode of the 2-wire controller is described in 2-Wire Interface section of the GN412x PCI Express Family Reference Manual. * General purpose IO are described inGeneral Purpose IO Block section of the GN412x PCI Express Family Reference Manual. * Details of all the internal registers and their respective register bit fields are described in Internal Registers section of the GN412x PCI Express Family Reference Manual. GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 24 of 30 Proprietary & Confidential 4.1 GN4121 Signals Figure 4-2 depicts the signals of the GN4121 laid out in their logical groupings. Figure 4-2: GN4121 Signal Groups Diagram GN4121 Local Bus Interface PCIe Link Transmit Interface Outbound Data (DDR SSTL) L2P_DATA[15:0] L2P_DFRAME L2P_VALID L2P_EDB L2P_CLKp L2P_CLKn PETp PETn PCIe Transmit PERp PERn PCIe Receive PECLKINp PECLKINn PCIe Reference Clock L_WR_RDY Outbound Buffer Status P_RD_D_RDY L2P_RDY TX_ERROR Receive Interface Inbound Data (DDR SSTL) Inbound Buffer Request / Status Local Bus Clock Output P2L_DATA[15:0] P2L_DFRAME P2L_VALID P2L_CLKp P2L_CLKn P_WR_REQ P_WR_RDY P2L_RDY VC_RDY Rx_ERROR LCLK LCLKn To Xtal or Oscillator LB_REF_CLK_MI LB_REF_CLK_MO Local Clock Mode Select LCLK_MODE[3:0] Scan / Test Control TDI TMS TCK TRST TDO JTAG SCAN_EN TEST_EN Reset Control RSTIN RSTOUT33 RSTOUT18 From PERST (PCIe CEM) To other system logic To FPGA FPGA Configuration SPRI_CLK SPRI_DATAOUT SPRI_CONFIG SPRI_DONE SPRI_XI_SWAP SPRI_STATUS To FPGA Serial Programming Interface 2-Wire Interface SCLK SDATA To Serial PROM and / or Processor General Purpose IO GPIO[15:0] GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 25 of 30 Proprietary & Confidential 5. Package & Ordering Information 5.1 Package Dimensions The GN4121 is packaged in a 256 ball BGA as illustrated in Figure 5-1. Figure 5-1: GN4121 Package Dimensions GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 26 of 30 Proprietary & Confidential 5.2 Packaging Data Table 5-1: Packaging Data Parameter Value Package Type 17mm x 17mm 256-ball BGA Package Drawing Reference Moisture Sensitivity Level 3 Junction to Air Thermal Resistance, j-a (at zero airflow) 27C/W Junction to Air Thermal Resistance, j-a (at 1m/s airflow) 24C/W Junction to Air Thermal Resistance, j-a (at 2m/s airflow) 22C/W Junction to Case Thermal Resistance, j-c 5.5C/W Psi 11.0C/W Pb-free and RoHS compliant Yes 5.3 Ordering Information Table 5-2: Packaging Data Part Number GN4121-CBE3 Package 256-BGA GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 Temperature Range 0C to 85C 27 of 30 Proprietary & Confidential Index Numerics L 2-wire serial controller 6 live on power-up 4 local bus interface 5 A absolute maximum ratings, electrical characteristics 15 application layer PCI Express 6 C configuration loader FPGA on-the-fly 5 local bus timing electrical characteristics 21 local clocks' pins settings 23 LVCMOS buffers, DC electrical characteristics 17 O operating conditions, electrical characteristics 15 ordering information 27 D overview 24 data sheet usage 6 P DC electrical characteristics 16 package dimensions 26 packaging and ordering information 26 E electrical characteristics absolute maximum ratings 15 DC 16 DC, LVCMOS buffers 17 DC, SSTL buffers 17 local bus timing 21 operating conditions 15 PCIe receiver 20 PCIe transmitter 17 packaging data 27 PCI Express application layer 6 PCI Express contact information 7 PCI Special Interest Group 7 PCIe receiver, electrical characteristics 20 PCIe transmitter, electrical characteristics 17 pin descriptions 9 pins global 9 global, 2-wire interface 10 F global, debug interface 10 features 3 global, general purpose interface 10 FPGA on-the-fly configuration loader 5 global, serial programming interface 11 G global, test interface 10 ground 14 Gennum contact information 7 local bus 12 getting answers to PCI Express related questions 7 local bus, inbound buffer request/status 12 getting help from Gennum 7 local bus, local PCIe (outbound data) 13 GN4121 signals 25 local bus, outbound buffer status 13 I I2C serial controller 6 interrupt controller 6 introduction 3 GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 local bus, PCIe to local (inbound data) 12 no connect 14 PCIe link, PCIe receive (input from the device) 11 PCIe link, PCIe transmit (output from the device) 11 28 of 30 Proprietary & Confidential PCIe link, PCIe x1 PHY interface 11 power 13 power-up live 4 S signals GN4121 25 SSTL buffers, DC electrical characteristics 17 V virtual channel support 6 GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 29 of 30 Proprietary & Confidential 30 DOCUMENT IDENTIFICATION CAUTION DATA SHEET ELECTROSTATIC SENSITIVE DEVICES The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION GENNUM CORPORATE HEADQUARTERS Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada E-mail: corporate@gennum.com www.gennum.com OTTAWA SNOWBUSH IP - A DIVISION OF GENNUM GERMANY 232 Herzberg Road, Suite 101 Kanata, Ontario K2K 2A1 Canada 439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada Hainbuchenstrae 2 80935 Muenchen (Munich), Germany Phone: +1 (613) 270-0458 Phone: +1 (416) 925-5643 Fax: +49-89-35804653 Fax: +1 (613) 270-0429 Fax: +1 (416) 925-0581 E-mail: gennum-germany@gennum.com CALGARY E-mail: sales@snowbush.com 3553 - 31st St. N.W., Suite 210 Calgary, Alberta T2L 2K7 Canada Web Site: http://www.snowbush.com Phone: +1 (403) 284-2672 UNITED KINGDOM MEXICO 288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900 Phone: +49-89-35831696 NORTH AMERICA WESTERN REGION Bayshore Plaza 2107 N 1st Street, Suite #300 San Jose, CA 95131 United States Phone: +1 (408) 392-9454 Phone: +1 (416) 848-0328 Fax: +1 (408) 392-9427 JAPAN KK E-mail: naw_sales@gennum.com NORTH AMERICA EASTERN REGION Fax: +44 1279 714171 Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan INDIA Phone: +81 (03) 3349-5501 Phone: +1 (905) 632-2996 #208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India Fax: +81 (03) 3349-5505 Fax: +1 (905) 632-2055 E-mail: gennum-japan@gennum.com E-mail: nae_sales@gennum.com Phone: +91 (674) 653-4815 TAIWAN Fax: +91 (674) 259-5733 6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C. North Building, Walden Court Parsonage Lane, Bishop's Stortford Hertfordshire, CM23 5DB United Kingdom Phone: +44 1279 714170 Web Site: http://www.gennum.co.jp 4281 Harvester Road Burlington, Ontario L7L 5M4 Canada KOREA 8F Jinnex Lakeview Bldg. 65-2, Bangidong, Songpagu Seoul, Korea 138-828 Phone: +82-2-414-2991 Phone: (886) 2-8732-8879 Fax: +82-2-414-2998 Fax: (886) 2-8732-8870 E-mail: gennum-korea@gennum.com E-mail: gennum-taiwan@gennum.com Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. PCIe and PCI Express mark are registered trademarks and/or service marks of PCI-SIG. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. (c) Copyright 2009 Gennum Corporation. All rights reserved. www.gennum.com GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 30 of 30 30 Proprietary & Confidential