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Characteristics subject to change without notice.
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Preliminary Information
128K
X4283/85
16K x 8 Bit
CPU Supervisor with 128K EEPROM
FEATURES
• Selectable watchdog timer
•Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
—Adjust low V
CC
reset threshold voltage using
special programming sequence
—Reset signal valid to V
CC
= 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock
™
protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead TSSOP
DESCRIPTION
The X4283/85 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply Volt-
age Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V
CC
falls below the set minimum V
CC
trip point. RESET/RESET is asserted until V
CC
returns
to proper operating level and stabilizes. Four industry
BLOCK DIAGRAM
Watchdog
Timer Reset
Data
Register
Command
Decode &
Control
Logic
SDA
SCL
VCC
Reset &
Watchdog
Timebase
Power on and
Generation
VTRIP
+
-
RESET (X4283)
Reset
Low Voltage
Status
Register
Protect Logic
EEPROM Array
Watchdog Transition
Detector
WP
VCC Threshold
Reset logic
Block Lock Control
8Kb 4Kb 4Kb
RESET (X4285)
S0
S1
X4283/85 – Preliminary Information
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standard Vtrip thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software proto-
col allowing operation on an 2-wire bus.
PIN CONFIGURATION
S1
VSS
VCC
SDA
SCL
3
2
4
1
6
7
5
8
S0
WP
RST/RST
VCC
S1
SCL
RST/RST
VSS
3
2
4
1
6
7
5
8
WP
SDA
S0
8-Pin JEDEC SOIC
8-Pin TSSOP
PIN DESCRIPTION
Pin
(SOIC)
Pin
(TSSOP) Name Function
13 S
0
Device Select Input
24 S
1
Device Select Input
3 5 RESET/
RESET
Reset Output
.
RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain
active until V
CC
rises above the minimum V
CC
sense level for 250ms. RESET/
RESET goes active if the Watchdog Timer is enabled and SDA remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling edge
on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes
active on power up and remains active for 250ms after the power supply stabilizes.
46 V
SS
Ground
5 7 SDA
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
6 8 SCL
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
71 WP
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
82 V
CC
Supply Voltage
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PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4283/85 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
TRIP
threshold value
for 200ms (nominal) the circuit releases RESET/
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4283/85 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL is HIGH (this is a start bit) prior
to the expiration of the watchdog time out period to pre-
vent a RESET/RESET signal. The state of two nonvola-
tile control bits in the Status Register determine the
watchdog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
CC
THRESHOLD RESET PROCEDURE
The X4283/85 is shipped with a standard V
CC
thresh-
old (V
TRIP
) voltage. This value will not change over nor-
mal operating and storage conditions. However, in
applications where the standard V
TRIP
is not exactly
right, or if higher precision is needed in the V
TRIP
value, the X4283/85 threshold may be adjusted. The
procedure is described below, and uses the application
of a nonvolatile control signal.
Figure 1. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
01234567
SCL
SDA
A0h
01234567
00h
WP VP = 12-15V
01234567
01h
01234567
00h
X4283/85 – Preliminary Information
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Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher or
lower voltage value. It is necessary to reset the trip
point before setting the new value.
To set the new V
TRIP
voltage, start by setting the WEL
bit in the control register, then apply the desired V
TRIP
threshold voltage to the V
CC
pin and the programming
voltage, V
P
,
to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit following a valid write
operation initiates the V
TRIP
programming sequence.
Bring WP
LOW to complete the operation.
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native”
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When V
TRIP
is reset, the new V
TRIP
is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V
TRIP
voltage start by setting the WEL
bit in the control register, apply V
CC
and the program-
ming voltage, V
P
, to the WP pin and 2 byte address and
1 byte of “00” data. The stop bit of a valid write opera-
tion initiates the V
TRIP
programming sequence. Bring
WP
LOW to complete the operation.
Figure 2. Reset V
TRIP
Level Sequence (V
CC
> 3V. WP = 12-15V, WEL bit set)
Figure 3. Sample V
TRIP
Reset Circuit
01234567
SCL
SDA
A0h
01234567
00h
WP VP = 12-15V
01234567
03h
01234567
00h
1
2
3
4
8
7
6
5
X4283
VTRIP
Adj.
VP
RESET
4.7K
SDA
SCL
µC
Adjust
Run
SOIC
X4283/85 – Preliminary Information
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Figure 4. V
TRIP
Programming Sequence
VTRIP Programming
Apply 5V to VCC
Decrement VCC
RESET pin
goes active?
Measured VTRIP -
Desired VTRIP
DONE
Execute
Sequence
Reset VTRIP
Set VCC = VCC Applied =
Desired VTRIP
Execute
Sequence
Set VTRIP
New VCC Applied =
Old VCC Applied + Error
(VCC = VCC - 50mV)
Execute
Sequence
Reset VTRIP
New VCC Applied =
Old VCC Applied - Error
Error ≤ –Emax
–Emax < Error < Emax
YES
NO
Error ≥ Emax
Emax = Maximum Allowed VTRIP Error
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4283/85 will not
acknowledge any data bytes written after the first byte
is entered.
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The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4283/85 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and zeroes
to the other bits of the control register. Once set, WEL
remains set until either it is reset to 0 (by writing a “0” to
the WEL bit and zeroes to the other bits of the control
register) or until the part powers up again. Writes to the
WEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of eight blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit. Four of the 8 protected blocks
match the original Block Lock segments and this pro-
tection scheme is fully compatible with the current
devices using 2 bits of block lock control (assuming the
BP2 bit is set to 0).
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is Hard-
ware Write Protected, nonvolatile writes as well as to the
block protected sections in the memory array cannot be
written. Only the sections of the memory array that are
not block protected can be written. Note that since the
WPEN bit is write protected, it cannot be changed back
to a LOW state; so write protection is enabled as long
as the WP pin is held HIGH.
76543210
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
BP2
BP1
BP0
Protected Addresses
(Size) Array Lock
0 0 0 None (factory setting) None
0 0 1 3000h - 3FFFh (4K bytes)Upper 1/4 (Q4)
0 1 0 2000h - 3FFFh (8K bytes)Upper 1/2 (Q3,Q4)
0 1 1 0000h - 3FFFh (16K bytes) Full Array (All)
100 000
h - 03Fh (64 bytes) First Page (P1)
101 000
h - 07Fh (128 bytes) First 2 pgs (P2)
110 000
h - 0FFh (256 bytes) First 4 pgs (P4)
111 000
h - 1FFh (512 bytes) First 8 pgs (P8)
WD1 WD0 Watchdog Time Out Period
0 0 1.4 seconds (factory setting)
0 1 600 milliseconds
1 0 200 milliseconds
1 1 disabled
X4283/85 – Preliminary Information
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Table 1. Write Protect Enable Bit and WP Pin Function
WP WPEN
Memory Array not
Block Protected
Memory Array
Block Protected
Block Protect
Bits WPEN Bit Protection
LOW X Writes OK Writes Blocked Writes OK Writes OK Software
HIGH 0 Writes OK Writes Blocked Writes OK Writes OK Software
HIGH 1 Writes OK Writes Blocked Writes Blocked Writes Blocked Hardware
Writing to the Control Register
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceded by a start
and ended with a stop).
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be repre-
sented as 0xys t 01r in binary, where xy are the WD
bits, and rst are the BP bits. (Operation preceded by a
start and ended with a stop). Since this is a nonvola-
tile write cycle it will take up to 10ms to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (0xys t11r) then the
RWEL bit is set, but the WD1, WD0, BP2, BP1 and
BP0 bits remain unchanged. Writing a second byte to
the control register is not allowed. Doing so aborts the
write operation and returns a NACK.
– A read operation occurring between any of the previous
operations will not interrupt the register write operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the Control Register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto
the bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera-
tions. Therefore, the devices in this family operate as
slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable Data Change Data Stable
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Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 6.
Serial Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 6.
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start Stop
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 7.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Figure 7. Acknowledge Response from Receiver
Data Output
from Transmitter
Data Output
from Receiver
81 9
START Acknowledge
SCL from
Master
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Serial Write Operations
BYTE WRITE
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array. After
receipt of the Word Address Byte, the device responds
with an acknowledge, and awaits the next eight bits of
data. After receiving the 8 bits of the Data Byte, the
device again responds with an acknowledge. The mas-
ter then terminates the transfer by generating a stop
condition, at which time the device begins the internal
write cycle to the nonvolatile memory. During this inter-
nal write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 8.
Figure 8. Byte Write Sequence
S
t
a
r
t
S
t
o
p
Slave
Address Word Address
Byte 0 Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Word Address
Byte 1
A
C
K
0101
A write to a protected block of memory will suppress
the acknowledge bit.
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit an
unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that the
master can write 64 bytes to the page starting at any
location on that page. If the master begins writing at
location 60, and loads 12 bytes, then the first 4 bytes
are written to locations 60 through 63, and the last 8
bytes are written to locations 0 through 7. Afterwards,
the address counter would point to location 8 of the
page that was just written. If the master supplies more
than 64 bytes of data, then new data over-writes the
previous data, one byte at a time.
Figure 9. Page Write Operation
S
t
a
r
t
S
t
o
p
Slave
Address
Word Address
Byte 1
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1 < n < 64)
Word Address
Byte 0
A
C
K
1010
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Figure 10. Writing 12 bytes to a 64-byte page starting at location 60.
Address
Address
60
4 Bytes
n-1
8 Bytes
Address
= 7
Address Pointer
Ends Here
Addr = 8
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in
the middle of a data byte, or before 1 full data byte plus
its associated ACK is sent, then the device will reset
itself without performing the write. The contents of the
array will not be effected.
Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the device
initiates the internal nonvolatile cycle. Acknowledge
polling can be initiated immediately. To do this, the
master issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device
is still busy with the nonvolatile cycle then no ACK will
be returned. If the device has completed the write oper-
ation, an ACK will be returned and the host can then
proceed with the read or write operation. Refer to the
flow chart in Figure 11.
Figure 11. Acknowledge Polling Sequence
ACK
returned?
Issue Slave Address
Byte (Read or Write)
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
Nonvolatile Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
Continue Normal
Read or Write
Command Sequence
PROCEED
YES
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Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 12 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Figure 12. Current Address Read Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
1010
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Figure 13. Random Address Read Sequence
0
Slave
Address
Word Address
Byte 1
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master Word Address
Byte 0
A
C
K
0101
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There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a stop
is issued instead of the second start shown in Figure
13. The device goes into standby mode after the stop
and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge,
indicating it requires additional data. The device contin-
ues to output data for each acknowledge received. The
master terminates the read operation by not responding
with an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000H and the device continues
to output data for each acknowledge received. Refer to
Figure 14 for the acknowledge and data transfer
sequence.
Figure 14. Sequential Read Sequence
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
X4283/85 Addressing
SLAVE ADDRESS BYTE
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is ‘1010’ to access the array
– one bits of ‘0’.
– next two bits are the device address.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 15.
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
X4283/85 – Preliminary Information
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Figure 15. X4283/85 Addressing
R/WS0S100101
Slave Address Byte
Device Identifier Device Select
A8A9A10A11A12A13
00
Word Address Byte 0–128K
High Order Word Address
(X6) (X5) (X4) (X3) (X2)(X7)
A0A1A2
Word Address Byte 0 for all Options
Low Order Word Address
(Y2) (Y1) (Y0)
A3
(Y3)
A4
(Y4)
A5
(Y5)
A6
(X0)
A7
(X1)
D0D1D2D3D4D5D6D7
Data Byte for all Options
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for tPURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
– Communication to the device is inhibited while
RESET/RESET is active and any in-progress
communication is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X4283/85 – Preliminary Information
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with
respect to VSS.......................................-1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C 70°C
Industrial -40°C +85°C
Option Supply Voltage Limits
–2.7 and –2.7A 2.7V to 5.5V
Blank and –4.5A 4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates
a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
Symbol Parameter
VCC = 2.7 to 5.5V
Unit Test ConditionsMin Max
ICC1(1) Active Supply Current Read 1.0 mA VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz, SDA = Commands
ICC2(1) Active Supply Current Write 3.0 mA
ISB1(2) Standby Current DC (WDT off) 1 µA VSDA = VSCL = VSB
Others = GND or VSB
ISB2(2) Standby Current DC (WDT on) 20 µA VSDA = VSCL = VSB
Others = GND or VSB
ILI Input Leakage Current 10 µA VIN = GND to VCC
ILO Output Leakage Current 10 µA VSDA = GND to VCC
Device is in Standby(2)
VIL(3) Input LOW Voltage -0.5 VCC x 0.3 V
VIH(3) Input nonvolatile VCC x 0.7 VCC +0.5 V
VHYS Schmitt Trigger Input Hysteresis
Fixed input level
VCC related level
0.2
.05 x VCC
V
V
VOL Output LOW Voltage 0.4 V IOL = 3.0mA (2.7–5.5V)
X4283/85 – Preliminary Information
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CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Note: (4) This parameter is periodically sampled and not 100% tested.
Symbol Parameter Max. Unit Test Conditions
COUT(4) Output Capacitance (SDA, RST/RST) 8 pF VOUT = 0V
CIN(4) Input Capacitance (SCL, WP) 6 pF VIN = 0V
EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS
SDA
or
RESET
1533Ω
100pF
5V
For VOL = 0.4V
and IOL = 3 mA
Input pulse levels 0.1 VCC to 0.9 VCC
Input rise and fall times 10ns
Input and output timing levels 0.5VCC
Output load Standard output load
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V
(6) Cb = total capacitance of one bus line in pF.
Symbol Parameter Min. Max. Unit
fSCL SCL Clock Frequency 0 400 kHz
tIN Pulse width Suppression Time at inputs 50 ns
tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs
tBUF Time the bus free before start of new transmission 1.3 µs
tLOW Clock LOW Time 1.3 µs
tHIGH Clock HIGH Time 0.6 µs
tSU:STA Start Condition Setup Time 0.6 µs
tHD:STA Start Condition Hold Time 0.6 µs
tSU:DAT Data In Setup Time 100 ns
tHD:DAT Data In Hold Time 0 µs
tSU:STO Stop Condition Setup Time 0.6 µs
tDH Data Output Hold Time 50 ns
tRSDA and SCL Rise Time 20 +.1Cb(6) 300 ns
tFSDA and SCL Fall Time 20 +.1Cb(6) 300 ns
tSU:WP WP Setup Time 0.6 µs
tHD:WP WP Hold Time 0 µs
Cb Capacitive load for each bus line 400 pF
X4283/85 – Preliminary Information
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TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol Parameter Min. Typ.(1) Max. Unit
tWC(1) Write Cycle Time 5 10 ms
tSU:STO
tDH
tHIGH
tSU:STA tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA IN
SDA OUT
tFtLOW
tBUF
tAA
tR
tHD:WP
SCL
SDA IN
WP
tSU:WP
Clk 1 Clk 9
Slave Address Byte
START
SCL
SDA
tWC
8th Bit of Last Byte ACK
Stop
Condition
Start
Condition
X4283/85 – Preliminary Information
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Power-Up and Power-Down Timing
RESET Output Timing
Note: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
Symbol Parameter Min. Typ. Max. Unit
VTRIP Reset Trip Point Voltage, X4283/85-4.5A
Reset Trip Point Voltage, X4283/85
Reset Trip Point Voltage, X4283/85-2.7A
Reset Trip Point Voltage, X4283/85-2.7
4.5
4.25
2.85
2.55
4.62
4.38
2.92
2.62
4.75
4.5
3.0
2.7
V
tPURST Power-up Reset Time out 100 250 400 ms
tRPD(8) VCC Detect to Reset/Output 500 ns
tF(8) VCC Fall Time 100 µs
tR(8) VCC Rise Time 100 µs
VRVALID Reset Valid VCC 1V
VCC
tPURST
tR
tF
tRPD
0 Volts
VTRIP
RESET
RESET
VRVALID
(X4285)
(X4283)
tPURST
VRVALID
tRSP<tWDO tRST
RESET
SDA
tRSP
Note: All inputs are ignored during the active reset period (tRST).
tRST
SCL
tRSP>tWDO
tRSP>tWDO
X4283/85 – Preliminary Information
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RESET Output Timing
VTRIP Programming Timing Diagram (WEL = 1)
VTRIP Programming Parameters
Symbol Parameter Min. Typ. Max. Unit
tWDO Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0 (factory setting)
100
450
1
250
650
1.5
400
850
2
ms
ms
sec
tRST Reset Time Out 100 250 400 ms
Parameter Description Min. Max. Unit
tVPS VTRIP Program Enable Voltage Setup time 1 µs
tVPH VTRIP Program Enable Voltage Hold time 1 µs
tTSU VTRIP Setup time 1 µs
tTHD VTRIP Hold (stable) time 10 ms
tWC VTRIP Write Cycle Time 10 ms
tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs
tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms
VPProgramming Voltage 15 18 V
VTRAN VTRIP Programmed Voltage Range 2.55 4.75 V
Vta1 Initial VTRIP Program Voltage accuracy (VCC applied–VTRIP) (Programmed at 25°C.) -0.1 +0.4 V
Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied–Vta1)—VTRIP.
Programmed at 25°C.)
-25 +25 mV
Vtr VTRIP Program Voltage repeatability (Successive program operations. Programmed
at 25°C.)
-25 +25 mV
Vtv VTRIP Program variation after programming (0–75°C). (Programmed at 25°C.) -25 +25 mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
VCC
(VTRIP)
WP
tTSU tTHD
tVPH
tVPS
VP
VTRIP
tVPO
SCL
SDA
A0h 01h or 03h
tRP
00h 00h
X4283/85 – Preliminary Information
Characteristics subject to change without notice. 19 of 22
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PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7°
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0° - 8°
X 45°
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"
Typical
0.030"
Typical
8 PlacesFOOTPRINT
X4283/85 – Preliminary Information
Characteristics subject to change without notice. 20 of 22
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PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
8-Lead Plastic, TSSOP, Package Type V
See Detail “A”
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5) .252 (6.4) BSC
.025 (.65) BSC
.114 (2.9)
.122 (3.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0° – 8°
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16) (7.72)
(1.78)
(0.42)
(0.65)
All Measurements Are Typical
X4283/85 – Preliminary Information
Characteristics subject to change without notice. 21 of 22
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Ordering Information
Part Mark Information
VCC
Range
VTRIP
Range Package
Operating
Temperature Range
Part Number RESET
(Active LOW)
Part Number RESET
(Active HIGH)
4.5-5.5V 4.5-4.75 8L SOIC 0°C–70°C X4283S8–4.5A X4285S8–4.5A
-40°C–85°C X4283S8I–4.5A X4285S8I–4.5A
8L TSSOP 0°C–70°C X4283V8–4.5A X4285V8–4.5A
-40°C–85°C X4283V8I–4.5A X4285V8I–4.5A
4.5-5.5V 4.25-4.5 8L SOIC 0°C–70°C X4283S8 X4285S8
-40°C–85°C X4283S8I X4285S8I
8L TSSOP 0°C–70°C X4283V8 X4285V8
-40°C–85°C X4283V8I X4285V8I
2.7-5.5V 2.85-3.0 8L SOIC 0°C–70°C X4283S8–2.7A X4285S8–2.7A
-40°C–85°C X4283S8I–2.7A X4285S8I–2.7A
8LTSSOP 0°C–70°C X4283V8–2.7A X4285V8–2.7A
-40°C–85°C X4283V8I–2.7A X4285V8I–2.7A
2.7-5.5V 2.55-2.7 8L SOIC 0°C–70°C X4283S8–2.7 X4285S8–2.7
-40°C–85°C X4283S8I–2.7 X4285S8I–2.7
8L TSSOP 0°C–70°C X4283V8–2.7 X4285V8–2.7
-40°C–85°C X4283V8I–2.7 X4285V8I–2.7
8-Lead TSSOP
EYWW
XXXXX
8-Lead SOIC
X4283/85 X
XX
Blank = 8-Lead SOIC
ADB/ADK = –4.5A (0 to +70°C)
ADD/ADM = No Suffix (0 to +70°C)
ADF/ADO = –2.7A (0 to +70°C)
ADH/ADQ = –2.7 (0 to +70°C)
4283/4285
F = –2.7 (0 to +70°C)
G = –2.7 (-40 to +85°C)
Blank = No Suffix (0 to +70°C)
I = No Suffix (-40 to +85°C)
AN = –2.7A (0 to +70°C)
AP = –2.7A (-40 to +85°C)
AL = –4.5A (0 to +70°C)
AM = –4.5A (-40 to +85°C)
X4283/85 – Preliminary Information
Characteristics subject to change without notice. 22 of 22
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
©Xicor, Inc. 2000 Patents Pending
REV 1.17 11/27/00 www.xicor.com
