UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP www.ti.com SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 QML CLASS V, CURRENT-MODE PWM CONTROLLERS Check for Samples: UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP FEATURES 1 Comp 1 8 VREF VFB 2 7 VCC ISENSE 3 6 Output RT/CT 4 5 Gnd Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details. The LDR improved die is only available in the UC1843A-SP (Orderable as 5962-8670409VPA). Contact factory to request an LDR improved version of the UC1842A-SP, UC1844A-SP, and UC1845A-SP. N/C VREF N/C 2 1 20 19 18 N/C 3 4 VCC 17 VC 16 15 N/C 14 8 9 10 11 12 13 N/C 5 6 7 !?! Output Gnd N/C ISENSE N/C N/C VFB Comp FK PACKAGE (TOP VIEW) N/C Pwr Gnd (2) JG PACKAGE (TOP VIEW) N/C (1) QML-V Qualified, SMD 5962-86704 Rad-Tolerant: 30 kRad (Si) TID (1) (2) Optimized for Offline and DC-to-DC Converters Low Start-Up Current (<0.5 mA) Trimmed Oscillator Discharge Current Automatic Feed Forward Compensation Pulse-by-Pulse Current Limiting Enhanced Load Response Characteristics Undervoltage Lockout With Hysteresis Double-Pulse Suppression High-Current Totem-Pole Output Internally Trimmed Bandgap Reference 500-kHz Operation Low RO Error Amplifier RT/CT * * * * * * * * * * * * * * DESCRIPTION The UC1842A/3A/4A/5A family of control IC's is a pin for pin compatible improved version of the UC1842/3/4/5 family.Providing the necessary features to control current-mode switched-mode power supplies, this device has the following improved features. Start up current is guaranteed to be less than 0.5 mA. Oscillator discharge is trimmed to 8.3 mA. During undervoltage lockout, the output stage can sink at least 10 mA at less than 1.2 V for VCC over 5 V. The difference between members of this family are shown in Table 1. Table 1. UC184xA Family PART NO. UVLO ON UVLO OFF MAXIMUM DUTY CYCLE UC1842A 16.0 V 10.0 V < 100% UC1843A 8.5 V 7.9 V < 100% UC1844A 16.0 V 10.0 V < 50% UC1845A 8.5 V 7.9 V < 50% 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009-2013, Texas Instruments Incorporated UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 www.ti.com BLOCK DIAGRAM 7 8 5 7 4 6 5 2 1 3 Table 2. ORDERING INFORMATION (1) PARENT UC1842A UC1843A UC1844A UC1845A (1) (2) PACKAGE (2) ORDERABLE PART NUMBER JG (8-CDIP) 5962-8670405VPA FK (20-LCCC) 5962-8670405VXA JG (8-CDIP) 5962-8670406VPA FK (20-LCCC) 5962-8670406VXA JG (8-CDIP) 5962-8670407VPA FK (20-LCCC) 5962-8670407VXA JG (8-CDIP) 5962-8670408VPA FK (20-LCCC) 5962-8670408VXA TA TOP-SIDE MARKING -55C to 125C -55C to 125C -55C to 125C -55C to 125C 8670405VPA/UC1842A 5962-8670405VXA/UC1842ALQMLV 8670406VPA/UC1843A 5962-8670406VXA/UC1843ALQMLV 8670407VPA/UC1844A 5962-8670407VXA/UC1844ALQMLV 8670408VPA/UC1845A 5962-8670408VXA/UC1845ALQMLV For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 3. ORDERING INFORMATION (RADIATION IMPROVED DEVICES) (1) (1) (2) (3) 2 (2) PARENT PACKAGE (3) ORDERABLE PART NUMBER TA TOP-SIDE MARKING UC1843A JG (8-CDIP) 5962-8670409VPA -55C to 125C 8670409VPA/UC1843A-SP See Electrical Characteristics (Radiation Improved Devices). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP www.ti.com SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage, low-impedance source IO 30 V Supply current Self limiting Output current 1 A 5 J Output energy (capacitive load) VI Input voltage (VFB, ISENSE) -0.3 V to 6.3 V Error amplifier output sink current PD Power dissipation (TA = 25C) Tstg Storage temperature range Tlead Lead temperature (soldering, 10 seconds) (1) (2) 10 mA 1W -65C to 150C 300C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (TA = TJ = -55C to 125C), unless otherwise noted. MIN VCC Supply voltage MAX UNIT 12 25 V Sink/source output current (continuous or time average) 0 200 mA Reference load current 0 20 mA ELECTRICAL CHARACTERISTICS VCC = 15 V (1), RT = 10 k, CT = 3.3 nF, TA = TJ = -55C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.95 5 5.06 V Reference Section Output voltage TJ = 25C, IO = 1 mA Line regulation VIN = 12 V to 25 V 6 20 Load regulation IO = 1 mA to 20 mA 6 25 mV 0.2 0.4 mV/C Temperature stability (2) (3) Total output variation Over line, load, and temperature Output noise voltage 10 Hz f 10 kHz, TJ = 25C Long term stability 1000 hours, TA = 125C (2) 4.9 5.1 -30 V V 50 Short-circuit output current mV 5 25 mV -100 -180 mA 52 57 kHz 0.2 1 % Oscillator Section Initial accuracy TJ = 25C (4) Voltage stability VCC = 12 V to 25 V Temperature stability TA = MIN to MAX Amplitude peak-to-peak V pin 4 (2) V pin 4 = 2 V (5) Discharge current (1) (2) (3) (4) (5) 47 (2) 5 % 1.7 TJ = 25C 7.8 TJ = Full range 7.5 8.3 V 8.8 8.8 mA Adjust VCC above the start threshold before setting at 15 V. Parameters ensured by design and/or characterization, if not production tested. Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: Temp Stability = VREF (max) - VREF (min)/TJ (max) - TJ (min). VREF (max) and VREF (min) are the maximum and minimum reference voltage measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature. Output frequency equals ocscillator frequency for the UC1842A and UC1843A. Output frequency is one half oscillator frequency for UC18444A and UC1845A. This parameter is measured with RT = 10 k to VREF. This contributes approximately 300 A of current to the measurement. The total current flowing into the RT/CT pin will be approximately 300 A higher than the measured value. Copyright (c) 2009-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP 3 UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VCC = 15 V(1), RT = 10 k, CT = 3.3 nF, TA = TJ = -55C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.45 2.50 2.55 mV -0.3 -1 A Error Amp Section Input voltage VComp = 2.5 V Input bias current Open-loop voltage gain VO = 2 V to 4 V 65 (6) Unity-gain bandwidth TJ = 25C PSRR VCC = 12 V to 25 V Output sink current VFB = 2.7 V, VComp = 1.1 V Output source current VFB = 2.3 V, VComp = 5 V High-level output voltage VFB = 2.3 V, RL = 15 k to ground Low-level output voltage VFB = 2.7 V, RL = 15 k to VREF 90 dB 0.7 1 MHz 60 70 dB 2 6 mA -0.5 -0.8 mA 5 6 V 0.7 1.1 V 2.85 3 3.15 V/V 0.9 1 1.1 Current Sense Section Gain (7) (8) Maximum input signal VComp = 5 V (7) PSRR VCC = 12 V to 25 V (7) 70 -2 -10 A (6) 150 300 ns ISINK = 20 mA 0.1 0.4 V ISINK = 200 mA 1.5 2.2 V Input bias current Delay to output VISENSE = 0 to 2 V V dB Output Section Output low-level voltage Output high-level voltage ISOURCE = -20 mA 13 13.5 ISOURCE = -200 mA 12 13.5 Rise time CL = 1 nF, TJ = 25C (6) Fall time UVLO saturation V V 50 150 ns CL = 1 nF, TJ = 25C (6) 50 150 ns VCC = 5 V, ISINK = 10 mA 0.7 1.2 V Undervoltage Lockout Section Start threshold Minimum operation voltage after turn-on UC1842A, UC1844A 15 16 17 UC1843A, UC1845A 7.8 8.4 9 UC1842A, UC1844A 9 10 11 UC1843A, UC1845A 7 7.6 8.2 UC1842A, UC1843A 94 96 100 UC1844A, UC1845A 47 48 50 V V PWM Section Maximum duty cycle Minimum duty cycle 0 % % Total Standby Current Start-up current (6) (7) (8) 4 Operating supply current VFB = VISENSE = 0 V VCC zener voltage ICC = 25 mA 30 0.3 0.5 mA 11 17 mA 34 V Parameters ensured by design and/or characterization, if not production tested. Parameter measured at trip point of latch with VFB = 0 V. Gain defined as: G = VComp/VISENSE; VISENSE = 0 to 0.8 V. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP www.ti.com SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS (RADIATION IMPROVED DEVICES) (1) VCC = 15 V, RT = 10 k, CT = 3.3 nF, TA = TJ = -55C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 4.94 UNIT Reference Section Output voltage TJ = 25C, IO = 1 mA 5 5.06 Line regulation VCC = 12 V to 25 V 6 20 mV Load regulation IL = 1 mA to 20 mA 6 25 mV Total output variation Over line, load, and temperature Output noise voltage 10 Hz f 10 kHz, TJ = 25C 4.9 5.1 -30 V V 50 Short-circuit output current V -100 -180 mA 52 57 kHz 0.2 1 % Oscillator Section Initial accuracy TJ = 25C Voltage stability VCC = 12 V to 25 V Temperature stability TJ = -55C to 125C 5 Amplitude VRT/CT peak to peak 1.7 Discharge current (2) 47 TJ = 25C, VRT/CT = 2 V 7.8 VRT/CT = 2 V 7.5 8.3 % V 8.8 8.8 mA Error Amp Section Input voltage VComp = 2.5 V 2.45 Input bias current 2.50 2.55 mV -0.3 -1 A Open-loop voltage gain VO = 2 V to 4 V 65 90 dB Unity-gain bandwidth TJ = 25C (3) 0.7 1 MHz PSRR VCC = 12 V to 25 V 60 70 dB Output sink current VFB = 2.7 V, VComp = 1.1 V Output source current VFB = 2.3 V, VComp = 5 V High-level output voltage VFB = 2.3 V, RL = 15 k to ground Low-level output voltage VFB = 2.7 V, RL = 15 k to VREF 2 6 mA -0.5 -0.8 mA 5 6 V 0.7 1.1 V 2.85 3 3.15 V/V 0.9 1 1.1 V Current Sense Section Gain (4) (5) VComp = 5 V (4) Maximum input signal PSRR VCC = 12 V to 25 V (4) 70 Delay to output dB -2 -10 A 150 300 ns ISINK = 20 mA 0.1 0.4 V ISINK = 200 mA 1.5 2.2 V Input bias current VISENSE = 0 to 2 V (3) Output Section Output low-level voltage Output high-level voltage ISOURCE = 20 mA 13 13.5 ISOURCE = 200 mA 12 13.0 V V Rise time CL = 1 nF, TJ = 25C (3) 50 150 ns Fall time CL = 1 nF, TJ = 25C (3) 50 150 ns UVLO saturation VCC = 5 V, ISINK = 10 mA 0.7 1.2 V 7.8 8.4 9 V 7 7.6 8.2 V Undervoltage Lockout Section Start threshold Minimum operation voltage after turn-on PWM Section (1) (2) (3) (4) (5) See Ordering Information (Radiation Improved Devices). This parameter is measured with RT = 10 k to VREF. This contributes approximately 300 A of current to the measurement. The total current flowing into the RT/CT pin will be approximately 300 A higher than the measured value. Parameters ensured by design and/or characterization, if not production tested. Parameter measured at trip point of latch with VFB = 0 V. Gain defined as: G = VComp/VISENSE; VISENSE = 0 to 0.8 V. Copyright (c) 2009-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP 5 UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (RADIATION IMPROVED DEVICES)(1) (continued) VCC = 15 V, RT = 10 k, CT = 3.3 nF, TA = TJ = -55C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS Maximum duty cycle MIN TYP MAX UNIT 94 96 100 % 0 % 0.3 0.5 mA 11 17 mA Minimum duty cycle Total Standby Current Start-up current 6 Operating supply current VFB = VISENSE = 0 V VCC zener voltage ICC = 25 mA Submit Documentation Feedback 30 34 V Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP www.ti.com SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 APPLICATION INFORMATION Amp can Source and Sink up to 0.5mA, and Sink up to 2mA. Figure 1. Error Amplifier Configuration During UVLO, the Output is low. Figure 2. Undervoltage Lockout Peak Current (IS) is Determined By The Formula 1.0V ISMAX RS A small RC filter may be required to suppress switch transients. Figure 3. Current-Sense Circuit Copyright (c) 2009-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP 7 UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 www.ti.com Figure 4. Output Saturation Characteristics Figure 5. Error Amplifier Open-Loop Frequency Response Oscillator Frequency vs Timing Resistance Maximum Duty Cycle vs Timing Resistor Figure 6. Oscillation Section 8 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP www.ti.com SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sam ple the oscillator waveform and apply an adjustable ramp to pin 3. Figure 7. Open-Loop Laboratory Test Fixture A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes. Figure 8. Slope Compensation Copyright (c) 2009-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP 9 UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP SLUS872B - JANUARY 2009 - REVISED OCTOBER 2013 Power Supply Specifications 1. Input Voltage 2. Line Isolation 3. Switching Frequency 4. Efficiency Full Load 95VAC to 130VA (50 Hz/60Hz) 3750V 40kHz 70% www.ti.com 5. Output Voltage: A. +5V, 5%; 1A to 4A load Ripple voltage: 50mV P-P Max B. +12V, 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max C. -12V , 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max Figure 9. Offline Flyback Regulator 10 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: UC1842A-SP UC1843A-SP UC1844A-SP UC1845A-SP PACKAGE OPTION ADDENDUM www.ti.com 22-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 5962-8670405VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670405VPA UC1842A 5962-8670405VXA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59628670405VXA UC1842AL QMLV 5962-8670406VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670406VPA UC1843A 5962-8670406VXA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59628670406VXA UC1843AL QMLV 5962-8670407VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670407VPA UC1844A 5962-8670407VXA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59628670407VXA UC1844AL QMLV 5962-8670408VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670408VPA UC1845A 5962-8670408VXA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59628670408VXA UC1845AL QMLV 5962-8670409VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670409VPA UC1843A-SP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Oct-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP : * Catalog: UC1842A, UC1843A, UC1844A, UC1845A * Enhanced Product: UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. 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