LTC5800-IPM
1
5800ipmfa
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TYPICAL APPLICATION
NETWORK FEATURES DESCRIPTION
SmartMesh IP Node 2.4GHz
802.15.4e Wireless Mote-on-Chip
SmartMesh IP™ wireless sensor networks are self manag-
ing, low power internet protocol (IP) networks built from
wireless nodes called motes. The LT C
®
5800-IPM is the
IP mote product in the Eterna
®
* family of IEEE 802.15.4e
System-on-Chip (SoC) solutions, featuring a highly-
integrated, low power radio design by Dust Networks
®
as
well as an ARM Cortex-M3 32-bit microprocessor running
Dust’s embedded SmartMesh IP networking software.
The LTC5800-IPM SoC features an on-chip power ampli-
fier (PA) and transceiver, requiring only power supply
decoupling, crystals, and antenna with matching circuitry
to create a complete wireless node.
With Dust’s time-synchronized SmartMesh IP networks,
all motes in the network may route, source or terminate
data, while providing many years of battery powered
operation. The SmartMesh IP software provided with the
LTC5800-IPM is fully tested and validated, and is read-
ily configured via a software Application Programming
Interface.
SmartMesh IP motes deliver a highly flexible network
with proven reliability and low power performance in an
easy-to-integrate platform.
L, LT , LT C , LT M , Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and
Eterna are registered trademarks and LTP, the Dust Networks logo, SmartMesh IP and Mote-
on-Chip are trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217,
7791419, 7881239, 7898322, 8222965.
* Eterna is Dust Networks’ low power radio SoC architecture.
LTC5800-IPM FEATURES
n Complete Radio Transceiver, Embedded Processor,
and Networking Software for Forming a Self-Healing
Mesh Network
n SmartMesh
®
Networks Incorporate:
n Time Synchronized Network-Wide Scheduling
n Per Transmission Frequency Hopping
n Redundant Spatially Diverse Topologies
n Network-Wide Reliability and Power Optimization
n NIST Certified Security
n SmartMesh Networks Deliver
n >99.999% Network Reliability Achieved in the
Most Challenging RF Environments
n Sub 50µA Routing Nodes
n Compliant to 6LoWPAN Internet Protocol (IP) and
IEEE 802.15.4e Standards
n Industry-Leading Low Power Radio Technology
n 4.5mA to Receive a Packet
n 9.7mA to Transmit at 8dBm
n PCB Module Versions Available (LTP5901/
LTP5902-IPM) with RF Modular Certifications
n 2.4GHz, IEEE 802.15.4e System-on-Chip
n 72-Pin 10mm × 10mm QFN Package
n Micrium µCOS-II Real Time Operating System based
On-Chip Software Development Kit
5800IPM TA01
20MHz
µCONTROLLERSENSOR
IN+
IN–
SPILTC2379-18
32kHz
LTC5800-IPM
UART
ANTENNA
20MHz
32kHz
LTC5800-IPR
UART
ANTENNA
HOST
APPLICATION
LTC5800-IPM
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TABLE OF CONTENTS
Network Features .......................................... 1
LTC5800-IPM Features .................................... 1
Typical Application ........................................ 1
Description.................................................. 1
SmartMesh Network Overview ........................... 3
Absolute Maximum Ratings .............................. 4
Order Information .......................................... 4
Pin Configuration .......................................... 4
Recommended Operating Conditions ................... 5
DC Characteristics ......................................... 5
Radio Specifications ...................................... 5
Radio Receiver Characteristics .......................... 6
Radio Transmitter Characteristics ....................... 6
Digital I/O Characteristics ................................ 7
Temperature Sensor Characteristics .................... 7
Analog Input Chain Characteristics ..................... 7
System Characteristics ................................... 8
UART AC Characteristics .................................. 8
TIMEn AC Characteristics ................................. 9
Radio_Inhibit AC Characteristics ....................... 10
Flash AC Characteristics ................................. 10
Flash SPI Slave AC Characteristics .................... 11
SPI Master AC Characteristics .......................... 12
I2C AC Characteristics .................................... 13
Typical Performance Characteristics ..................15
Pin Functions .............................................. 20
Operation................................................... 26
Power Supply ..........................................................26
Supply Monitoring and Reset .................................27
Precision Timing .....................................................27
Application Time Synchronization ..........................27
Time References ..................................................... 27
Radio ......................................................................28
UARTs .....................................................................28
Autonomous MAC ...................................................29
Security ..................................................................29
Temperature Sensor ...............................................30
Radio Inhibit ...........................................................30
Flash Programming ................................................30
FLASH Data Retention ............................................30
State Diagram ......................................................... 30
SPI Master .............................................................. 32
I2C Master ..............................................................33
1-Wire Master ......................................................... 33
Applications Information ................................ 33
Modes of Operation ................................................33
Slave Mode .............................................................33
Master Mode ..........................................................33
On-Chip SDK (OCSDK) ...........................................33
Regulatory and Standards Compliance ...................34
Soldering Information ............................................. 34
Related Documentation .................................. 35
Package Description ..................................... 36
Revision History .......................................... 37
Typical Application .......................................38
Related Parts .............................................. 38
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SMARTMESH NETWORK OVERVIEW
The Network Manager uses health reports to continually
optimize the network to maintain >99.999% data reliability
even in the most challenging RF environments.
The use of TSCH allows SmartMesh devices to sleep in
between scheduled communications and draw very little
power in this state. Motes are only active in time slots
where they are scheduled to transmit or receive, typically
resulting in a duty cycle of < 1%. The optimization soft-
ware in the Network Manager coordinates this schedule
automatically. When combined with the Eterna low power
radio, every mote in a SmartMesh network—even busy
routing ones—can run on batteries for years. By default,
all motes in a network are capable of routing traffic from
other motes, which simplifies installation by avoiding the
complexity of having distinct routers vs non-routing end
nodes. Motes may be configured as non-routing to further
reduce that particular mote’s power consumption and to
support a wide variety of network topologies.
A SmartMesh network consists of a self-forming multi-hop
mesh of nodes, known as motes, which collect and relay
data, and a network manager that monitors and manages
network performance and security, and exchanges data
with a host application.
SmartMesh networks communicate using a time slotted
channel hopping(TSCH) link layer, pioneered by Dust
Networks. In a TSCH network, all motes in the network
are synchronized to within less than a millisecond. Time
in the network is organized into time slots, which enables
collision-free packet exchange and per-transmission
channel-hopping. In a SmartMesh network, every device
has one or more parents (e.g. mote 3 has motes 1 and
2 as parents) that provide redundant paths to overcome
communications interruption due to interference, physical
obstruction or multi-path fading. If a packet transmission
fails on one path, the next retransmission may try on a
different path and different RF channel.
A network begins to form when the network manager
instructs its on-board Access Point (AP) radio to begin
sendingadvertisements—packets that contain information
that enables a device to synchronize to the network and
request to join. This message exchange is part of thesecu-
rityhandshake that establishes encrypted communications
between the manager or application, and mote. Once motes
have joined the network, they maintain synchronization
through time corrections when a packet is acknowledged.
At the heart of SmartMesh motes and network manag-
ers is the Eterna IEEE 802.15.4e System-on-Chip (SoC),
featuring Dust Networks’ highly integrated, low power
radio design, plus an ARM Cortex-M3 32-bit micropro-
cessor running SmartMesh networking software. The
SmartMesh networking software comes fully compiled
yet is configurable via a rich set of Application Program-
ming Interfaces (APIs) which allows a host application
to interact with the network, e.g. to transfer information
to a device, to configure data publishing rates on one or
more motes, or to monitor network state or performance
metrics. Data publishing can be uniform or different for
each device, with motes being able to publish infrequently
or faster than once per second as needed.
An ongoing discovery process ensures that the network
continually discovers new paths as the RF conditions
change. In addition, each mote in the network tracks per-
formance statistics (e.g. quality of used paths, and lists of
potential paths) and periodically sends that information
to the network manager in packets called health reports.
ALL NODES ARE ROUTERS.
THEY CAN TRANSMIT AND RECEIVE.
THIS NEW NODE CAN JOIN
ANYWHERE BECAUSE ALL
NODES CAN ROUTE.
SNO 02
HOST
APPLICATION
AP
SNO 01
NETWORK MANAGER
Mote
2
Mote
1
Mote
3
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage on VSUPPLY .................................. 4.20V
Input Voltage on AI_0/1/2/3 Inputs ........................1.80V
Voltage on Any Digital I/O Pin ...–0.3V to VSUPPLY + 0.3V
Input RF Level ...................................................... 10dBm
Storage Temperature Range (Note 3) ..... –55°C to 125°C
Junction Temperature (Note 3) ............................. 125°C
Operating Temperature Range
LTC5800I .............................................–40°C to 85°C
LTC5800H .......................................... –55°C to 105°C
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions
be observed when handling the LTC5800-IPM.
(Note 1)
TOP VIEW
WR PACKAGE
72-LEAD PLASTIC QFN
RADIO_INHIBIT 1
CAP_PA_1P 2
CAP_PA_1M 3
CAP_PA_2M 4
CAP_PA_2P 5
CAP_PA_3P 6
CAP_PA_3M 7
CAP_PA_4M 8
CAP_PA_4P 9
VDDPA 10
LNA_EN / GPIO17 11
RADIO_TX / GPIO18 12
RADIO_TXn / GPIO19 13
ANTENNA 14
AI_0 15
AI_1 16
AI_3 17
AI_2 18
OSC_32K_XOUT 19
OSC_32K_XIN 20
VBGAP 21
RESETn 22
TDI 23
TDO 24
TMS 25
TCK 26
DP4 (GPIO23) 27
OSC_20M_XIN 28
OSC_20M_XOUT 29
VDDA 30
VCORE 31
VOSC 32
DP3 (GPIO22) / TIMER8_IN 33
DP2 (GPIO21) / LPTIMER_IN 34
SLEEPn / GPIO14 35
DP0 (GPIO0) / SPIM_SS_2n 36
54 VPP
53 SPIS_SSn / SDA
52 SPIS_SCK / SCL
51 SPIS_MOSI / GPIO26 / UARTC1_RX
50 SPIS_MISO / 1_WIRE / UARTC1_TX
49 PWM0 / GPIO16
48 DP1 (GPIO20) / TIMER16_IN
47 SPIM_SS_0n / GPIO12
46 SPIM_SS_1n / GPIO13
45 IPCS_SSn / GPIO3
44 IPCS_SCK / GPIO4
43 SPIM_SCK / GPIO9
42 IPCS_MOSI / GPIO5
41 SPIM_MOSI / GPIO10
40 IPCS_MISO / GPIO6
39 SPIM_MISO / GPIO11
38 UARTCO_RX
37 UARTCO_TX
EXPOSED PAD
(GND)
72 TIMEn
71 UART_TX
70 UART_TX_CTSn
69 UART_TX_RTSn
68 UART_RX
67 UART_RX_CTSn
66 UART_RX_RTSn
65 VSUPPLY
64 CAP_PRIME_1P
63 CAP_PRIME_1M
62 CAP_PRIME_2M
61 CAP_PRIME_2P
60 CAP_PRIME_3P
59 CAP_PRIME_3M
58 CAP_PRIME_4M
57 CAP_PRIME_4P
56 VPRIME
55 FLASH_P_ENn
TJMAX = 125°C, θJA = 21°C/W, θJCbottom = 0.6°C/W
EXPOSED PAD IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC5800IWR-IPMA#PBF LTC5800IWR-IPMA#PBF LTC5800WR-IPMA 72-Lead (10mm × 10mm × 0.85mm) Plastic QFN –40°C to 85°C
LTC5800HWR-IPMA#PBF LTC5800HWR-IPMA#PBF LTC5800WR-IPMA 72-Lead (10mm × 10mm × 0.85mm) Plastic QFN –55°C to 105°C
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Pin functions shown in italics are currently not supported in software.
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RECOMMENDED OPERATING CONDITIONS
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSUPPLY Supply Voltage Including Noise and Load Regulation l 2.1 3.76 V
Supply Noise Requires Recommended RLC Filter, 50Hz to 2MHz l250 mV
Operating Relative Humidity Non-condensing l10 90 % RH
Temperature Ramp Rate While Operating in Network l–8 +8 °C/min
DC CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
OPERATION/STATE CONDITIONS MIN TYP MAX UNITS
Reset After Power-on Reset 1.2 µA
Power-on Reset During Power-on Reset, Maximum 750µs + VSUPPLY Rise Time
from 1V to 1.9V
12 mA
Doze RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Active
1.2 µA
Deep Sleep RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Inactive
0.8 µA
In-Circuit Programming RESETn and FLASH_P_ENn Asserted, IPCS_SCK @ 8MHz 20 mA
Peak Operating Current
+8dBm
+0dBm
System Operating at 14.7MHz, Radio Transmitting, During Flash
Write. Maximum duration 4.33 ms.
30
26
mA
mA
Active ARM Cortex M3, RAM and Flash Operating, Radio and All Other
Peripherals Off. Clock Frequency of CPU and Peripherals Set to
7.3728MHz, VCORE = 1.2V
1.3 mA
Flash Write Single Bank Flash Write 3.7 mA
Flash Erase Single Bank Page or Mass Erase 2.5 mA
Radio Tx
+0dBm (LTC5800I)
+0dBm (LTC5800H)
+8dBm (LTC5800I)
+8dBm (LTC5800H)
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
5.4
5.6
9.7
9.9
mA
mA
mA
mA
Radio Rx
LTC5800I
LTC5800H
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
4.5
4.7
mA
mA
RADIO SPECIFICATIONS
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Frequency Band l2.4000 2.4835 GHz
Number of Channels l15
Channel Separation l5 MHz
Channel Center Frequency Where k = 11 to 25, as Defined by IEEE.802.15.4 l2405 + 5•(k-11) MHz
Raw Data Rate l250 kbps
Antenna Pin ESD Protection HBM Per JEDEC JESD22-A114F ±1000 V
Range (Note 4)
Indoor
Outdoor
Free Space
25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m
Above Ground
100
300
1200
m
m
m
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RADIO RECEIVER CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Receiver Sensitivity Packet Error Rate (PER) = 1% (Note 5) –93 dBm
Receiver Sensitivity PER = 50% –95 dBm
Saturation Maximum Input Level the Receiver Will
Properly Receive Packets
0 dBm
Adjacent Channel Rejection (High Side) Desired Signal at -82dBm, Adjacent Modulated Channel 5MHz
Above the Desired Signal, PER = 1% (Note 5)
22 dBc
Adjacent Channel Rejection (Low Side) Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Below the Desired Signal, PER = 1% (Note 5)
19 dBc
Alternate Channel Rejection
(High Side)
Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Above the Desired Signal, PER = 1% (Note 5)
40 dBc
Alternate Channel Rejection (Low Side) Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Below the Desired Signal, PER = 1% (Note 5)
36 dBc
Second Alternate Channel Rejection Desired Signal at –82dBm, Second Alternate Modulated Channel
Either 15MHz Above or Below, PER = 1% (Note 5)
42 dBc
Co-Channel Rejection Desired Signal at –82dBm, Undesired Signal is an 802.15.4
Modulated Signal at the Same Frequency, PER = 1%
–6 dBc
LO Feed Through –55 dBm
Frequency Error Tolerance (Note 6) ±50 ppm
Symbol Error Tolerance ±50 ppm
Received Signal Strength Indicator
(RSSI) Input Range
–90 to –10 dBm
RSSI Accuracy ±6 dB
RSSI Resolution 1 dB
RADIO TRANSMITTER CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Power
High Calibrated Setting
Low Calibrated Setting
Delivered to a 50Ω load
8
0
dBm
dBm
Spurious Emissions
30MHz to 1000MHz
1GHz to 12.75GHz
2.4GHz ISM Upper Band Edge (Peak)
2.4GHz ISM Upper Band Edge (Average)
2.4GHz ISM Lower Band Edge
Conducted Measurement with a 50Ω Single-Ended Load,
+8dBm Output Power. All Measurements Made with Max
Hold. RF Implementation Per Eterna Reference Design
RBW = 120kHz, VBW = 100Hz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 10Hz
RBW = 100kHz, VBW = 100kHz
<–70
–45
–37
–49
–45
dBm
dBm
dBm
dBm
dBc
Harmonic Emissions
2nd Harmonic
3rd Harmonic
Conducted Measurement Delivered to a 50Ω Load,
Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz,
RF Implementation Per Eterna Reference Design
–50
–45
dBm
dBm
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DIGITAL I/O CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
VIL Low Level Input Voltage l–0.3 0.6 V
VIH High Level Input Voltage (Note 8) lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
VOL Low Level Output Voltage Type 1, IOL(MAX) = 1.2mA l0.4 V
Low Level Output Voltage Type 2, Low Drive, IOL(MAX) = 2.2mA l0.4 V
Low Level Output Voltage Type 2, High Drive, IOL(MAX) = 4.5mA l0.4 V
VOH High Level Output Voltage Type 1, IOH(MAX) = –0.8mA lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
High Level Output Voltage Type 2, Low Drive, IOH(MAX) = –1.6mA lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
High Level Output Voltage Type 2, High Drive, IOH(MAX) = –3.2mA lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
Input Leakage Current Input Driven to VSUPPLY or GND 50 nA
Pull-Up/Pull-Down Resistance 50 kΩ
TEMPERATURE SENSOR CHARACTERISTICS
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Offset Temperature Offset Error at 25°C ±0.25 °C
Slope Error ±0.033 °C/°C
ANALOG INPUT CHAIN CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Variable Gain Amplifier
Gain
Gain Error
1
8
2
%
DNL
Offset-Digital to Analog Converter (DAC)
Full-Scale
Resolution
Differential Non-Linearity
1.80
4
2.7
V
Bits
mV
DNL
INL
Analog to Digital Converter (ADC)
Full-Scale, Signal
Resolution
Offset
Differential Non-Linearity
Integral Non-Linearity
Settling Time
Conversion Time
Current Consumption
Mid-Scale
10kΩ Source Impedance
1.80
1.8
1.4
40
12
1
1
10
20
V
mV
LSB
LSB
LSB
µs
µs
µA
Analog Inputs (Note 8)
Load
Series Input Resistance
20
1
pF
kΩ
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SYSTEM CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Doze to Active State Transition 5 µs
Doze to Radio Tx or Rx 1.2 ms
QCCA Charge to Sample RF Channel RSSI Charge Consumed Starting from Doze State
and Completing an RSSI Measurement
4 µC
QMAX Largest Atomic Charge Operation Flash Erase, 21ms Max Duration l200 µC
RESETn Pulse Width l125 µs
UART AC CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Permitted RX Baud Rate Error Both Application Programming
Interface (API) and Command Line
Interface (CLI) UARTs
l–2 2 %
Generated TX Baud Rate Error Both API and CLI UARTs l–1 1 %
tRX_RTS to RX_CTS Assertion of UART_RX_RTSn to Assertion
of UART_RX_CTSn, or Negation of UART_
RX_RTSn to Negation of UART_RX_CTSn
l0 2 ms
tRX_CTS to RX Assertion of UART_RX_CTSn to Start of
Byte
l0 20 ms
tEOP to RX_RTS End of Packet (End of the Last Stop Bit) to
Negation of UART_RX_RTSn
l0 22 ms
tBEG_TX_RTS to TX_CTS Assertion of UART_TX_RTSn to Assertion
of UART_TX_CTSn
l0 22 ms
tEND_TX_RTS to TX_CTS Negation of UART_TX_RTSn to Negation
of UART_TX_CTSn
Mode 2 Only 22 ms
tEND_TX_CTS to TX_RTS Negation of UART_TX_CTSn to Negation
of UART_TX_RTSn
Mode 4 Only 2 Bit Period
tTX_CTS to TX Assertion of UART_TX_CTSn to Start of
Byte
l0 2 Bit Period
tEOP to TX_RTS End of Packet (End of the Last Stop Bit) to
Negation of UART_TX_RTSn
l0 1 Bit Period
tRX_INTERBYTE Receive Inter-Byte Delay l100 ms
tRX_INTERPACKET Receive Inter-Packet Delay l20 ms
tTX_INTERPACKET Transmit Inter-Packet Delay l1 Bit Period
tTX to TX_CTS Start of Byte to Negation of
UART_TX_CTSn
l0 ns
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UART AC CHARACTERISTICS
TIMEn AC CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSTROBE TIMEn Signal Strobe Width l125 µs
tRESPONSE Delay from Rising Edge of TIMEn to the Start
of Time Packet on API UART
l0 100 ms
tTIME_HOLD Delay from End of Time Packet on API UART
to Falling Edge of Subsequent TIMEn
l0 ns
Timestamp Resolution (Note 10) l1 µs
Network-Wide Time Accuracy (Note 11) l±5 µs
5800IPM F01
UART_RX_RTSn
UART_RX_CTSn
tRX_RTS to RX_CTS
UART_RX
UART_TX_RTSn
UART_TX_CTSn
UART_TX
tEOP to RX_RTS
tRX_RTS to RX_CTS
tRX_CTS to RX tRX_INTERBYTE
BYTE 0 BYTE 1
BYTE 0 BYTE 1
tTX_RTS to TX_CTS tEND_TX_CTS to TX_RTS
tTX_CTS to TX
tTX to TX_CTS
tEOP to TX_RTS
tEND_TX_RTS to TX_CTS
tTX_INTERPACKET
tRX_INTERPACKET
Figure 1. API UART Timing
5800IPM F02
TIMEn
UART_TX
tSTROBE tTIME_HOLD
tRESPONSE
TIME INDICATION PAYLOAD
Figure 2. Timestamp Timing
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RADIO_INHIBIT AC CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tRADIO_OFF Delay from Rising Edge of
RADIO_INHIBIT to Radio Disabled
l20 ms
tRADIO_INHIBIT_STROBE Maximum RADIO_INHIBIT Strobe Width l2 s
FLASH AC CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tWRITE Time to Write a 32-Bit Word (Note 12) l21 µs
tPAGE_ERASE Time to Erase a 2kB Page (Note 12) l21 ms
tMASS_ERASE Time to Erase 256kB Flash Bank (Note 12) l21 ms
Data Retention 25°C
85°C
105°C
100
20
8
Years
Years
Years
5800IPM F03
RADIO_INHIBIT
RADIO STATE
tRADIO_OFF
tRADIO_INHIBIT_STROBE
ACTIVE/OFF ACTIVE/OFFOFF
Figure 3. RADIO_INHIBIT Timing
LTC5800-IPM
11
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For more information www.linear.com/LTC5800-IPM
5800IPM F04
IPCS_SCK
IPCS_MOSI
IPCS_SSn
RESETn
FLASH_P_ENn
tFP_EN_TO_RESET
tFP_ENTER
tSSS
tCK
tSSH
tFP_EXIT
tDIS
tDIH
tDOV tOFF
IPCS_MISO
Figure 4. Flash Programming Interface Timing
FLASH SPI SLAVE AC CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tFP_EN_to_RESET Setup from Assertion of FLASH_P_ENn to
Assertion of RESETn
l0 ns
tFP_ENTER Delay from the Assertion RESETn to the
First Falling Edge of IPCS_SSn
l125 µs
tFP_EXIT Delay from the Completion of the Last
Flash SPI Slave Transaction to the
Negation of RESETn and FLASH_P_ENn
(Note 13)
l10 µs
tSSS IPCS_SSn Setup to the Leading Edge of
IPCS_SCK
l15 ns
tSSH IPCS_SSn Hold from Trailing Edge of
IPCS_SCK
l15 ns
tCK IPCS_SCK Period l300 ns
tDIS IPCS_MOSI Data Setup l15 ns
tDIH IPCS_MOSI Data Hold l5 ns
tDOV IPCS_MISO Data Valid l–5 30 ns
tOFF IPCS_MISO Data Tri-State from Trailing
Edge of IPCS_SSn
l0 30 ns
LTC5800-IPM
12
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5800IPM F??
SPIM_SCK
SPIM_MISO
SPIM_SSXn
tSSS
tCK
tSSH
CPOL = 0
CPOL = 1
SPIM_MOSI
tDIS
tDIH
tDOV tOFF
Figure 6. SPI Master Timing - CPHA = 1
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSSS SPIM_SSXn Setup to the Leading Edge of
SPIM_SCK
ltCK-30 ns
tSSH SPIM_SSXn Hold from Trailing Edge of
SPIM_SCK
ltCK-30 ns
tCK SPIM_SCK Period l268 ns
tDIS SPIM_MOSI Data Setup l30 ns
tDIH SPIM_MOSI Data Hold l5 ns
tDOV SPIM_MISO Data Valid l-5 30 ns
tOFF SPIM_MISO Data Tri-State from Trailing
Edge of SPIM_SSXn
l0 30 ns
SPI MASTER AC CHARACTERISTICS
5800IPM F??
SPIM_SCK
SPIM_MISO
SPIM_SSXn
tSSS
tCK
tSSH
CPOL = 0
CPOL = 1
SPIM_MOSI
tDIS
tDIH
tDOV tOFF
Figure 5. SPI Master Timing - CPHA = 0
LTC5800-IPM
13
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The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL SCL Frequency 184kHz Operation
92kHz Operation
l184.3
92.2
188
94
kHz
tHD_STA Start Hold Time (SCL from SDA) 184kHz Operation
92kHz Operation
l1
2
µs
tSU_STA Setup Time for a Repeated Start 184kHz Operation, 750ns SCL Rise
Time
92kHz Operation, 1.5µs SCL Rise
Time
l300
600
ns
tHD_DAT Data Hold Time 184kHz Operation
92kHz Operation
l1
2
µs
tSU_DAT Data Setup Time 184kHz Operation
92kHz Operation
l1
2
µs
tSU_STO Setup Time for Stop Condition 184kHz Operation
92kHz Operation
l1
2
µs
SCL
SDA
tHD_STA tHD_STA
tSU_STA
tHD_DAT
tSU_DAT tHD_DAT
I2C AC CHARACTERISTICS
Figure 7. I2C Master Timing
LTC5800-IPM
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ESD (electrostatic discharge) sensitive device. ESD protection
devices are used extensively internal to Eterna. However, high electrostatic
discharge can damage or degrade the device. Use proper ESD handling
precautions.
Note 3: Extended storage at high temperature is discouraged, as this
negatively affects the data retention of Eterna’s calibration data. See the
FLASH Data Retention section for details.
Note 4: Actual RF range is subject to a number of installation-specific
variables including, but not restricted to ambient temperature, relative
humidity, presence of active interference sources, line-of-sight obstacles,
and near-presence of objects (for example, trees, walls, signage, and so
on) that may induce multipath fading. As a result, range varies.
Note 5: As Specified by IEEE Std. 802.15.4-2006: Wireless Medium
Access Control (MAC) and Physical Layer (PHY) Specifications for
Low-Rate Wireless Personal Area Networks (LR-WPANs)
http://standards.ieee.org/findstds/standard/802.15.4-2011.html
Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a
frequency tolerance of better than ±40 ppm.
Note 7: Per pin IO types are provided in the Pin Functions section.
Note 8: VIH maximum voltage input must respect the VSUPPLY maximum
voltage specification.
Note 9: The analog inputs to the ADC can be modeled as a series resistor
to a capacitor. At a minimum the entire circuit, including the source
impedance for the signal driving the analog input should be designed
to settle to within ¼ LSB within the sampling window to match the
performance of the ADC.
Note 10: See the SmartMesh IP Mote API Guide for the timeIndication
notification definition.
Note 11: Network time accuracy is a statistical measure and varies over
the temperature range, reporting rate and the location of the device
relative to the manager in the network. See the Typical Performance
Characteristics section for a more detailed description.
Note 12: Code execution from flash banks being written or erased is
suspended until completion of the flash operation.
Note 13: Guaranteed by design. Not production tested.
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tRSTL Reset Low l527 556 584 µs
tPS Presense Sample l60.1 69.4 79 µs
tBIT_PERIOD 1_WIRE Data Bit Period l82 86.8 92 µs
tLOW0 1_WIRE Write Data 0 Low Width l65 69 82 µs
tLOW1 1_WIRE Write Data 1 Low Width l8.2 8.7 9.2 µs
tLOWR 1_WIRE Read Data Low Width l8.2 8.7 9.2 µs
tRS Read Sample from 1_WIRE Low l13.2 14.6 15.0 µs
1_WIRE
tRSTL tPS
1_WIRE tLOW1
tBIT_PERIOD
1_WIRE tLOW0
tBIT_PERIOD
1_WIRE
tLOWR
tBIT_PERIOD
tRS
Figure 8. 1-Wire Master Timing
1-WIRE MASTER
LTC5800-IPM
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TYPICAL PERFORMANCE CHARACTERISTICS
Network motes typically route through at least two parents
the traffic destined for the manager. The supply current
graphs shown in Figure 9 include a parameter called de-
scendants. In these graphs the term descendants is short
for traffic-weighted descendants and refers to an amount
of activity equivalent to the number of descendants if all
of the network traffic directed to the mote in question.
Generally the number of descendants of a parent is more,
typically 2x or more, than the number of traffic-weighted
descendants. For example, with reference to Figure 10 mote
P1 has 0.75 traffic-weighted descendants. To obtain this
value notice that mote D1 routes half its packets through
mote P1 adding 0.5 to the traffic-weighted descendant
value; the other half of D1’s traffic is routed through its
other parent, P2. Mote D2 routes half its packets through
mote D1 (the other half going through parent P3), which
we know routes half its packets to mote P1, adding another
0.25 to the traffic-weighted descendant value for a total
traffic-weighted descendant value of 0.75.
As described in the Application Time Synchronization
section, Eterna provides two mechanisms for applications
to maintain a time base across a network. The synchro-
nization performance plots that follow were generated
using the more precise TIMEn input. Publishing rate is
the rate a mote application sends upstream data. Syn-
chronization improves as the publishing rate increases.
Baseline synchronization performance is provided for a
network operating with a publishing rate of zero. Actual
performance for applications in network will improve
as publishing rates increase. All synchronization testing
was performed with the 1-hop mote inside a temperature
chamber. Timing errors due to temperature changes and
temperature differences both between the manager and
this mote and between this mote and its descendents
therefore propagated down through the network. The syn-
chronization of the 3-hop and 5-hop motes to the manager
was then affected by the temperature ramps even though
they were at room temperature. For 2°C/minute testing
the temperature chamber was cycled between –40°C and
85°C at this rate for 24 hours. For 8°C/minute testing, the
temperature chamber was rapidly cycled between 85°C and
45°C for 8 hours, followed by rapid cycling between –5°C
and 45°C for 8 hours, and lastly, rapid cycling between
–40°C and 15°C for 8 hours.
Figure 10. Example Network Graph
REPORTING INTERVAL (sec)
0
0
MEDIAN LATENCY (sec)
1.0
1.5
2.0
4.0
5800IPM F05b
0.5
3.0
3.5
2.5
30
10 20
5 HOPS
4 HOPS
3 HOPS
2 HOPS
1 HOP
REPORTING INTERVAL (sec)
0
0
SUPPLY CURRENT (µA)
100
5800IPM F05c
200
30
10 20
5 DESCENDANTS
2 DESCENDANTS
1 DESCENDANTS
0 DESCENDANTS
Figure 9
TEMPERATURE (°C)
–60
0
SUPPLY CURRENT (µA)
20
60
80
100
120
140
5800IPM F05a
40
–10 40 90
2 DESCENDANTS 5sec REPORTING
5 DESCENDANTS 30sec REPORTING
2 DESCENDANTS 30sec REPORTING
0 DESCENDANTS 5sec REPORTING
0 DESCENDANTS 30sec REPORTING
MANAGER
1 HOP
2 HOP
3 HOP
5800IPM F06
P1
P2
P3
D1
D2
LTC5800-IPM
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TYPICAL PERFORMANCE CHARACTERISTICS
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, Room Temperature
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, Room Temperature
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, Room Temperature
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 2°C/Min
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 2°C/Min
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 2°C/Min
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 8°C/Min
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 8°C/Min
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 8°C/Min
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
30
40
50
60
–30
5800IPM G01
20
40
–20 0 10 20 30
–10
µ = 0.2
σ = 0.9
N = 89700
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
5
15
20
25
30
–30
5800IPM G02
10
40
–20 0 10 20 30
–10
µ = –0.2
σ = 1.7
N = 89699
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
2
6
8
10
12
14
–30
5800IPM G03
4
40
–20 0 10 20 30
–10
µ = –0.2
σ = 3.6
N = 89698
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
5
10
15
20
–30
5800IPM G04
40
–20 0 10 20 30
–10
µ = 1.5
σ = 3.3
N = 93812
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
2
4
6
8
10
12
14
–30
5800IPM G05
40
–20 0 10 20 30
–10
µ = 0.9
σ = 3.9
N = 93846
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
2
4
6
8
10
12
–30
5800IPM G07
40
–20 0 10 20 30
–10
µ = 3.6
σ = 5.0
N = 88144
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
2
4
6
8
10
14
12
–30
5800IPM G08
40
–20 0 10 20 30
–10
µ = 1.1
σ = 3.8
N = 88179
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
2
4
6
8
10
14
12
–30
5800IPM G08
40
–20 0 10 20 30
–10
µ = 1.1
σ = 3.8
N = 88179
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
2
4
6
8
10
14
12
–30
5800IPM G09
40
–20 0 10 20 30
–10
µ = 1.0
σ = 7.4
N = 88178
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
1
2
3
4
5
6
7
–30
5800IPM G06
40
–20 0 10 20 30
–10
µ = 1.0
σ = 7.7
N = 93845
LTC5800-IPM
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TYPICAL PERFORMANCE CHARACTERISTICS
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, Room Temperature
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, Room Temperature
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, Room Temperature
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, 2°C/Min
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, 2°C/Min
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, 2°C/Min
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, 8°C/Min
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, 8°C/Min
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, 8°C/Min
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
20
30
40
60
50
–30
5800IPM G10
40
–20 0 10 20 30
–10
µ = 0.0
σ = 1.2
N = 22753
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
20
30
40
60
50
–30
5800IPM G11
40
–20 0 10 20 30
–10
µ = –0.2
σ = 1.2
N = 17008
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
20
30
40
60
50
–30
5800IPM G12
40
–20 0 10 20 30
–10
µ = –0.2
σ = 1.2
N = 17007
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
5
15
20
35
30
25
–30
5800IPM G13
40
–20 0 10 20 30
–10
µ = 0.5
σ = 1.9
N = 85860
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
5
15
20
45
35
40
30
25
–30
5800IPM G14
40
–20 0 10 20 30
–10
µ = 0.1
σ = 1.5
N = 85858
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
5
15
20
35
30
25
–30
5800IPM G15
40
–20 0 10 20 30
–10
µ = 0.1
σ = 1.5
N = 85855
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
20
30
60
50
40
–30
5800IPM G16
40
–20 0 10 20 30
–10
µ = 0.2
σ = 1.4
N = 33932
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
20
30
60
50
40
–30
5800IPM G17
40
–20 0 10 20 30
–10
µ = 0.0
σ = 1.3
N = 33930
SYNCHRONIZATION ERROR (µs)
–40
0
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
20
30
50
40
–30
5800IPM G18
40
–20 0 10 20 30
–10
µ = –1.0
σ = 1.3
N = 33929
LTC5800-IPM
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As described in the SmartMesh Network Overview sec-
tion, devices in network spend the vast majority of their
time inactive in their lowest power state (doze). On a
synchronous schedule a mote will wake to communicate
with another mote. Regularly occurring sequences which
wake, perform a significant function and return to sleep
are considered atomic. These operations are considered
atomic as the sequence of events can not be separated
into smaller events while performing a useful function.
For example, transmission of a packet over the radio is an
atomic operation. Atomic operations may be characterized
in either charge or energy. In a time slot where a mote
successfully sends a packet, an atomic transmit includes
setup prior to sending the message, sending the message,
receiving the acknowledgment and the post processing
needed as a result of the message being sent. Similarly in
a time slot when a mote successfully receives a packet, an
atomic receive includes setup prior to listening, listening
until the start of the packet transition, receiving the packet,
sending the acknowledgement and post processing re-
quired due to the arrival of the packet.
To ensure reliability each mote in the network is provided
multiple time slots for each packet it nominally will send
and forward. The time slots are assigned to communicate
upstream, toward the manager, with at least two different
motes. When combined with frequency hopping this pro-
vides temporal, spatial and spectral redundancy. Given this
approach a mote will often listen for a message that it will
never receive, since the time slot is not being used by the
transmitting mote. It has already successfully transmitted
the packet. Since typically 3 time slots are scheduled for
every 1 packet to be sent or forwarded, motes will perform
more of these atomic “idle listens” than atomic transmit or
atomic receive sequences. Examples of transmit, receive
and idle listen atomic operations are shown in Figure 11.
TYPICAL PERFORMANCE CHARACTERISTICS
LTC5800-IPM
19
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11
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PIN FUNCTIONS
The following table organizes the pins by functional
groups. For those I/O with multiple functions the alternate
functions are shown on the second and third line in their
respective row. The No column provides the pin number.
The second column lists the function. The Type column
lists the I/O type. The I/O column lists the direction of the
signal relative to Eterna. The Pull column shows which
signals have a fixed passive pull-up or pull-down. The
Description column provides a brief signal description.
NO POWER SUPPLY TYPE I/O PULL DESCRIPTION
P GND Power - - Ground Connection, P = QFN Paddle
2 CAP_PA_1P Power - - PA DC/DC Converter Capacitor 1 Plus Terminal
3 CAP_PA_1M Power - - PA DC/DC Converter Capacitor 1 Minus Terminal
4 CAP_PA_2M Power - - PA DC/DC Converter Capacitor 2 Minus Terminal
5 CAP_PA_2P Power - - PA DC/DC Converter Capacitor 2 Plus Terminal
6 CAP_PA_3P Power - - PA DC/DC Converter Capacitor 3 Plus Terminal
7 CAP_PA_3M Power - - PA DC/DC Converter Capacitor 3 Minus Terminal
8 CAP_PA_4M Power - - PA DC/DC Converter Capacitor 4 Minus Terminal
9 CAP_PA_4P Power - - PA DC/DC Converter Capacitor 4 Plus Terminal
10 VDDPA Power - - Internal Power Amplifier Power Supply, Bypass
30 VDDA Power - - Regulated Analog Supply, Bypass
31 VCORE Power - - Regulated Core Supply, Bypass
32 VOSC Power - - Regulated Oscillator Supply, Bypass
54 VPP Test Internal Regulator Test Port
56 VPRIME Power - - Internal Primary Power Supply, Bypass
57 CAP_PRIME_4P Power - - Primary DC/DC Converter Capacitor 4 Plus Terminal
58 CAP_PRIME_4M Power - - Primary DC/DC Converter Capacitor 4 Minus Terminal
59 CAP_PRIME_3M Power - - Primary DC/DC Converter Capacitor 3 Minus Terminal
60 CAP_PRIME_3P Power - - Primary DC/DC Converter Capacitor 3 Plus Terminal
61 CAP_PRIME_2P Power - - Primary DC/DC Converter Capacitor 2 Plus Terminal
62 CAP_PRIME_2M Power - - Primary DC/DC Converter Capacitor 2 Minus Terminal
63 CAP_PRIME_1M Power - - Primary DC/DC Converter Capacitor 1 Minus Terminal
64 CAP_PRIME_1P Power - - Primary DC/DC Converter Capacitor 1 Plus Terminal
65 VSUPPLY Power - - Power Supply Input to Eterna
NO RADIO TYPE I/O PULL DESCRIPTION
1 RADIO_INHIBIT 1 (Note 14) I - Radio Inhibit
11 LNA_EN
GPIO17
1 O
I/O
-
-
External LNA Enable
General Purpose Digital I/O
12 RADIO_TX
GPIO18
1O
I/O
-
-
Radio TX Active (External PA Enable/Switch Control)
General Purpose Digital I/O
13 RADIO_TXn
GPIO19
1 O
I/O
-
-
Radio TX Active (External PA Enable/Switch Control), Active Low
General Purpose Digital I/O
14 ANTENNA - - - Single-Ended Antenna Port, 50Ω
Pin functions shown in italics are currently not supported in software.
LTC5800-IPM
21
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PIN FUNCTIONS
Pin functions shown in italics are currently not supported in software.
NO ANALOG TYPE I/O PULL DESCRIPTION
15 AI_0 Analog I - Analog Input 0
16 AI_1 Analog I - Analog Input 1
17 AI_3 Analog I - Analog Input 3
18 AI_2 Analog I - Analog Input 2
NO CRYSTALS TYPE I/O PULL DESCRIPTION
19 OSC_32K_XOUT Crystal I - 32 kHz Crystal Xout
20 OSC_32K_XIN Crystal I - 32 kHz Crystal Xin
28 OSC_20M_XIN Crystal I - 20 MHz Crystal Xin
29 OSC_20M_XOUT Crystal I - 20 MHz Crystal Xout
NO RESET TYPE I/O PULL DESCRIPTION
22 RESETn 1 I UP Reset Input, Active Low
NO JTAG TYPE I/O PULL DESCRIPTION
23 TDI 1 I UP JTAG Test Data In
24 TDO 1 O - JTAG Test Data Out
25 TMS 1 I UP JTAG Test Mode Select
26 TCK 1 I DOWN JTAG Test Clock
NO GPIOS (NOTE 14) TYPE I/O PULL DESCRIPTION
27 DP4 (GPIO23) 1 I/O - General Purpose Digital I/O
33 DP3 (GPIO22)
TIMER8_EXT
1 I/O
I
-
-
General Purpose Digital I/O
External Input to 8-Bit Timer/Counter
34 DP2 (GPIO21)
LPTIMER_EXT
1 I/O
I
-
-
General Purpose Digital I/O
External Input to Low Power Timer/Counter
36 DP0 (GPIO0)
SPIM_SS_2n
1 I/O
O
-
-
General Purpose Digital I/O
SPI Master Slave Select 2, Active Low
48 DP1 (GPIO20)
TIMER16_EXT
1 I/O
I
-
-
General purpose digital I/O
External Input to 16-Bit Timer/Counter
NO SPECIAL PURPOSE TYPE I/O PULL DESCRIPTION
35 SLEEPn
GPIO14
1 (Note 14) I
I/O
-
-
Deep Sleep, Active Low
General Purpose Digital I/O
49 PWM0
TIMER16_OUT
GPIO16
2O
O
I/O
-
-
-
Pulse Width Modulator 0
16-Bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
72 TIMEn 1 (Note 14) I - Time Capture Request, Active Low
NO CLI TYPE I/O PULL DESCRIPTION
37 UARTC0_TX 2 O - CLI UART 0 Transmit
38 UARTC0_RX 1 I UP CLI UART 0 Receive
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PIN FUNCTIONS
Pin functions shown in italics are currently not supported in software.
NO SPI MASTER TYPE I/O PULL DESCRIPTION
39 SPIM_MISO
GPIO11
1 I
I/O
-
-
SPI Master (MISO) Master In Slave Out Port
General Purpose Digital I/O
41 SPIM_MOSI
GPIO10
2 O
I/O
-
-
SPI Master (MOSI) Master Out Slave In Port
General Purpose Digital I/O
43 SPIM_SCK
GPIO9
2 O
I/O
-
-
SPI Master (SCK) Serial Clock Port
General Purpose Digital I/O
46 SPIM_SS_1n
GPIO13
1 O
I/O
-
-
SPI Master Slave Select 1, Active Low
General Purpose Digital I/O
47 SPIM_SS_0n
GPIO12
1 O
I/O
-
-
SPI Master Slave Select 0, Active Low
General Purpose Digital I/O
NO IPCS SPI/FLASH PROGRAMMING (NOTE 16) TYPE I/O PULL DESCRIPTION
40 IPCS_MISO
TIMER16_OUT
GPIO6
2 O
O
I/O
-
-
-
SPI Flash Emulation (MISO) Master In Slave Out Port
16-Bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
42 IPCS_MOSI
TIMER16_EXT
GPIO5
1 I
I
I/O
-
-
-
SPI Flash Emulation (MOSI) Master Out Slave In Port
External Input to 16-bit Timer/Counter
General Purpose Digital I/O
44 IPCS_SCK
TIMER8_EXT
GPIO4
1 I
I
I/O
-
-
-
SPI Flash Emulation (SCK) Serial Clock Port
External Input to 8-Bit Timer/Counter
General Purpose Digital I/O
45 IPCS_SSn
LPTIMER_EXT
GPIO3
1 I
I
I/O
-
-
-
SPI Flash Emulation Slave Select, Active Low
External Input to Low Power Timer/Counter
General Purpose Digital I/O
55 FLASH_P_ENn 1 I UP Flash Program Enable, Active Low
NO I2C/1-WIRE/SPI SLAVE TYPE I/O PULL DESCRIPTION
50 SPIS_MISO
UARTC1_TX
1_WIRE
2O
O
I/O
-
-
-
SPI Slave (MISO) Master In Slave Out Port
CLI UART 1 Transmit
1 Wire Master
51 SPIS_MOSI
UARTC1_RX
GPIO26
1I
I
I/O
-
-
-
SPI Slave (MOSI) Master Out Slave In Port
CLI UART 1 Receive
General Purpose Digital I/O
52 SPIS_SCK
SCL
2I
I/O
-
-
SPI Slave (SCK) Serial Clock Port
I2C Serial Clock
53 SPIS_SSn
SDA
2I
I/O
-
-
SPI Slave Select, Active Low
I2C Serial Data
NO API UART TYPE I/O PULL DESCRIPTION
66 UART_RX_RTSn 1 (Note 14) I - UART Receive (RTS) Request to Send, Active Low
67 UART_RX_CTSn 1 O - UART Receive (CTS) Clear to Send, Active Low
68 UART_RX 1 (Note 14) I - UART Receive
69 UART_TX_RTSn 1 O - UART Transmit (RTS) Request to Send, Active Low
70 UART_TX_CTSn 1 (Note 14) I - UART Transmit (CTS) Clear to Send, Active Low
71 UART_TX 2 O - UART Transmit
Note 14: These inputs are always enabled and must be driven or pulled to
a valid state to avoid leakage.
Note 15: See also pins 40, 42, 44, and 45 for additional GPIO ports.
Note 16: Embedded programming over the IPCS SPI bus is only avaliable
when RESETn is asserted.
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PIN FUNCTIONS
VSUPPLY: System and I/O Power Supply. Provides power
to the chip including the on-chip DC/DC converters. The
digital-interface I/O voltages are also set by this voltage.
Bypass with 2.2µF and 0.1µF to ensure the DC/DC convert-
ers operate properly.
VDDPA: PA-Converter Bypass Pin. A 0.47µF cap should be
connected from VDDPA to ground with as short a trace as
feasible. Do not connect anything else to this pin.
VDDA: Analog-Regulator Bypass Pin. A 0.1µF cap should
be connected from VDDA to ground with as short a trace
as feasible. Do not connect anything else to this pin.
VCORE: Core-Regulator Bypass Pin. A 56nF cap should be
connected from VCORE to ground with as short a trace as
feasible. Do not connect anything else to this pin.
VOSC: Oscillator-Regulator Bypass Pin. A 56nF cap should
be connected from VOSC to ground with as short a trace
as feasible. Do not connect anything else to this pin.
VPP: Maunufacturing Test port for internal regulator. Do
not connect anything to this pin.
VPRIME: Primary-Converter Bypass Pin. A 0.22µF cap
should be connected from VPRIME to ground with as short
a trace as feasible. Do not connect anything else to this pin.
VBGAP: Bandgap Reference Output. Used for testing and
calibration. Do not connect anything to this pin.
CAP_PA_1P, CAP_PA_1M through CAP_PA_4P, CAP_
PA_4M: Dedicated Power-Amplifier DC/DC Converter
Capacitor Pins. These pins are used when the radio is
transmitting to efficiently convert VSUPPLY to the proper
voltage for the power amplifier. A 56nF cap should be con-
nected between each P and M pair. Trace length should
be as short as feasible.
CAP_PRIME_1P, CAP_PRIME_1M through CAP_
PRIME_4P, CAP_PRIME_4M: Primary DC/DC Converter
Capacitor Pins. These pins are used when the device is
awake to efficiently convert VSUPPLY to the proper voltage
for the three on-chip low-dropout regulators. A 56nF cap
should be connected between each P and M pair. Trace
length should be as short as feasible.
RADIO_INHIBIT: RADIO_INHIBIT provides a mechanism
for an external device to temporarily disable radio opera-
tion. Failure to observe the timing requirements defined
in the Radio_Inhibit AC Characteristics table, may result
in unreliable network operation. In designs where the
RADIO_INHIBIT function is not needed the input must
either be tied, pulled or actively driven low to avoid excess
leakage.
LNA_ENABLE, RADIO_TX, RADIO_TXn: Control signals
generated by the autonomous MAC supporting the inte-
gration of an external LNA/PA. See the Eterna Extended
Range Reference Design for implementation details.
ANTENNA: Multiplexed Receiver Input and Transmitter
Output Pin. The impedance presented to the antenna
pin should be 50Ω, single-ended with respect to paddle
ground. To ensure regulatory compliance of the final
product please see the Eterna Integration Guide for filtering
requirements. The antenna pin should not have a DC path
to ground; AC blocking must be included if a DC-grounded
antenna is used.
AI_0, AI_1, AI_2, AI_3: Analog Inputs. These pins are
multiplexed to the analog input chain. The analog input
chain, as shown in Figure 12, is software-configurable
and includes a variable-gain amplifier, an offset-DAC for
adjusting input range, and a 10b ADC. Valid input range
is between 0 to 1.8V. Analog inputs can be sampled as
described in the On-Chip Software Development Kit (On-
Chip SDK).
Figure 12. Analog Input Chain
5800IPM F08
ANALOG INPUT
3-BIT
VGA
+
4-BIT DAC
10-BIT ADC
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PIN FUNCTIONS
OSC_32K_XOUT: Output Pin for the 32kHz Oscillator.
Connect to 32kHz quartz crystal. The OSC_32K_XOUT
and OSC_32K_XIN traces must be well-shielded from
other signals, both on the same PCB layer and lower PCB
layers, as shown in Figure 13.
OSC_20M_XIN: Input for the 20MHz Oscillator. Connect
only to a supported 20MHz quartz crystal. The OSC_20M_
XOUT and OSC_20M_XIN traces must be well-shielded
from other signals, both on the same PCB layer and lower
PCB layers, as shown in Figure 13.
RESETn: The asynchronous reset signal is internally pulled
up. Resetting Eterna will result in the ARM Cortex M3
rebooting and loss of network connectivity. Use of this
signal for resetting Eterna is not recommended except
during power-on and in-circuit programming.
TMS, TCK, TDI, TDO: JTAG Port Supporting Software
Debug and Boundary Scan. An IEEE Std 1149.1b-1994
compliant Boundary Scan Definition Language (BDSL) file
for the WR QFN72 package can be found here.
SLEEPn: The SLEEPn function is not currently supported
in software. The SLEEPn input must either be tied, pulled
or actively driven high to avoid excess leakage.
UART_RX, UART_RX_RTSn, UART_RX_CTSn, UART_TX,
UART_TX_RTSn, UART_TX_CTSn: The API UART interface
includes bi-directional wake up and flow control. Unused
input signals must be driven or pulled to their inactive state.
TIMEn: Strobing the TIMEn input is the most accurate
method to acquire the network time maintained by Eterna.
Eterna latches the network timestamp with sub-microsec-
ond resolution on the rising edge of the TIMEn signal and
produces a packet on the API serial port containing the
timing information.
UARTC0_RX, UARTC0_TX: The CLI UART provides a
mechanism for monitoring, configuration and control of
Eterna during operation. For a complete description of
the supported commands see the SmartMesh IP Mote
CLI Guide.
GPIO0, GPIO3 - GPIO6, GPIO9 - GPIO13, GPIO16,
GPIO20 - GPIO23, GPIO26: General purpose IO that can
be sampled or driven as described in the On-Chip Software
Development Kit (On-Chip SDK).
Figure 13. PCB Top Metal Layer Shielding of Crystal Signals
OSC_32K_XIN: Input for the 32kHz Oscillator. Con-
nect to 32kHz quartz crystal.The OSC_32K_XOUT and
OSC_32K_XIN traces must be well-shielded from other
signals, both on the same PCB layer and lower PCB layers,
as shown in Figure 13.
OSC_20M_XOUT: Output for the 20MHz Oscillator.
Connect only to a supported 20MHz quartz crystal. The
OSC_20M_XOUT and OSC_20M_XIN traces must be
well-shielded from other signals, as shown in Figure 13.
See the Eterna Integration Guide for supported crystals.
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PIN FUNCTIONS
FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,
IPCS_SSn: The In-circuit Programming Control System
(IPCS) bus enables in-circuit programming of Eterna’s flash
memory. IPCS_SCK is a clock and should be terminated
appropriately for the driving source to prevent overshoot
and ringing.
SPIM_CLK, SPIM_MISO, SPIM_MOSI, SPIM_SS_0n,
SPIM_SS_1n, SPIM_SS_4n: The SPI Master bus with
support for up to three SPI slave devices, via the On-Chip
Software Development Kit (On-Chip SDK) provides an in-
terface to SPI peripheral slave devices. The SPI interface
is syncrhonous to SPIM_CLK, which should be treated as
a clock singal and terminated appropriately .
1_WIRE: The 1-Wire master clock/data/power signal. See
the On-Chip Software Development Kit (On-Chip SDK) for
details on operating the 1-Wire Master controller.
SCL, SDA: The I2C bus SCL and SDA should be externally
pulled to VSUPPLY with a 10kΩ resistor. See the On-Chip
Software Development Kit (On-Chip SDK) for details on
operating the 1-Wire Master controller.
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OPERATION
The LTC5800 is the world’s most energy-efficient IEEE
802.15.4 compliant platform, enabling battery and en-
ergy harvested applications. With a powerful 32-bit ARM
Cortex™-M3, best-in-class radio, flash, RAM and purpose-
built peripherals, Eterna provides a flexible, scalable and
robust networking solution for applications demanding
minimal energy consumption and data reliability in even
the most challenging RF environments.
Shown in Figure 14, Eterna integrates purpose-built
peripherals that excel in both low operating-energy con-
sumption and the ability to rapidly and precisely cycle
between operating and low-power states. Items in the
gray shaded region labeled "Analog Core” correspond to
the analog/RF components.
POWER SUPPLY
Eterna is powered from a single pin, VSUPPLY, which
powers the I/O cells and is also used to generate internal
supplies. Eterna’s two on-chip DC/DC converters mini-
mize energy consumption while the device is awake. To
conserve power the DC/DC converters are disabled when
the device is in low-power state. Integrated power supply
conditioning, including the two integrated DC/DC convert-
ers and three integrated low-dropout regulators, provides
excellent rejection of supply noise. Eterna’s operating
supply voltage range is high enough to support direct
connection to lithium-thionyl chloride (Li-SOCl2) sources
and wide enough to support battery operation over a broad
temperature range.
Figure 14. Eterna Block Diagram
4-BIT
DAC
VGA
BPF PPF
AGC
LPF
ADC
DAC
PLL
RSSI
LNA
PA
20MHz
32kHz
32kHz, 20MHz
PTAT
5800IPM F10
BAT
LOAD
LIMITER
VOLTAGE REFERENCE
ANALOG COREDIGITAL CORE
CORE REGULATOR
CLOCK REGULATOR
ANALOG REGULATOR
PA
DC/DC
CONVERTER
PRIMARY
DC/DC
CONVERTER
RELAXATION
OSCILLATOR
PoR
TIMERS
SCHED
SRAM
72kB
FLASH
512kB
FLASH
CONTROLLER
AES
AUTO
MAC
802.15.4
MOD
802.15.4
FRAMING
DMA
IPCS
SPI
SLAVE
CLI
UART
(2 PIN)
API
UART
(6 PIN)
ADC
CTRL
802.15.4
DEMOD
PMU/
CLOCK
CONTROL
10-BIT
ADC
CODE
SYSTEM
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OPERATION
SUPPLY MONITORING AND RESET
Eterna integrates a Power-on reset (PoR) circuit. As the
RESETn input pin is nominally configured with an internal
pull-up resistor, no connection is required. For a graceful
shutdown, the software and the networking layers should
be cleanly halted via API commands prior to assertion of
the RESETn pin. See the SmartMesh IP Mote API Guide
for details on the disconnect and reset commands. Eterna
includes a soft brown-out monitor that fully protects the
flash from corruption in the event that power is removed
while writing to flash. Integrated flash supervisory func-
tionality, in conjunction with a fault tolerant file system,
yields a robust nonvolatile storage solution.
PRECISION TIMING
Eterna’s unique low power dedicated timing hardware and
timing algorithms provides a significant improvement over
competing 802.15.4 product offerings. This functionality
provides timing precision two to three orders of magnitude
better than any other low-power solution available at the
time of publication. Improved timing accuracy allows motes
to minimize the amount of radio listening time required
to ensure packet reception thereby lowering even further
the power consumed by SmartMesh networks. Eterna’s
patented timing hardware and timing algorithms provide
superior performance over rapid temperature changes,
further differentiating Eterna’s reliability when compared
with other wireless products. In addition, precise timing
enables networks to reduce spectral dead time, increasing
total network throughput.
APPLICATION TIME SYNCHRONIZATION
In addition to coordinating time slots across the network,
which is transparent to the user, Eterna’s timing manage-
ment is used to support two mechanisms to share network
time. Having an accurate, shared, network-wide time base
enables events to be accurately time stamped or tasks to
be performed in a synchronized fashion across a network.
Eterna will send a time packet through its serial interface
when one of the following occurs:
n Eterna receives an API request to read time
n The TIMEn signal is asserted
The use of TIMEn has the advantage of being more accu-
rate. The value of the timestamp is captured in hardware
relative to the rising edge of TIMEn. If an API request is
used, due to packet processing, the value of the timestamp
may be captured several milliseconds after receipt of the
packet. See the TIMEn AC Characteristics section for the
TIMEn function’s definition and specifications.
TIME REFERENCES
Eterna includes three clock sources: an internal relaxation
oscillator, a low power oscillator designed for a 32.768kHz
crystal, and the radio reference oscillator designed for a
20MHz crystal.
Relaxation Oscillator
The relaxation oscillator is the primary clock source for
Eterna, providing the clock for the CPU, memory subsys-
tems, and all peripherals. The internal relaxation oscillator
is dynamically calibrated to 7.3728MHz. The internal re-
laxation oscillator typically starts up in a few μs, providing
an expedient, low-energy method for duty cycling between
active and low power states. Quick start-up from the doze
state, defined in the State Diagram section, allows Eterna to
wake up and receive data over the UART and SPI interfaces
by simply detecting activity on the appropriate signals.
32.768kHz Crystal
Once Eterna is powered up and the 32.768kHz crystal
source has begun oscillating, the 32.768kHz crystal re-
mains operational while in the Active state, and is used as
the timing basis when in Doze state. See the State Diagram
section, for a description of Eterna’s operational states.
20MHz Crystal
The 20MHz crystal source provides a frequency reference
for the radio, and is automatically enabled and disabled by
Eterna as needed. Eterna requires specific characterized
20MHz crystal references. See the the Eterna Integration
Guide for a complete list of the currently supported 20MHz
crystals.
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OPERATION
RADIO
Eterna includes the lowest-power commercially available
2.4GHz IEEE 802.15.4e radio by a substantial margin.
(Please refer to the Radio Specifications section for
power consumption numbers.). Eterna’s integrated power
amplifier is calibrated and temperature-compensated to
consistently provide power at a limit suitable for worldwide
radio certifications. Additionally, Eterna uniquely includes
a hardware-based autonomous MAC that handles precise
sequencing of peripherals, including the transmitter, the
receiver, and advanced encryption standard (AES) pe-
ripherals. The hardware-based autonomous media access
controller (MAC) minimizes CPU activity, thereby further
decreasing power consumption.
UARTS
The principal network interface is through the application
programming interface (API) UART. A command-line
interface (CLI) is also provided for support of test and
debug functions. Both UARTs sense activity continuously,
consuming virtually no power until data is transferred and
automatically returning to their lowest power state after the
conclusion of a transfer. The definition for packet encoding
on the API UART interface can be found in the SmartMesh
IP Mote API Guide and the CLI command definitions can
be found in the SmartMesh IP Mote CLI Guide.
API UART Protocols
The API UART supports multiple modes with the goal of
supporting a wide range of companion multipoint control
units (MCUs) while reducing power consumption of the
system. As a general rule, higher serial data rates translate
into lower energy consumption for both endpoints. The API
UART receive protocol includes two additional signals in ad-
dition to UART_RX: UART_RX_RTSn and UART_RX_CTSn.
The transmit half of the API UART protocol includes two
additional signals in addition to UART_TX: UART_TX_RTSn
and UART_TX_CTSn. The two supported protocols are
referred to as UART Mode 2 and UART Mode 4. Mode
setting is controlled via the Fuse Table.
In the Figures accompanying the protocol descriptions,
signals driven by the companion processor are drawn
in black and signals driven by Eterna are drawn in blue.
UART Mode 2
UART Mode 2 provides the most energy-efficient method
for operating Eterna’s API UART. UART Mode 2 requires
the use of all six UART signals, but does not require
adherence to the minimum inter-packet delay as defined
in the UART AC Characteristics section. UART Mode 2
incorporates edge-sensitive flow control, at either 9600
or 115200 baud. Packets are HDLC encoded with one
stop bit and no parity bit. The flow control signals for
Eterna’s API receive path are shown in Figure 15. Trans-
fers are initiated by the companion processor asserting
UART_RX_RTSn. Eterna then responds by enabling the
UART and asserting UART_RX_CTSn. After detecting the
assertion of UART_RX_CTSn the companion processor
sends the entire packet. Following the transmission of
the final byte in the packet, the companion processor
negates UART_RX_RTSn and waits until the negation of
UART_RX_CTSn before asserting UART_RX_RTSn again.
The flow control signals for Eterna’s API transmit path are
shown in Figure 16. Transfers are initiated by Eterna assert-
ing UART_TX_RTSn. The companion processor responds
by asserting UART_TX_CTSn when ready to receive data.
After detecting the falling edge of UART_TX_CTSn Eterna
sends the entire packet. Following the transmission of the
final byte in the packet Eterna negates UART_TX_RTSn
and waits until the negation of UART_TX_CTSn before as-
serting UART_TX_RTSn again. The companion processor
may negate UART_TX_CTSn any time after the first byte
is transferred provided the time out from UART_TX_RTSn
to UART_TX_CTSn, tEND_TX_RTS to TX_CTS, is met.
5800IPM F11
UART_RX BYTE 0 BYTE 1
UART_RX_CTSn
UART_RX_RTSn
Figure 15. UART Mode 2 Receive Flow Control
Figure 16. UART Mode 2 Transmit Flow Control
5800IPM F12
UART_TX BYTE 0 BYTE 1
UART_TX_CTSn
UART_TX_RTSn
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OPERATION
UART Mode 4
UART Mode 4 incorporates level-sensitive flow control
on the TX channel and requires no flow control on the
RX channel, supporting both 9600 and 115200 baud.
The use of level-sensitive flow control signals enables
data rates above 9600 baud with the option of using a
reduced set of the flow control signals; however, Mode
4 has specific limitations. First, The use of the RX flow
control signals (UART_RX_RTSn and UART_RX_CTSn)
for Mode 4 are optional provided the use is limited to the
industrial temperature range (–40°C to 85°C); otherwise,
the flow control is mandatory. If RX flow control signals
are not used, UART_RX_RTSn should be tied to VSUPPLY
(inactive) and UART_RX_CTSn should be left unconnected.
Second, unless the companion processor is always ready
to receive a packet, the companion processor must negate
UART_TX_CTSn prior to the end of the current packet.
Failure to negate UART_TX_CTSn prior to the end of a
packet may result in back to back packets. Third, the
companion processor must wait at least tRX_INTERPACKET
between transmitting packets on UART_RX. See the
UART AC Characteristics section for complete timing
specifications. Packets are HDLC encoded with one stop
bit and no parity bit. The flow control signals for the TX
channel are shown in Figure 17. Transfers are initiated by
Eterna asserting UART_TX_RTSn. The UART_TX_CTSn
signal may be actively driven by the companion proces-
sor when ready to receive a packet or UART_TX_CTSn
may be tied low if the companion processor is always
ready to receive a packet. After detecting a logic ‘0’ on
UART_TX_CTSn Eterna sends the entire packet. Follow-
ing the transmission of the final byte in the packet Eterna
negates UART_TX_RTSn and waits for tTX_INTERPACKET,
defined in the UART AC Characteristics section, before
asserting UART_TX_RTSn again.
For details on the timing of the UART protocol, see the
UART AC Characteristics section.
CLI UART
The command line interface (CLI) UART port is a two
wire protocol (TX and RX) that operates at a fixed 9600
baud rate with one stop bit and no parity. The CLI UART
interface is intended to support command line instructions
and response activity.
AUTONOMOUS MAC
Eterna was designed as a system solution to provide a
reliable, ultralow power, and secure network. A reliable
network capable of dynamically optimizing operation
over changing environments requires solutions that are
far too complex to completely support through hardware
acceleration alone. As described in the Precision Timing
section, proper time management is essential for optimizing
a solution that is both low power and reliable. To address
these requirements Eterna includes the Autonomous MAC,
which incorporates a co-processor for controlling all of
the time-critical radio operations. The Autonomous MAC
provides two benefits: first, preventing variable software
latency from affecting network timing and second, greatly
reducing system power consumption by allowing the CPU
to remain inactive during the majority of the radio activity.
The Autonomous MAC, provides software-independent
timing control of the radio and radio-related functions,
resulting in superior reliability and exceptionally low power.
SECURITY
Network security is an often overlooked component of
a complete network solution. Proper implementation of
security protocols is significant in terms of both engineer-
ing effort and market value in an OEM product. Eterna
system solutions provide a FIPS-140 compliant encryp-
tion scheme that includes authentication and encryption
at the MAC and network layers with separate keys for
each mote. This not only yields end-to-end security, but
if a mote is somehow compromised, communication
from other motes is still secure. A mechanism for secure
key exchange allows keys to be kept fresh. To prevent
physical attacks, Eterna includes hardware support for
Figure 17. UART Mode 4 Transmit Flow Control
5800IPM F13
UART_TX BYTE 0 BYTE 1
UART_TX_CTSn
UART_TX_RTSn
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OPERATION
electronically locking devices, thereby preventing access
to Eterna’s flash and RAM memory and thus the keys and
code stored therein. This lock-out feature also provides
a means to securely unlock a device should support of a
product require access. For details see the Board Specific
Configuration Guide.
TEMPERATURE SENSOR
Eterna includes a calibrated temperature sensor on chip.
The temperature readings are available locally through
Eterna’s serial API, in addition to being available via the
network manager. The performance characteristics of the
temperature sensor can be found in the Typical Performance
Characteristics section.
RADIO INHIBIT
The RADIO_INHIBIT input enables an external control-
ler to temporarily disable the radio software drivers (for
example, to take a sensor reading that is susceptible to
radio interference). When RADIO_INHIBIT is asserted
the software radio drivers will disallow radio operations
including clear channel assessment, packet transmits,
or packet receipts. If the current timeslot is active when
RADIO_INHIBIT is asserted the radio will be diabled after
the present operation completes. For details on the timing
associated with RADIO_INHIBIT, see the Radio_Inhibit AC
Characteristics section.
FLASH PROGRAMMING
This product is provided without software programmed into
the device. OEMs will need to program software images
during development and manufacturing. Eterna’s software
images are loaded via the In-Circuit Programming Control
System (IPCS) SPI interface. Sequencing of RESETn and
FLASH_P_ENn, as described in the Flash SPI Slave AC
Characteristics section, places Eterna in a state emulating
a serial flash to support in-circuit programming. Hardware
and software for supporting development and production
programming of devices is described in the Eterna Serial
Programmer Guide. The serial protocol, SPI, and tim-
ing parameters are described in the Flash SPI Slave AC
Characteristics section.
FLASH DATA RETENTION
Eterna contains internal flash (non-volatile memory) to
store calibration results, unique ID, configuration set-
tings and software images. Flash retention is specified
over the operating temperature range. See the Electrical
Characteristics and Absolute Maximum Ratings sections.
Non destructive storage above the operating temperature
range of –55°C to 105°C is possible; although, this may
result in a degradation of retention characteristics.
The degradation in flash retention for temperatures >105°C
can be approximated by calculating the dimensionless
acceleration factor using the following equation.
AF =e
Ea
k
⎛
⎝
⎜⎞
⎠
⎟•1
T
USE+273 −1
TSTRESS+273
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎤
⎦
⎥
where:
AF = acceleration factor
Ea = activation energy = 0.6eV
k = 8.625 • 10–5eV/°K
TUSE = is the specified temperature retention in °C
TSTRESS = actual storage temperature in °C
Example: Calculate the effect on retention when storing
at a temperature of 125°C.
TSTRESS = 125°C
TUSE = 85°C
AF = 7.1
So the overall retention of the flash would be degraded
by a factor of 7.1, reducing data retention from 20 years
at 85°C to 2.8 years at 125°C.
STATE DIAGRAM
In order to provide capabilities and flexibility in addition
to ultra low power, Eterna operates in various states, as
shown in Figure 18. State transitions shown in red are
not recommended.
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OPERATION
Figure 18. Eterna State Diagram
SERIAL FLASH
EMULATION
LOAD FUSE
SETTINGS
RESETn LOW AND
FLASH_P_ENn HIGH
RESETn HIGH
AND
FLASH_P_ENn
HIGH
RESET
DEASSERT
RESETn
CPU AND
PERIPHERALS
INACTIVE
HW OR PMU EVENT
BOOT
START-UP
OPERATION INACTIVE
DOZE DEEP SLEEP
LOW POWER SLEEP
COMMAND
5800IPM F14
ASSERT RESETn
ASSERT RESETnASSERT RESETn
CPU
ACTIVE
CPU
INACTIVE
POWER-ON
RESET
RESETn LOW AND
FLASH_P_ENn LOW
SET RESETn HIGH AND
FLASH_P_ENn HIGH
FOR 125µs, THEN
SET RESETn LOW
VSUPPLY > PoR
ACTIVE
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OPERATION
Fuse Table
Eterna’s Fuse Table is a 2kB page in flash that contains
two data structures. One structure supports hardware
configuration immediately following power-on reset or
the assertion of RESETn. The second structure supports
configuration of software board support parameters.
Fuse Tables are generated via the Fuse Table application
described in the Board Specific Configuration Guide.
Hardware configuration of I/O immediately following power-
on reset provides a method to minimize leakage due to
floating nets prior to software configuration. I/O leakage
can contribute hundreds of microamperes of leakage
per input, potentially stressing current limited supplies.
Examples of software board support parameters include
setting of UART modes, clock sources and trim values.
Fuse Tables are loaded into flash using the same software
and in-circuit programmer used to load software images
as described in the Eterna Serial Programmer Guide.
Start-Up
Start-up occurs as a result of either crossing the power-on
reset threshold or asserting RESETn. After the comple-
tion of power-on reset or the falling edge of an internally
synchronized RESETn, Eterna loads its Fuse Table which,
as described in the previous section, includes configuring
I/O direction. In this state, Eterna checks the state of the
FLASH_P_ENn and RESETn pins and enters the serial
flash emulation mode if both signals are asserted. If the
FLASH_P_ENn pin is not asserted but RESETn is asserted,
Eterna automatically reduces its energy consumption to
a minimum until RESETn is released. Once RESETn is
de-asserted, Eterna goes through a boot sequence, and
then enters the active state.
Serial Flash Emulation
When both RESETn and FLASH_P_ENn are asserted,
Eterna disables normal operation and enters a mode to
emulate the operation of a serial flash. In this mode, its
flash can be programmed.
Operation
Once Eterna has completed start-up, Eterna transitions to
the operational group of states (active/CPU active, active/
CPU inactive, and doze). There, Eterna cycles between the
various states, automatically selecting the lowest pos-
sible power state while fulfilling the demands of network
operation.
Active State
In the active state, Eterna’s relaxation oscillator is running
and peripherals are enabled as needed. The ARM Cortex-
M3 cycles between CPU-active and CPU-inactive (referred
to in the ARM Cortex-M3 literature as sleep now mode).
Eterna’s extensive use of DMA and intelligent peripherals
that independently move Eterna between active state and
doze state minimizes the time the CPU is active, signifi-
cantly reducing Eterna’s energy consumption.
Doze State
The doze state consumes orders of magnitude less cur-
rent than the active state and is entered when all of the
peripherals and the CPU are inactive. In the doze state
Eterna’s full state is retained, timing is maintained, and
Eterna is configured to detect, wake, and rapidly respond
to activity on I/Os (such as UART signals and the TIMEn
pin). In the doze state the 32.768kHz oscillator and as-
sociated timers are active.
SPI MASTER
The Eterna SPI master controller supports all configura-
tions of clock polarity and phase, with a setable shift
clock frequencies of 460.8kHz, 921.6kHz, 1.8432MHz, or
3.6864MHz. In addition the SPI master controller can be
configured to repetatively issue commands and capture
the corresponding output, enabling repetative sampling
of signals from a SPI ADC or SPI sensor based upon a
clock reference of better than ±50ppm. For implementa-
tion details refer to the On-Chip Software Development
Kit (On-Chip SDK).
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OPERATION
I2C MASTER
The I2C Master enables control of I2C slave devices,
including support for clock stretching slaves. I2C Multi-
master and bus arbitration protocols are not supported.
For implementation details refer to the On-Chip Software
Development Kit (On-Chip SDK).
1-WIRE MASTER
The Eterna 1-Wire Master controller supports the reset,
pressense detect, read and write 1-Wire protocol opera-
tions, incorporating an active pull-up. The active pull-up
becomes active when the passive pull-up raises the volt-
age on the 1_WIRE pin nominally above 1.4V, driving the
1_WIRE signal as specified in Digital I/O Characteristics.
For implementation details refer to the On-Chip Software
Development Kit (On-Chip SDK).
APPLICATIONS INFORMATION
MODES OF OPERATION
The SmartMesh IP Mote software can be operated in three
distinct modes, namely, namely Slave, Master, and On-
Chip SDK. Mode selection should be considered during
the architecture/design phase of the development process.
Slave Mode
In Slave mode, the Eterna is connected to an external
microprocessor through the API UART and is solely used
as a networking device. None of the built in I/Os are ac-
cessible in this mode. Refer to the SmartMesh IP User's
Guide for more detailed information.
Master Mode
In Master mode, no external uProcessor is required and a
limited set of functionality is made available with no pro-
gramming required on the device. The following features
are available
n On-Chip Temperature Sensor
n 4 Analog Inputs
n 4 Digital Inputs
n 3 Digital Outputs
Refer to the SmartMesh IP User's Guide for more detailed
information.
On-Chip SDK (OCSDK)
The SmartMesh IP On-Chip Software Development Kit (On-
Chip SDK) enables development of C-code applications for
execution on the LTC5800-IPM, running Micrium’s µCOS-II
real-time operating system. With the On-Chip SDK, users
may quickly and easily develop application code without
the need for an external microprocessor.
Applications written within the On-Chip SDK may send
and receive wireless messages through the mesh network;
process data, such as statistical analysis; execute local
decision-making and control; and manage the following
peripherals:
n General Purpose Input-Output (GPIO) pins
n Analog-to-Digital Converter (ADC)
n Universal Asynchronous Receiver/Transmitter
(UART)
n Serial Peripheral Interface (SPI) Master
n Inter-Integrated Circuit (I2C) Master
n 1-Wire Master
Network connectivity and quality of service is handled by
the SmartMesh IP protocol stack. The SmartMesh IP stack
comes as a pre-compiled library and delivers >99.999%
data reliability while providing ultra low power operation.
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APPLICATIONS INFORMATION
REGULATORY AND STANDARDS COMPLIANCE
Radio Certification
Eterna is suitable for systems targeting compliance with
worldwide radio frequency regulations: ETSI EN 300 328
and EN 300 440 class 2 (Europe), FCC CFR47 Part 15
(US), and ARIB STD-T66 (Japan). Application Program-
ming Interfaces (APIs) supporting regulatory testing are
provided on both the API and CLI UART interfaces. The
Eterna Certification User Guide provides:
n Reference information required for certification
n Test plans for common regulatory test cases
n Example CLI API calls
n Sample manual language and example label
Compliance to Restriction of Hazardous Substances
(RoHS)
Restriction of Hazardous Substances (RoHS) is a directive
that places maximum concentration limits on the use of
cadmium (Cd), lead (Pb), hexavalent chromium (Cr+6),
mercury (Hg), Polybrominated Biphenyl (PBB), and Poly-
brominated Diphenyl Ethers (PBDE). Linear Technology is
committed to meeting the requirements of the European
Community directive 2002/95/EC.
This product has been specifically designed to utilize
RoHS-compliant materials and to eliminate or reduce the
use of restricted materials to comply with 2002/95/EC.
The RoHS-compliant design features include:
n RoHS-compliant solder for solder joints
n RoHS-compliant base metal alloys
n RoHS-compliant precious metal plating
n RoHS-compliant cable assemblies and connector
choices
n Lead-free QFN package
n Halogen-free mold compound
n RoHS-compliant and 245°C re-flow compatible
Note: Customers may elect to use certain types of lead-
free solder alloys in accordance with the European Com-
munity directive 2002/95/EC. Depending on the type of
solder paste chosen, a corresponding process change to
optimize reflow temperatures may be required.
SOLDERING INFORMATION
Eterna is suitable for both eutectic PbSn and RoHS-6 reflow.
The maximum reflow soldering temperature is 260°C. A
more detailed description of layout recommendations, as-
sembly procedures and design considerations is included
in the Eterna Integration Guide.
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RELATED DOCUMENTATION
TITLE LOCATION DESCRIPTION
SmartMesh IP User’s Guide http://www.linear.com/docs/41880 User’s guide for Smartmesh IP networks, managers and motes.
SmartMesh IP Mote API Guide http://www.linear.com/docs/41886 Definitions of the applications interface commands available over
the API UART
SmartMesh IP Mote CLI Guide http://www.linear.com/docs/41885 Definitions of the command line interface commands available
over the CLI UART
Eterna Integration Guide http://www.linear.com/docs/41874 Recommended practices for designing with the LTC5800-IPM
Eterna Serial Programmer Guide http://www.linear.com/docs/41876 User’s guide for the Eterna Serial programmer used for in circuit
programming of the LTC5800-IPM
Board Specific Configuration Guide http://www.linear.com/docs/41875 User’s guide for the Eterna Board Specific Configuration
application, used to configure the board specific parameters
Eterna Certification User Guide http://www.linear.com/docs/42918 The essential documentation necessary to complete radio
certifications, including examples for common test cases
SmartMesh IP Tools Guide http://www.linear.com/docs/42453 The user’s guide for all IP related tools, and specifically the
definition for the On-chip Application Protocol (OAP)
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PACKAGE DESCRIPTION
WR Package
72-Lead QFN (10mm × 10mm)
(Reference LTC DWG # 05-08-1930 Rev A)
0.15 C
SEATING PLANE
0.10 C
0.10 C
0.15 C
9.75
BSC
9.75 BSC
10.00
BSC
B
B
10.00 BSC
0.5 ±0.1
7255
36 19
54
37 18
1
C
DETAIL A
PIN 1
R0.300
TYP
6.00 ±0.15
6.00 ±0.15
DETAIL B
0.50 BSC
0.65 REF
0°–14° (×4)
DETAIL A
0.02
MAX
1.0mm
0.20
REF
0.50
0.60
MAX
0.25 ±0.05
b
BAC0.10 M
DETAIL B
WR72 0213 REV A
C0.0.5 M
0.60 MAX
WR Package
72-Lead QFN (10mm × 10mm)
(Reference LTC DWG # 05-08-1930 Rev A)
8.50 REF
(4 SIDES)
0.50 BSC
6.00 ±0.15
6.00 ±0.15 8.90 ±0.05
10.50 ±0.05
0.25 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220
2. DIMENSION “b” APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN
0.15mm AND 0.30mm FROM THE TERMINAL TIP. IF THE TERMINAL HAS OPTIONAL
RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION B SHOULD NOT BE
MEASURED IN THAT RADIUS AREA
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. DRAWING NOT TO SCALE
0.8 ±0.05
LTCXXXXXX
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
Please refer to http://www.linear.com/product/LTC5800-IPM#packaging for the most recent package drawings.
LTC5800-IPM
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For more information www.linear.com/LTC5800-IPM
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/15 Added H-Grade Ordering Information and Product Specifications
Added SPI Master AC Characteristics
Added I2C Master AC Characteristics
Added 1-Wire Master section
Added Overviews of On-Chip SDK Operation, SPI Master, I2C Master and 1-Wire Master Ports
4, 5, 29
12
13
14
32-33
LTC5800-IPM
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LINEAR TECHNOLOGY CORPORATION 2013
LT 1215 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC5800-IPM
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC5800-IPRA IP Wireless Mesh 32 Mote Manager Manages Networks of Up to 32 SmartMesh IP Nodes.
LTC5800-IPRB IP Wireless Mesh 100 Mote Manager Manages Networks of Up to 100 SmartMesh IP Nodes.
LT P 5901-IPMA IP Wireless Mesh Mote PCB Module with Chip
Antenna
Includes Modular Radio Certification in the United States, Canada, Europe, Japan,
South Korea, Taiwan, India, Australia and New Zealand
LT P 5902-IPMA IP Wireless Mesh Mote PCB Module with MMCX
Antenna Connector
Includes Modular Radio Certification in the United States, Canada, Europe, Japan,
South Korea, Taiwan, India, Australia and New Zealand
LT6654 Precision High Output Drive Low Noise Reference 1.6ppm Peak-to-Peak Noise (0.1Hz to 10Hz), Sink/Source ±10mA, 5ppm/°C Max Drift
LTC2379-18 18-Bit,1.6Msps/1Msps/500ksps/250ksps Serial,
Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC
LTC3388-1/
LTC3388-3
20V High Efficiency Nanopower Step-Down
Regulator
860nA IQ in Sleep, 2.7V to 20V Input, VOUT = 1.2V to 5.0V, Enable and Standby Pins
LTC3588-1 Piezoelectric Energy Generator with Integrated
High Efficiency Buck Converter
VIN = 2.7V to 20V, VOUT(MIN) = Fixed to 1.8V/2.5V/3.3V/3.6V, IQ = 0.95μA, 3mm ×
3mm DFN-10 and MSOP-10E Packages
LTC3108-1 Ultralow Voltage Step-Up Converter and Power
Manager
VIN = 0.02V to 1V, VOUT = 2.5V/3V/3.7V/4.5V Fixed, IQ = 6μA, 3mm × 4mm DFN-12
and SSOP-16 Packages
LTC3459 Micropower Synchronous Boost Converter VIN = 1.5V to 5.5V, VOUT(MAX) = 10V, IQ = 10μA, 2mm × 2mm DFN, 2mm × 3mm DFN
or SOT-23 Package
Mesh Network Thermistor
5800IPM TA02
TADIRAN TL-5903
Li-SOCI2
LTC5800-IPM
3.3nH
100pF
ANTENNA VSUPPLY
IPCS_MISO
AI_0
AI_1
VDDA
CAP_PA_1P
CAP_PA_1M
CAP_PA_2P
CAP_PA_2M
CAP_PA_3P
CAP_PA_3M
CAP_PA_4P
CAP_PA_4M
1pF
56nF
56nF
56nF
56nF
0.47µF
1pF
2.2µH
2.2µF
0.1µF
CAP_PRIME_1P
CAP_PRIME_1M
CAP_PRIME_2P
CAP_PRIME_2M
CAP_PRIME_3P
CAP_PRIME_3M
CAP_PRIME_4P
CAP_PRIME_4M
56nF
56nF
56nF
56nF
0.22µF
0.1µF
VCORE
20MHz
32.768kHz
RT = 5k • AI_0 / (2 • AI_1 – AI_0)
T(°C) = 1 / {A + B [Ln(RT)] + C[Ln(RT)]3} – 273.15
A = 1.032 • 10–3
B = 2.387 • 10–4
C = 1.580 • 10–7
56nF
VOSC
56nF
GND
OSC_20M_XOUT
OSC_20M_XIN
OSC_32K_XOUT
OSC_32K_XIN
LT6654
5k
0.1%
10k, 0.2C
OMEGA 44006
VIN VOUT
GND2 GND1
0.1µF
1000pF
5k
0.1%
5k
0.1%
1000pF
VDDPA
VPRIME
