A product Line of Diodes Incorporated PI3HDX1204E HDMI 2.0 6Gbps Linear Redriver Level Shifter Near to the Sink/DFE-side application Description Applications PI3HDX1204E is the HDMI 2.0 Linear Redriver with the Level Shifter, supporting the minimum additive jitters. The linear Redriver provides the easiness of handling the signal integrity issues known in the component placement and the setting parameters of Equalization and Flat Gain compensation between Source-side and Sink-side link system. IITVs and Monitors near to the Sink-side Devices Receiver SOC D0 D1 D2 CLK The advantage of Linear Redriver does not block the original source differential signals to maximize the Sink-side Receiver Digital Feedback Equalization (DFE) Feedback circuits to improve the high-speed linked signal quality. The output swing range can set by Swing control for the power saving. D0 D1 D2 CLK PI3HDX1204E Linear Redriver RX CTLE + DFE Equalization I2C EQ/FG/SW Control DDC SCL/SDA Monitor The optimization of the signal quality over a variety of physical mediums by reducing Inter-symbol Interference (ISI) jitters can be done by the pin-strapping or I2C programming. HDMI Cable In EEPROM mode, the Equalization, Voltage Swing and Gain controls can be automatically loaded during the system power-up to eliminate the need of external microprocessor or software driver. Transmier CHIPSET AC-coupled DP Mainlink DP++ Tx Features DP++ Level Shier PI3HDX1204Bx PI3HDX6211x Liming Redriver LevelShier D0 D1 D2 CLK DDC SCL/SDA Notebook IIHDMI 2.0 Compliant TMDS Linear Redriver with 2x Improved Jitter Performance than conventional technology Figure 1. Monitor for sink-side with Rx DFE receiver IIDP++ Level Shifting for HDMI output IILinear Redriver increases TMDS Link Margin supporting Sink-side DFE (Decision Feedback Equalizers) receiver Ordering Information IIEvery Channel's Equalizations, Swings and Gains are programmable Independently Ordering Number IISupport Pin- strap and I2C Programming IIFlexible 4-bit I2C address selectable (42-pin, ZH package) IIPower supply: 3.3V IIPackage (Pb-Free & Green): Package Code Eco Plan PI3HDX1204E ZLEX ZL Pb-free & Green, 32-pin TQFN PI3HDX1204E ZHEX ZH Pb-free & Green, 42pin TQFN -- 32-pin TQFN (3x6mm) -- 42-pin TQFN (3.5x9mm) PI3DPX1204E Document number: DS40009 Rev 1-2 1 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 2. General Information 2.1 Revision History Revision Description March 2016 Pin-out (p8): FGx(x=0,1) Pin name typo fixed. April 2016 Electrical(p17): tSK_INTRA_OUT changed 5 typ, 10 max ps May 2016 Application(p30): More informative system EE contents added. DDC source-side pull-up changed to 10 kOhm from 2 kOhm June 2016 Mechanical (p39): EPAD outline changed Oct 2016 Diodes Disclaimer added Aug 2017 Clarified Output Swing range control in functional description. PI3HDX1204B1 limiting and PI3HDX1204E linear pin-out comparison added in generic information session Dec 2017 Updated package mechanical drawing with latest (p46). 2.2 PI3HDX1204D to PI3HDX1204E PDN Notice PI3HDX1204E is a production part number of PI3HDX1204D. The detail comparison is summarized below. PI3HDX1204E Changes 32-pin TQFN package added Pin-out No change PI3HDX1204D Function control No change Application Note PI3HDX1204D application note and schematics are applicable to the PI3HDX1204E. EOL (End of Life). PI3HDX1204D was engineering version of PI3HDX1204E 2.3 Similar Products Comparison PI3HDX1204B1 PI3HDX1204E Redriver Type Limiting type Linear type EQ at 6Gbps 22 dB 10 dB Output TMDS peak-topeak Swing Output Swing Amplitude / Pre-Emphasis control. Blocking type Follow Source Swing Amplitude. Non-blocking type. DDC Switch/Buffer No No HDMI1.4/2.0 Type ID No No Ioff Protection External Power Switch External Power Switch Data Rate (Gbps) 6 Gbps 6 Gbps Application Near to Source-side device Near to Sink-side device Availability Production Production PI3DPX1204E Document number: DS40009 Rev 1-2 2 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E SW1 SW0 DE1 DE0 VCC A0RX+ 1 2 3 4 A0RX- 5 6 7 GND A1RX+ A1RXVCC A2RX+ A2RXGND A3RX+ A3RXVCC DNC DNC A1 A4 Connection Description BST1 EQ1/AD1 BST0 EQ0/AD0 BST3 EQ3/AD3 BST2 EQ2/AD2 PI3HDX1204B1 / PI3HDX1204E Pin out Co-layout Comparison 42 41 40 39 38 37 36 35 FG1/I2C_RESET# PS1 FG0 PS0 VCC A0TX+ 34 A0TXVCC A1TX+ A1TXVCC A2TX+ 8 9 10 33 32 31 30 29 11 12 13 14 15 28 A2TX- 27 26 25 24 VCC 16 17 23 22 VOD1 A0 Pin 16,17,23: Do not connect in PI3HDX1204E Pin 1,2,20,21,22,37,38,39,40,41,42: Pull-up and Pulldown pin mode control pins A3TX+ A3TXVCC DNC I2C_DONE PI3HDX1204B1 PI3HDX1204E PI3DPX1204E Document number: DS40009 Rev 1-2 PRSNT# PEN ENI2C PIN_MODE SDA SCL 18 19 20 21 3 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 2.4 Related Products Part Numbers Products Description Retimers / Jitter Cleaner PI3HDX2711B HDMI 2.0 and DP++ Retimer (Jitter Cleaner) PI3HDX711B HDMI 1.4 and DP++ ReTimer (Jitter Cleaner) Redrivers PI3DPX1203B DisplayPort 1.4 Redriver for Source/Sink/Cable Application, Linear-type PI3HDX1204B1 HDMI 2.0 Redriver (DP++ Level Shifter), High EQ, place near to the source-side, Limiting type PI3HDX1204E HDMI 2.0 Linear Redriver (DP++ Level Shifter) , Link transparent, place near to the sink-side PI3DPX1207B DisplayPort 1.4 Alt Type-C Redriver, 8.1 Gbps and USB3.1 10 Gbps, Link Transparent PI3DPX1202A Low Power DisplayPort 1.2 Redriver with built-in AUX Listener, Limiting-type PI3HDX511F High EQ HDMI 1.4b Redriver and DP++ Level Shifter for Sink/Source Application, Limiting-type Active Switches & Splitters PI3DPX1205A DisplayPort 1.4 Alt Type-C Mux Redriver, 8.1 Gbps and USB3.1 10 Gbps, Link Transparent PI3HDX231 HDMI 2.0 3:1 ports Mux Redriver, Linear-type PI3HDX414 HDMI 1.4b 1:4 Demux Redriver & Splitter for 3.4 Gbps Application, Limiting-type PI3HDX412BD HDMI 1.4b 1:2 Demux Redriver & Splitter for 3.4 Gbps Application, Limiting-type PI3HDX621 HDMI 1.4 Redriver 2:1 Active Switch with built-in ARC and Fast Switching support, Limiting-type PI3DPX1204E Document number: DS40009 Rev 1-2 4 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Contents 1. Product Brief..................................................................................................................................................................... 1 2. General Information ...................................................................................................................................................... 2 2.1 2.2 2.3 2.4 Revision History................................................................................................................................................................ 2 PI3HDX1204D to PI3HDX1204E PDN Notice................................................................................................................ 2 Similar Products Comparison .......................................................................................................................................... 2 Related Products............................................................................................................................................................... 4 3. Pin Configuration............................................................................................................................................................ 6 3.1 Package Pin-out................................................................................................................................................................. 6 3.2 Pin Description................................................................................................................................................................. 7 4. Functional......................................................................................................................................................................... 11 4.1 Functional Block............................................................................................................................................................. 11 4.2 Function Description...................................................................................................................................................... 12 5. I2C Programming.......................................................................................................................................................... 16 5.1 Programming registers.................................................................................................................................................... 16 5.2 I2C operation.................................................................................................................................................................. 18 6. Electrical Specification................................................................................................................................................. 20 6.1 6.2 6.3 6.4 Absolute Maximum ratings............................................................................................................................................. 20 Recommended operating conditions.............................................................................................................................. 20 Electrical characteristics ................................................................................................................................................. 20 I2C Interface Bus............................................................................................................................................................. 25 7.1 7.2 7.3 7.4 7.5 7.6 DC/AC-coupled Application........................................................................................................................................... 27 Sink-side Redriver Application....................................................................................................................................... 28 Channels/Polarity Swap.................................................................................................................................................. 28 Output Eye Diagram....................................................................................................................................................... 29 Layout Guidelines........................................................................................................................................................... 33 HDMI 2.0 Compliance Test............................................................................................................................................ 39 7. Applications..................................................................................................................................................................... 27 8. Mechanical/Packaging................................................................................................................................................. 42 8.1 Mechanical Outline......................................................................................................................................................... 42 8.2 Part Marking Information............................................................................................................................................... 45 8.3 Tape & Reel Materials and Design.................................................................................................................................. 46 9. Important Notice........................................................................................................................................................... 49 PI3DPX1204E Document number: DS40009 Rev 1-2 5 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 3. Pin Configuration 8 VDD 24 23 22 21 TQFN ZL32 3x6mm 9 10 20 19 18 11 17 12 13 14 15 16 A0TXVDD A1TX+ A1TXVDD A2TX+ A2TXVDD A3TX+ A3TX- A0RX- 5 6 7 GND A1RX+ A1RXVDD A2RX+ 8 9 10 A2RXGND A3RX+ A3RXVDD 11 12 13 14 15 DNC DNC 16 17 EQ1/AD1 EQ0/AD0 FG1/I2C_RESET# FG0 EQ1 25 SDA SCL A3RX+ A3RX- 26 1 2 3 4 42 41 40 39 TQFN ZH42 3.5x9mm 38 37 36 35 FG1/I2C_RESET# FG0 34 A0TXVDD A1TX+ A1TXGND A2TX+ 33 32 31 30 29 28 27 26 25 24 23 22 VDD A0TX+ A2TXVDD A3TX+ A3TXVDD DNC I2C_DONE 18 19 20 21 PRSNT# ENI2C A2RX- 27 A0TX+ SW1 SW0 VDD A0RX+ SDA SCL A2RX+ 5 6 7 32 31 30 29 28 I2C_DONE A0RXVDD A1RX+ A1RXVDD 1 2 3 4 PRSNT# ENI2C A0RX+ EQ2 EQ3 SW[1:0] = 11 (tied high internally) EQ3/AD3 EQ2/AD2 3.1 Package Pin-out Figure 3-1 32/42-pin package pin-out Note: In TMDS Data and Clock Differential Pairs of Input and Output, the polarity (+/- or P/N) of each pairs and high-speed data channels A[3:0] can use interchangeably. Output pins of polarity and data channel will always follow the input polarity and data channel assignment changes. PI3DPX1204E Document number: DS40009 Rev 1-2 6 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 3.2 Pin Description 3.2.1 32-pin package Pin # Pin Name Type Description 1 2 A0RX+ A0RX- I TMDS differential positive/negative input for Channel A0, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 27 26 A0TX+, A0TX- O TMDS differential positive/negative outputs for Channel A0, with internal 50 Pull-Up and ~2k Pull-Up otherwise. 4 5 A1RX+, A1RX- I TMDS differential positive/negative inputs for Channel A1, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 24 23 A1TX+, A1TX- O TMDS differential positive/negative outputs for Channel A1, with internal 50 Pull-Up and ~2k Pull-Up otherwise. 7 8 A2RX+, A2RX- I TMDS differential positive/negative inputs for Channel A2, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 21 20 A2TX+, A2TX- O TMDS differential positive/negative outputs for Channel A2, with internal 50 Pull-Up and ~2k Pull-Up otherwise. 10 11 A3RX+, A3RX- I TMDS differential positive/negative inputs for Channel A3, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 18 17 A3TX+, A3TX- O TMDS differential positive/negative outputs for Channel A3, with internal 50 Pull-Up and ~2k Pull-Up otherwise. SDA I/O I2C Serial Data line I/O I2C Serial Clock line In Master mode (ENI2C pin floating), SCL is an output. Otherwise it is an input as a slave mode. Data Signals Control Signals 12 13 SCL Cable Present Detect input. This pin has internal 100K pull-up. 14 PRSNT# I The pin is active when both PIN mode ( ENI2C = LOW) and I2C mode ( ENI2C = HIGH). When High, a cable is not present, and the device is put in lower power mode. When Low, the device is enabled and in normal operation. 15 ENI2C I I2C Enable pin. When LOW, each channel is programmed by the external pin voltage. When HIGH, each channel is programmed by the data stored in the I2C bus. When floating, master mode (Read External EEPROM) EQ[3:1] I EQ Control pin. Inputs with internal 100k pull-up. This pins set the amount of Equalizer Boost in all channels when ENI2C is low. AD[3:1] I Address bits control pins for I2C programming with internal 100k pullup. 32,31,30 PI3DPX1204E Document number: DS40009 Rev 1-2 7 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Pin # Pin Name Type Description 29 FG1/I2C_RESET# I Shared pin for Gain Control bit-1 and I2C Reset pin. Inputs with internal 100k pull up resistor. (1) Sets the output flat gain level bit-1 on all channels when ENI2C is Low. (2) I2C Reset pin. Active Low to reset the registers to default state. 28 FG0 I Flat Gain control bit-0 pin. Inputs with internal 100k pull up resistor. Sets the output flat gain level on all channels when ENI2C is low. I2C_DONE O I2C Done pin. Valid register load status output for using the daisy chain I2C master. Low = External EEPROM load failed High = External EEPROM load passed 3,6,9,19,22,25 VDD PWR 3.3V Power supply pins Center Pad GND GND Exposed Ground pad. 16 Power Pins PI3DPX1204E Document number: DS40009 Rev 1-2 8 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 3.2.2 42-pin package Pin # Pin Name Type Description 4 5 A0RX+ A0RX- I TMDS differential positive/negative input for Channel A0, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 35 34 A0TX+, A0TX- O TMDS differential positive/negative outputs for Channel A0, with internal 50 Pull-Up and ~2k Pull-Up otherwise. 7 8 A1RX+, A1RX- I TMDS differential positive/negative inputs for Channel A1, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 32 31 A1TX+, A1TX- O TMDS differential positive/negative outputs for Channel A1, with internal 50 Pull-Up and ~2k Pull-Up otherwise. 10 11 A2RX+, A2RX- I TMDS differential positive/negative inputs for Channel A2, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 29 28 A2TX+, A2TX- O TMDS differential positive/negative outputs for Channel A2, with internal 50 Pull-Up and ~2k Pull-Up otherwise. 13 14 A3RX+, A3RX- I TMDS differential positive/negative inputs for Channel A3, with internal 50 Pull-Up and ~200k Pull-Up otherwise. 26 25 A3TX+, A3TX- O TMDS differential positive/negative outputs for Channel A3, with internal 50 Pull-Up and ~2k Pull-Up otherwise. Data Signals Control Signals 16,17,23 DNC Do Not Connect 19 SCL I/O I2C Serial Clock line In Master mode (ENI2C pin floating), SCL is an output. Otherwise it is an input as a slave mode. 18 SDA I/O I2C Serial Data line Cable Present Detect input. 20 PRSNT# I This pin has internal 100K pull-up. The pin is active when both PIN mode ( ENI2C = LOW) and I2C mode ( ENI2C = HIGH). When High, a cable is not present, and the device is put in lower power mode. When Low, the device is enabled and in normal operation. 21 PI3DPX1204E Document number: DS40009 Rev 1-2 ENI2C I I2C Enable pin. When LOW, each channel is programmed by the external pin voltage. When HIGH, each channel is programmed by the data stored in the I2C bus. When floating, master mode (Read External EEPROM) 9 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Pin # Pin Name Type Description EQ[3:0] I EQ Control pin. Inputs with internal 100k pull-up. This pins set the amount of Equalizer Boost in all channel when ENI2C is LOW. AD[3:0] I I2C address bits control pins for programming with internal 100k pullup. SW[1:0] I Output Swing control pins. Inputs with internal 100k pull-up. This pin sets the output Voltage Level in all channel when ENI2C is LOW. I Gain Control pin bit 0 Inputs with internal 100k pull up resistor. Sets the output flat gain level on all channels when ENI2C is low. 39,40,41,42 1,2 37 FG0 38 FG1/I2C_RESET# I Shared pin for Flat Gain control bit-1 or I2C Reset pin. Inputs with internal 100k pull up resistor. (1) Sets the output flat gain level bit-1 on all channels when ENI2C is Low. (2) I2C Reset pin. Active Low to reset the registers to default state. 22 I2C_DONE O I2C Done pin. Valid register load status output, use for daisy chain master Low = External EEPROM load failed High = External EEPROM load passed 3, 9, 15, 24, 27, 33, 36 VDD PWR 3.3V Power Supply pins 6, 12, 30, Center Pad GND GND Exposed Ground pad. Power Pins PI3DPX1204E Document number: DS40009 Rev 1-2 10 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 4. Functional 4.1 Functional Block VDD VDD 50 or 200K AxRX+ Input Buffer EQ[3:0] or AD[3:0] Linear Amplifier Rx AxRX- 50 or 2K Equalization Control 4-bits AxTX+ Buffer Tx Output Driver Flat Gain 2-bits Voltage Swing 2-bits Control Logic/Configuration Registers SDA/SCL ENI2C I2C_DONE AxTX- SW[1:0] FG[1:0] I2C Slave/ Master PRSNT# I2C_RESET# Figure 4-1 Functional Block Diagram PI3DPX1204E Document number: DS40009 Rev 1-2 11 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 4.2 Function Description 4.2.1 Power-Down/Enable When PRSNT# is set to "1", device enter to the power-down mode. When Input 200k and Output High Impedance (HIZ) termination resisters set, each individual channels Ax(x=0,1,2,3) can program the I2C register. 4.2.2 Input Equalization Setting The EQx(x=0,1,2,3) pins are the pin-strap option for each Ax(x=0,1,2,3) channels. It can also be programmable by the I2C mode. Table 4-1. Equalization Setting for 42-pin EQ3 EQ2 EQ1 EQ0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 PI3DPX1204E Document number: DS40009 Rev 1-2 6Gbps Input(dB) 3.6 4.0 4.4 4.7 5.1 5.5 5.9 6.2 6.6 6.9 7.3 7.6 8.0 8.2 8.6 8.9 12 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Table 4-2. Equalization Setting for 32-pin EQ3 EQ2 EQ1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 6 Gbps Input EQ(dB) 4.0 4.7 5.5 6.2 6.9 7.6 8.2 8.9 Notes (1) EQ0 pin always tied to "1" internally in 32-pin package. 4.2.3 Output -1 dB Compression Swing setting SWx(x=0,1) affects the linearity of the output when input amplitude changes. Table 4-3. SW[1:0] Output Swing Setting SW1 SW0 Voltage Swing mVpp @100MHz Voltage Swing mVpp @ 6Gbps Notes 0 0 920 1100 0 1 1040 1200 1 0 1280 1300 1 Note 1 1370 1400 Default Setting. Internally 100k pull-up. (1) SW[1:0]=11 setting support by I2C programming in 32-pin package 4.2.4 Flat Gain Setting FGx(x=0,1) two pins are the selection 2 bits for the DC Flat Gain value. Table 4-4. Flat Gain FG[1:0] Control FG1 FG0 Gain (dB) 0 0 -3.5 dB 0 1 -1.5 dB 1 0 +0.5 dB 1 1 +2.5 dB PI3DPX1204E Document number: DS40009 Rev 1-2 13 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Input/Output Differential Voltage Swing (-1dB Compression) at 4.05GHz, 3.3V, EQ=3dB and FG = 0dB Output Differential Signal (Vpp) Swing Range Input Differential Signal (Vpp) Figure 4-2 Example of Output voltage swing with different SW setting 300mA 250 FG=-3.5 FG=-2.5 FG=0.5 FG=2.5 200 700 800 900 1000mV Figure 4-3 Power dissipation mA vs. SW[1:0] setting PI3DPX1204E Document number: DS40009 Rev 1-2 14 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Gain (dB) Gain (dB) RX1P Output (V) FG Setting TX1P SW range RX1N TX1N EQ Setting f(GHz) Control Input Equalization control f(GHz) Flat Gain control Input (V) Output Swing range contol Figure 4-4 Illustration of EQ, Gain and Swing setting PI3DPX1204E Document number: DS40009 Rev 1-2 15 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 5. I2C Programming 5.1 Programming registers 5.1.1 I2C address A6 A5 A4 A3 A2 A1 A0 R/W 1 1 1 AD3 AD2 AD1 AD0(1) 1=R, 0=W Note: (1) Address A0 is always "1" tied high for 32-pin package. 5.1.2 Configuration Registers BYTE 0 Bit Type 7:0 R Power up condition Description Control affected Comment Control affected Comment Control affected Comment Reserved BYTE 1 Bit Type 7:0 R Power up condition Description Reserved BYTE 2 Bit Type Power up condition 7 R/W 0 A3 Power down 6 R/W 0 A2 Power down 5 R/W 0 A1 Power down 4 R/W 0 A0 Power down 3 R/W 0 Reserved 2 R/W 0 Reserved 1 R/W 0 Reserved 0 R/W 0 Reserved Description 1 = Power down BYTE 3 Bit Type Power up condition 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 PI3DPX1204E Document number: DS40009 Rev 1-2 Description Channel A0 configuration 16 of 49 www.diodes.com Control affected Comment Equalizer EQ0 FG1 Flat gain Swing December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E BYTE 4 Bit Type Power up condition 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 Bit Type Power up condition 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 Bit Type Power up condition 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 Bit Type Power up condition 7:0 R/W Description Channel A1 configuration Control affected Comment Equalizer EQ0 FG1 Flat gain Swing BYTE 5 Description Channel A2 configuration Control affected Comment Equalizer EQ0 FG1 Flat gain Swing BYTE 6 Description Channel A3 configuration Control affected Comment Equalizer EQ0 FG1 Flat gain Swing BYTE 7 Description Control affected Comment Control affected Comment Reserved BYTE 8-15 Bit Type Power up condition Description power up condition : "0" PI3DPX1204E Document number: DS40009 Rev 1-2 17 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 5.2 I2C operation The integrated I2C interface operates as a slave device mode. Standard I2C mode (100 Kbps) is supported with 7-bit addressing and data byte format 8-bit. The device supports Read/Write. The bytes must be accessed in sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A3 to A0 are programmable to support multiple chips environment. The Data is loaded until a Stop sequence is issued. I2C_RESET# Trstpw SCL/SDA ENI2C >2us Trstd 200us Master Load I2C_RESET# >1us HIZ condition Figure 5-1 I2C Reset, Enable and SCL/SDA Timing Diagram Transferring Data Every byte put on the SDA line must be 8-bit long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see the I2C Data Transfer diagram). It will never hold the clock line SCL LOW to force the master into a wait state. Acknowledge Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge clock pulse, it will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I2C Data Transfer diagram. It will generate an acknowledge after each byte has been received. Data Transfer A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, it will watch the next byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit. Data is transferred with the most significant bit (MSB) first. Start & Stop Conditions A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. PI3DPX1204E Document number: DS40009 Rev 1-2 18 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Table 5-1. I2C Address Setting with 4-bits AD[3:0] I2C address: AD3, AD2, AD1, AD0 Data starting location 0000 00H 0001 10H 0010 20H 0011 30H 0100 40H 0101 50H 0110 60H 0111 70H 1000 80H 1001 90H 1010 A0H 1011 B0H 1100 C0H 1101 D0H 1110 E0H 1111 F0H Read Sequence S Slave Address R A DATA W A DATA ... A DATA A P Write Sequence S Slave Address A ... DATA A P A= not acknowledge From master to slave A= acknowledge From slave to master S= start condition P= stop condition Figure 5-2 I2C Read / Write Timing Sequence PI3DPX1204E Document number: DS40009 Rev 1-2 19 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 6. Electrical Specification 6.1 Absolute Maximum ratings Supply Voltage to Ground Potential -0.5 V to +4.6 V DC SIG Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to +25 mA Power Dissipation Continuous 2.1 W ESD, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2 kV to +2 kV Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to +150 C Note Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6.2 Recommended operating conditions Parameter Min. Power supply voltage (VDD to GND)(1) Typ. 3.0 Max 3.6 V I2C (SDA, SCL) 3.6 V Supply Noise Tolerance up to 25 MHz (2) 100 mVp-p 85 C Ambient Temperature 3.3 Units -40 25 Note (1) Typical parameters are measured at VCC = 3.3 0.3V, TA = 25C. They are for the reference purposes, and are not production-tested (2) Allow supply noise (mVp-p sine wave) under typical condition 6.3 Electrical characteristics Over recommend operating supply and temperature range unless otherwise specified. 6.3.1 LVCMOS DC specifications Symbol Parameter Conditions Min. Typ. Max Unit VIH DC input logic high VDD/2 + 0.7 VDD + 0.3 V VIL DC input logic low -0.3 VDD/2 - 0.7 V VOH At IOH = -200A VOL At IOL = -200A V hys Hysteresis of Schmitt trigger input VDD + 0.2 V 0.2 0.8 V V 6.3.2 Power Dissipation Symbol IDD IDDQ Parameter Supply current Quiescent supply current PI3DPX1204E Document number: DS40009 Rev 1-2 Conditions Min. Typ. PRSNT#=0 , SW=1000mVdiff, FG=2.5 256 PRSNT#=0, SW=900mVdiff, FG=2.5 240 PRSNT#=0, SW=800mVdiff, FG=2.5 233 PRSNT#=1, TMDS Output Disable 2.0 20 of 49 www.diodes.com Max. Unit mA 290 mA mA 4.2 mA December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 6.3.3 Package power ratings Package Theta Ja(still air) (C/W) Theta Jc (C/W) Max. Power Dissipation Rating Ta 70 32-pin TQFN (ZL32) 37.05 11.3 1.48W 42-pin TQFN (ZH42) 33.69 15.17 1.63W 6.3.4 Switching I/O characteristics Symbol Parameter VRX-DIFFp-p Peak to peak differential input voltage TR Rise Time TF Falling Time TPLH Conditions Min. Typ. Max. Unit 200 mV Input signal with 30ps rise time, 20% to 80% 31 ps Input signal with 30ps rise time, 20% to 80% 31 ps Low-to-High Propagation Delay 65 ps TPHL High-to-Low Propagation Delay 65 ps TSK_IN- Input Intra-pair Differential Skew tolerance TRA_IN Output Intra-pair Differential Skew 5 TER_OUT Output Inter-pair Differential Skew 8 RJ Add-in Random Jitter at 6Gbps 0.57 DJ Add-in Deterministic Jitter at 6Gbps 6.57 TSX Select to Switch Output S22 Output return loss TSK_INTRA_OUT TSK_IN- R IN ROUT ZRX-HIZ VRX-DIFFPP 10 MHz to 6 Gbps differential 13 2 Gbps to 6 Gbps common mode 8 50 DC Differential Input Impedance 100 DC single-ended output impedance 50 DC Differential output Impedance 100 DC input CM input impedance during reset or power down 200 PI3DPX1204E Document number: DS40009 Rev 1-2 UI 10 ps ps RMS ps ps 10 DC single-ended input impedance Differential Input Peak-to-peak Voltage 0.15 ns dB Operational k 1.4 21 of 49 www.diodes.com Vppd December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Symbol Parameter Conditions VCM- Input source common-mode noise DC - 200MHz NOISE TTX-IDLESET-TOIDLE TTX-IDLETO-DIFFDATA Typ. Max. Unit 150 mVpp Max time to electrical idle after sending an EIOS 4 8 ns Max time to valid differential signal after leaving electrical idle 4 8 ns TPD Latency GP Peaking gain (Compensation at 6Gbps, relative to 100MHz, 100mVp-p sine wave input) GF Min. Flat gain (100MHz, EQ<3:0> = 1000, SW<1:0> = 10) From input to output 0.5 ns EQ<3:0> = 1111 EQ<3:0> = 1000 EQ<3:0> = 0000 8.9 6.6 3.6 dB Variation around typical -3 FG<1:0> = 11 FG<1:0> = 10 FG<1:0> = 01 FG<1:0> = 00 Variation around typical +3 -3.5 -1.5 0.5 2.5 -3 dB dB +3 dB V1dB_100M -1dB compression point of output swing (at 100MHz) SW<1:0> = 11 SW<1:0> = 10 SW<1:0> = 01 SW<1:0> = 00 1400 1300 1200 1100 mVppd V1dB_6G -1dB compression point of output swing (at 6 Gbps) SW<1:0> = 11 SW<1:0> = 10 SW<1:0> = 01 SW<1:0> = 00 1300 1200 1100 1000 mVppd VCoup Channel isolation 100MHz to 6 Gbps 40 100MHz to 6 Gbps, FG<1:0> = 11, EQ<3:0> = 0000 0.5 100MHz to 6 Gbps, FG<1:0> = 11, EQ<3:0> = 1010 0.4 100MHz to 6 Gbps, FG<1:0> = 11, EQ<3:0> = 0000 0.7 100MHz to 6 Gbps, FG<1:0> = 11, EQ<3:0> = 1010 0.8 Vnoise_inInput-referred noise(2) put Vnoise_ output Output-referred noise(2) dB mVRMS 1.6 mVRMS Note (1) Measured using a vector-network analyzer (VNA) with -15dBm power level applied to the adjacent input. The VNA detects the signal at the output of the victim channel. All other inputs and outputs are terminated with 50. (2) Guaranteed by design. PI3DPX1204E Document number: DS40009 Rev 1-2 22 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Test Unit Board Signal Generater (BERT) D.U.T. In Out Pre-trace Board TP1 Post-trace Board TP2 TP3 TP4 Figure 6-1 Electrical parameter test setup Latency Delay Time, tDD Input Intra-Pair Skew, tSK_INTRA_IN INxP 50% INxN Output Intra-Pair Skew, tSK_INTRA_OUT OUTxP 50% OUTxN Output Inter-Pair Skew, tSK_INTER_OUT OUTyP Falling time, tF 80% 20% 50% 20% OUTyN 80% Rising time, tR Intra-Pair and Inter-Pair Differential Signaling Skew Figure 6-2 Intra and Inter-pair Differential Skew definition Common Mode Voltage VCM = (|VD+ + VD-| / 2) VCMP = (max |VD+ + VD-| / 2) VD+ VDIFF VCM VD- V_D + -V_D- DIFFp-p Symmetric Differential Swing VDIFFp-p = (2 * max |VD+ - VD-|) 0V VDIFFP-P Asymmetric Differential Swing VDIFFp-p = (max |VD+ - VD-| {VD+ > VD-} + max |VD+ - VD-| {VD+ < VD-}) Figure 6-3 Definition of Peak-to-peak Differential voltage PI3DPX1204E Document number: DS40009 Rev 1-2 23 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 50 50 RX_+ TX_+ RX_- TX_- POWER METER GIGATRONICS 8652A WITH 80301A HEAD (10MHz to 18GHz) BALUN PSPL 5315A (200kHz TO 17GHz) Figure 6-4 Noise test configuration 4-PORT VECTOR NETWORK ANALYZER N52454 AGGRESSOR SIGNAL (0dBm) 50 RX1+ TX1+ RX1- TX1- INPUT 50 50 RX2+ 50 RX2- TX2+ TX2- OUTPUT Figure 6-5 Channel-isolation test configuration Figure 6-6 PI3DPX1204E Document number: DS40009 Rev 1-2 24 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 6.4 I2C Interface Bus Symbol Parameter VDD Nominal Bus Voltage Freq Bus Operation Frequency VIH DC input logic high VDD/2 + 0.7 VIL DC input logic low -0.3 VOL DC output logic low IOL = 3mA Current Through Pull-Up Resistor High Power specification Ipullup or Current Source Ileak-bus Input leakage per bus segment Ileak-pin Input leakage per device pin CI Capacitance for SDA/SCL tBUF Bus Free Time Between Stop and Start condition tHD:STA Hold time after (Repeated) Start condition. After this period, the first clock is generated. TSU:STA TSU:STO Conditions Min. Typ. 3.0 Max Units 3.6 V 400 kHz VDD + 0.3 VDD/2 - 0.7 V V 0.4 V 3.0 3.6 mA -200 200 uA -15 uA 10 pF 1.3 us 0.6 us Repeated start condition setup time 0.6 us Stop condition setup time 0.6 us 0 ns At pull-up, Max THD:DAT Data hold time TSU:DAT Data setup time 100 ns tLOW Clock low period 1.3 us tHIGH Clock high period tF Clock/Data fall time 0.6 tR tPOR 50 us 300 ns Clock/Data rise time 300 ns Time in which a device must be operation after power-on reset 500 ms Note: (1) Recommended maximum capacitance load per bus segment is 400pF. (2) Compliant to I2C physical layer specification. (3) Ensured by Design. Parameter not tested in production. PI3DPX1204E Document number: DS40009 Rev 1-2 25 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Figure 6-7 I2C Timing definition PI3DPX1204E Document number: DS40009 Rev 1-2 26 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 7. Applications 7.1 DC/AC-coupled Application High-speed differential signal traces VDD 50 VBias 50 50 A0RX+ A0TX+ A0RX- A0TX- GND 50 GND Receiver DC-Coupled Differential Signaling Application Circuits VDD VBias 50 50 4.7nF A0RX+ 50 4.7nF 50 A0TX+ A0TX- A0RX- GND Receiver AC-Coupled Differential Signaling Application Circuits Figure 7-1 DC/AC-coupled application diagram PI3DPX1204E Document number: DS40009 Rev 1-2 27 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 7.2 Sink-side Redriver Application EN +3.3V AP2151 Power Switch Regulator 5-> 3.3V +5V +3.3V PI3HDX1204xx ReDriver HDMI Tx HDMI Sink Device Scalar/SoC DDC-ch DVI DVI NoteBook PC Sink-side ( i.e. Display ) Figure 7-2 HDMI Sink-side application 7.3 Channels/Polarity Swap Linear Redriver does not have built-in internal channel/polarity switch. Transmitter can send swapped polarity signal to the Redriver. Transmitter Pin-map ML3N ML3P ML2N ML2P ML1N ML1P ML0N ML0P ML0N ML0P ML1N ML1P ML2N ML2P ML3N ML3P Connector pin-map ReDriver A0RX+ A0TX+ A0RX- A0TX- A1RX+ A1TX+ A1RX- A1TX- A2RX+ A2TX+ TMDS_DATA1_DN A2TX- TMDS_DATA1_DP A3TX+ A3TX- TMDS_DATA2_DN A2RXA3RX+ A3RX- A0RX+ A0TX+ A0RX- A0TX- A1RX+ A1TX+ A1RX- A1TX- A2RX+ A2RX- A2TX+ A3RX+ A3RX- A3TX+ A3TX- A2TX- TMDS_CLK_N TMDS_CLK_P TMDS_DATA0_DN TMDS_DATA0_DP TMDS_DATA2_DP TMDS_DATA2_DN TMDS_DATA2_DP TMDS_DATA1_DN TMDS_DATA1_DP TMDS_DATA0_DN TMDS_DATA0_DP TMDS_CLK_N TMDS_CLK_P Figure 7-3 Polarity Swap Connection PI3DPX1204E Document number: DS40009 Rev 1-2 28 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 7.4 Output Eye Diagram 7.4.1 Trace Card Loss Informations Frequency 3 GHz 6GHz Units 6 inch Input Trace -1.43 -4 dB 12 inch Input Trace -6.1 -11 dB 18 inch Input Trace -8.34 -15 dB 30 inch Input Trace -10.14 -18 dB 36 inch Input Trace -12.13 -22 dB 48 inch Input Trace -16.42 -29 dB Table 7-1. Characterization Trace Card dB Loss Information Figure 7-4 Trace board photo PI3DPX1204E Document number: DS40009 Rev 1-2 29 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 7.4.2 Output Eye Diagram measurement Figure 7-5 Eye Width vs. EQ plots at 6 Gbps, PRBS2^23-1, FG=11 (Gain +2.5dB) Eye Width vs EQ, FG =1000mV, Gain=+2.5dB (Input Swing=800mVd) Figure 7-6 Eye Width vs. EQ plots at 6 Gbps, PRBS2^23-1, FG=10 (Gain +0.5dB) Eye Height vs EQ, FG=1000mV, Gain=+2.5dB (input swing=800mVd) PI3DPX1204E Document number: DS40009 Rev 1-2 30 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Figure 7-7 Frequency response vs EQ with FG=11(+2.5dB), Output Swing=1000mV, Vdd=3.0V, 25C, Input Power=-15dBm, No Input Trace 7.4.3 Output Eye diagram Condition: PRBS 2^23-1 pattern, Input Swing=800mVdiff, Output Swing= 1000mVdiff Table 7-2. Output Eye diagram by EQ changes at FG 0.5dB No Trace, FG=0.5dB 6-in trace, FG=0.5dB 12-in trace, FG=0.5dB 18-in trace, FG=0.5dB EQ=3dB EQ=3dB EQ=5dB EQ=6dB 24-in trace, FG=0.5dB 30-in trace, FG=0.5dB 36-in trace, FG=0.5dB 48-in trace, FG=0.5dB EQ=10dB EQ=13.3dB EQ=14.5dB EQ=15dB PI3DPX1204E Document number: DS40009 Rev 1-2 31 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Table 7-3. Output Eye Diagram by EQ changes at FG 2.5dB No Trace, FG=2.5dB 6-in trace, FG=2.5dB 12-in trace, FG=2.5dB 18-in trace, FG=2.5dB EQ=3dB EQ=3dB EQ=5dB EQ=8dB 24-in trace, FG=2.5dB 30-in trace, FG=2.5dB 36-in trace, FG=2.5dB 48-in trace, FG=2.5dB EQ=13dB EQ=15dB EQ=15dB EQ=15dB PI3DPX1204E Document number: DS40009 Rev 1-2 32 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 7.5 Layout Guidelines As transmission data rate increases rapidly, any flaws and/or mis-matches on PCB layout are amplified in terms of signal integrity. Layout guideline for high-speed transmission is highlighted in this application note. 7.5.1 Power and Ground To provide a clean power supply for high-speed device, few recommendations are listed below: * * * * * * Power (VDD) and ground (GND) pins should be connected to corresponding power planes of the printed circuit board directly without passing through any resistor. The thickness of the PCB dielectric layer should be minimized such that the VDD and GND planes create low inductance paths. One low-ESR 0.1uF decoupling capacitor should be mounted at each VDD pin or should supply bypassing for at most two VDD pins. Capacitors of smaller body size, i.e. 0402 package, is more preferable as the insertion loss is lower. The capacitor should be placed next to the VDD pin. One capacitor with capacitance in the range of 4.7uF to 10uF should be incorporated in the power supply decoupling design as well. It can be either tantalum or an ultra-low ESR ceramic. A ferrite bead for isolating the power supply for Pericom high-speed device from the power supplies for other parts on the printed circuit board should be implemented. Several thermal ground vias must be required on the thermal pad. 25-mil or less pad size and 14-mil or less finished hole are recommended. V DD P la ne Bypass noise Power Flow Several Thermal GND Vias must be required on the Thermal Pad area 10uF 1uF 0.1uF 0.1uF VIN Center Pad GND Plane VIN G N D P la ne 0.1uF VIN Figure 7-8 Decoupling Capacitor Placement Diagram PI3DPX1204E Document number: DS40009 Rev 1-2 33 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 7.5.2 High-speed signal Routing Well-designed layout is essential to prevent signal reflection: * * For 90 differential impedance, width-spacing-width micro-strip of 6-7-6 mils is recommended; for 100 differential impedance, width-spacing-width micro-strip of 5-7-5 mils is recommended. Differential impedance tolerance is targeted at 15%. Figure 7-9 Trace Width and Clearance of Micro-strip and Strip-line PI3DPX1204E Document number: DS40009 Rev 1-2 34 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E * For micro-strip, using 1/2oz Cu is fine. For strip-line in 6+ PCB layers, 1oz Cu is more preferable. Figure 7-10 4-Layer PCB Stack-up Example Figure 7-11 6-Layer PCB Stack-up Example PI3DPX1204E Document number: DS40009 Rev 1-2 35 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E * Ground referencing is highly recommended. If unavoidable, stitching capacitors of 0.1uF should be placed when reference plane is changed. Figure 7-12 Stitching Capacitor Placement * * To keep the reference unchanged, stitching vias must be used when changing layers. Differential pair should maintain symmetrical routing whenever possible. The intra-pair skew of micro-strip should be less than 5 mils. * * To keep the reference unchanged, stitching vias must be used when changing layers. Differential pair should maintain symmetrical routing whenever possible. The intra-pair skew of micro-strip should be less than 5 mils. Figure 7-13 Layout Guidance of Matched Differential Pair * * * For minimal crosstalk, inter-pair spacing between two differential micro-strip pairs should be at least 20 mils or 4 times the dielectric thickness of the PCB. Wider trace width of each differential pair is recommended in order to minimize the loss, especially for long routing. More consistent PCB impedance can be achieved by a PCB vendor if trace is wider. Differential signals should be routed away from noise sources and other switching signals on the printed circuit board. PI3DPX1204E Document number: DS40009 Rev 1-2 36 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E * To minimize signal loss and jitter, tight bend is not recommended. All angles should be at least 135 degrees. The inner air gap A should be at least 4 times the dielectric thickness of the PCB. Figure 7-14 Layout Guidance of Bends * Stub creation should be avoided when placing shunt components on a differential pair. Figure 7-15 Layout Guidance of Shunt Component * Placement of series components on a differential pair should be symmetrical. Figure 7-16 Layout Guidance of Series Component PI3DPX1204E Document number: DS40009 Rev 1-2 37 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E * Stitching vias or test points must be used sparingly and placed symmetrically on a differential pair. Figure 7-17 Layout Guidance of Stitching Via PI3DPX1204E Document number: DS40009 Rev 1-2 38 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 7.6 HDMI 2.0 Compliance Test Figure 7-18 HDMI 2.0 CTS test setup* Note: Table 7-4. Application Trace Card Information for CTS test HDMI FR4 trace Insertion loss @ 6Gbps PI3DPX1204E Document number: DS40009 Rev 1-2 0 in 6 in 12 in 18 in 24 in 30 in 36 in -5.91 dB -9.75 dB -10.47 dB -13.05 dB -15.87 dB -16.97 dB -21.20 dB 39 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Figure 7-19 HDMI 2.0 CTS Test Report PI3DPX1204E Document number: DS40009 Rev 1-2 40 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E PI3DPX1204E Document number: DS40009 Rev 1-2 41 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 8. Mechanical/Packaging 8.1 Mechanical Outline 15-0222 Figure 8-1 32-pin TQFN package mechanical PI3DPX1204E Document number: DS40009 Rev 1-2 42 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Figure 8-2 42-pin TQFN package mechanical PI3DPX1204E Document number: DS40009 Rev 1-2 43 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Figure 8-3 Thermal Via Pad Area: 32-pin PI3DPX1204E Document number: DS40009 Rev 1-2 44 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 8.2 Part Marking Information Product marking follows our standard part number ordering information. PI X1 X2X3X4 X5X6X7X8X9 X10X11 X12X13 I E X Packaging i.e) Blank = Tube; X = Tape & Reel Pb-Free i.e) E = Pb-free & Green Temperature Range i.e) Blank=Commerial temp, I=Industrial temp Package Code X12:Product Skew & X13:Version i.e) Blank = 1st release, B1 = Type B and Version 1 Product IO Configuration i.e) X5X6= Data Speed, X7=Total IO ports, X8= Port in, X9= Port out Device Family Code: X2X3: Protocol, X4:Technology i.e) DPX = DisplayPort Redriver, EQX = Generic Redriver, HDT=HDMI Retimer Voltage Supply Code i.e) "1" = 0.5~1.5V, "2" = 1.5~2.5V, "3" = 2.5~3.5V Power Supply PI = Pericom Figure 8-4 Part number information PI3HDX 1204EZHE YYYWWXX 1st Y: Die Rev YY: Year WW: Workweek 1st X: Assembly Code 2nd X: Fab Code Figure 8-5 Package marketing information PI3DPX1204E Document number: DS40009 Rev 1-2 45 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 8.3 Tape & Reel Materials and Design 8.3.1 Carrier Tape The Pocketed Carrier Tape is made of Conductive Polystyrene plus Carbon material (or equivalent). The surface resistivity is 106 /sq. maximum. Pocket tapes are designed so that the component remains in position for automatic handling after cover tape is removed. Each pocket has a hole in the center for automated sensing if the pocket is occupied or not, thus facilitating device removal. Sprocket holes along the edge of the center tape enable direct feeding into automated board assembly equipment. See Figures 3 and 4 for carrier tape dimensions. 8.3.2 Cover Tape Cover tape is made of Anti-static Transparent Polyester film. The surface resistivity is 107 /Sq. Minimum to 1011Ohm sq. maximum. The cover tape is heat-sealed to the edges of the carrier tape to encase the devices in the pockets. The force to peel back the cover tape from the carrier tape shall be a MEAN value of 20 to 80gm (2N to 0.8N). 8.3.3 Reel The device loading orientation is in compliance with EIA-481, current version (Figure 2). The loaded carrier tape is wound onto either a 13-inch reel, (Figure 4) or 7-inch reel. The reel is made of Anti-static High-Impact Polystyrene. The surface resistivity 107 / sq. minimum to 1011 /sq. max. NOTE: LABELS TO BE PLACED ON THE REEL OPPOSITE PIN 1 BARCODE LABEL TOP COVER TAPE SPROCKET HOLE (ROUND) CARRIER TAPE EMBOSSED CAVITY Figure 8-6 Tape & Reel label information CARRIER TAPE Top Left PIN 1 ORIENTATION Top Right PIN 1 ORIENTATION COVER TAPE END START COVER TAPE TRAILER COMPONENTS LEADER Bottom Left PIN 1 ORIENTATION Figure 8-7 Tape leader and trailer pin 1 orientations PI3DPX1204E Document number: DS40009 Rev 1-2 46 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Round Sprocket Holes Cover Tape T Po Do T1 (10 pitches cumulative tolerance on tape 0.2mm Ao P2 Bo B1 E1 F Embossed Cavity So Ko W R (min) D1 S1 Center lines of Cavity T2 P1 Direction of Unreeling Figure 8-8 Standard embossed carrier tape dimensions Table 8-1. Constant Dimensions Tape Size 8mm 12mm 16mm 24mm 32mm 44mm D0 D1 (Min) E1 P0 P2 1.0 1.5 +0.1 -0.0 1.5 R (See Note 2) 2.0 0.05 1.75 0.1 4.0 0.1 2.0 S1 (Min) T T1 (Max) (Max) 25 0.6 30 0.6 2.0 0.1 2.0 0.15 0.1 N/A (See Note 3) 50 Table 8-2. Variable Dimensions Tape Size 8mm 12mm 16mm 24mm 32mm 44mm P1 Specific per package type. Refer to FR-0221 (Tape and Reel Packing Information) B1 (Max) E2 (Min) 4.35 8.2 12.1 20.1 23.0 35.0 6.25 10.25 14.25 22.25 N/A N/A F 3.5 0.05 5.5 0.05 7.5 0.1 11.5 0.1 14.2 0.1 20.2 0.15 So T2 W (Max.) (Max) N/A (see note 4) 2.5 6.5 8.0 28.4 0.1 40.4 0.1 12.0 16.0 8.3 12.3 16.3 24.3 32.3 44.3 A0, B0, & K0 See Note 1 NOTES: 1. A0, B0, and K0 are determined by component size. The cavity must restrict lateral movement of component to 0.5mm maximum for 8mm and 12mm wide tape and to 1.0mm maximum for 16,24,32, and 44mm wide carrier. The maximum component rotation within the cavity must be limited to 20o maximum for 8 and 12 mm carrier tapes and 10o maximum for 16 through 44mm. 2. Tape and components will pass around reel with radius "R" without damage. 3. S1 does not apply to carrier width 32mm because carrier has sprocket holes on both sides of carrier where DoS1. 4. So does not exist for carrier 32mm because carrier does not have sprocket hole on both side of carrier. PI3DPX1204E Document number: DS40009 Rev 1-2 47 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E Table 8-3. Reel dimensions by tape size Tape Size A 8mm 12mm 178 2.0mm or 3302.0mm N (Min) See Note A 60 2.0mm or 1002.0mm 16mm 24mm 32mm 330 2.0mm 44mm 100 2.0mm W2 (Max) W1 8.4 +1.5/-0.0 mm 12.4 +2.0/0.0 mm 16.4 +2.0/0.0 mm 24.4 +2.0/0.0 mm 32.4 +2.0/-0.0 mm 44.4 +2.0/-0.0 mm W3 B (Min) C Shall Accommodate Tape Width Without Interference 1.5mm D (Min) 14.4 mm 18.4 mm 22.4 mm 30.4 mm 38.4 mm 13.0 +0.5/-0.2 mm 20.2mm 50.4 mm NOTE: A. If reel diameter A=178 2.0mm, then the corresponding hub diameter (N(min)) will by 60 2.0mm. If reel diameter A=3302.0mm, then the corresponding hub diameter (N(min)) will by 1002.0mm. PI3DPX1204E Document number: DS40009 Rev 1-2 48 of 49 www.diodes.com December 2017 (c) Diodes Incorporated A product Line of Diodes Incorporated PI3HDX1204E 9. Important Notice DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. 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Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks. This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by Diodes Incorporated. LIFE SUPPORT Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein: A. Life support devices or systems are devices or systems which: 1. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. Copyright (c) 2016, Diodes Incorporated www.diodes.com -- PI3DPX1204E Document number: DS40009 Rev 1-2 49 of 49 www.diodes.com December 2017 (c) Diodes Incorporated