Rev. 1.5 (September 2014) 1 © DLP Design, Inc.
D
DL
LP
P-
-F
FP
PG
GA
A
LEAD-FREE
USB - FPGA MODULE
PWREN VCCIO
Dual Channel USB IC
VCC
USBDP CH B
USBDM
FTDI FT2232D
CH A
USB Type 'B'
Connector to
Host Windows/
Linux/Mac PC
XILINX
FPGA
XC3S250E
-4TQ144
5V
6MHz
Clock
50-pin,
0.9-inch
Wide
Interface
Headers
5V
MOSFET
Power
Switch
128K x 8
SRAM
SPI Flash
VREGs
3.3V
APPLICATIONS:
- Rapid Prototyping
- Educational Tool
- Industrial/Process
Control
FEATURES:
- Built-In Configuration Loader—Writes Bit File Directly
to SPI Flash via Full-Speed USB Interface
- 40 I/O Channels: 27 Input/Output; 13 Input Only
- Xilinx XC3S250E-4TQ144 FPGA
- On-Board 128K x 8, 70nS SRAM
- USB Port Powered
- USB 1.1 and 2.0 Compatible Interface
- Small Footprint: 2.8 x 1.-Inch PCB
- Standard 50-Pin, 0.9-Inch DIP Interface
Rev. 1.5 (September 2014) 2 © DLP Design, Inc.
1.0 INTRODUCTION
The DLP-FPGA Module is a low-cost, compact prototyping module that can be used for rapid proof of
concept or for educational environments. The module is based on the Xilinx Spartan 3E and Future
Technology Devices International’s FT2232D Dual-Channel USB IC. Used by itself or with the
optional 200-page training manual, the DLP-FPGA provides both the beginner as well as the
experienced engineer with a rapid path to developing FPGA-based designs. When combined with the
free WebPACK™ Tools from Xilinx, this module is more than sufficient for creating anything from
basic logical functions to a highly complex system controller.
As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files
directly to the SPI Flash—no external programmer is required. This represents a savings of as much
as $200 in that no additional programming cable is required for configuring the FPGA. All that is
needed to load bit files to the DLP-FPGA is a Windows software utility (free with purchase), a
Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool
environment using a Xilinx programming cable (purchased separately).
The DLP-FPGA is fully compatible with the free ISE™ WebPACK™ tools from Xilinx. ISE WebPACK
offers the ideal development environment for FPGA designs with HDL synthesis and simulation,
implementation, device fitting and JTAG programming.
The DLP-FPGA has on-board voltage regulators that generate all required power supply voltages
from a single 5-volt source. Power for the module can be taken from either the host USB port or from
a user-supplied, external 5-volt power supply.
Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025 square
inch post DIP header. Other on-board features include a 128K x 8 static RAM IC for user projects,
and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools.
2.0 FPGA SPECIFICATIONS
The FPGA device used on the DLP-FPGA is the Xilinx Spartan 3E: XC3S250E-4TQ144.
• Part Number: XC3S250E
• System Gates: 250K
• Equivalent Logic Cells: 5,508
• CLB Array
o Rows: 34
o Columns: 26
o Total CLB’s: 612
o Total Slices: 2,448
• Distributed RAM Bits: 38K
• Block RAM Bits: 216K
• Dedicated Multipliers: 12
• DCM’s: 4
Rev. 1.5 (September 2014) 3 © DLP Design, Inc.
3.0 BITLOADAPP SOFTWARE
Windows software is provided for use with the DLP-FPGA that will load an FPGA configuration (.bit)
file directly to the SPI Flash device via the USB interface. This app (shown below) will allow the user
to erase the flash, verify the erasure and then program and verify the flash:
4.0 JTAG INTERFACE
The easiest way to load an FPGA configuration (bit file) to the FPGA is to run the BitLoadApp
software, then select and program a file from the local hard drive directly to the SPI flash. Once
written to the SPI flash, the configuration will load to the FPGA and execute. Alternatively, a
traditional JTAG header location is provided on the DLP-FPGA giving the user access to the pins on
the FPGA required by the development tools. (Refer to the schematic at the end of this datasheet for
details.)
5.0 EEPROM SETUP / MPROG
The DLP-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively to
load an FPGA configuration (bit file) to the SPI flash. This configuration data is automatically
transferred to the FPGA when power is applied to the module. Channel B is used for communication
between the FPGA and host PC at run time. A 93C56B EEPROM connected to the USB interface IC
is used to store the setup for the two channels. The parameters stored in the EEPROM include the
Vendor ID (VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX)
and port type (UART serial or FIFO parallel).
As mentioned above, Channel A is used exclusively for loading the FPGA’s configuration to the SPI
flash, and Channel B is used for communication between the host PC and the DLP-FPGA. As such,
the D2XX drivers and FIFO mode must be selected in the EEPROM for Channel A. Channel B must
use the FIFO mode, but can use either the VCP or D2XX drivers. The VCP drivers make the DLP-
FPGA appear as an RS232 port to the host app. The D2XX drivers provide faster throughput, but
require working with a .lib or .dll library in the host app.
The operational modes and other EEPROM selections are written to the EEPROM using the MPROG
utility. This utility and its manual are available for download from the bottom of the page at
www.dlpdesign.com.
Rev. 1.5 (September 2014) 4 © DLP Design, Inc.
6.0 TEST BIT FILE
A test file is provided as a download from the DLP Design website that provides rudimentary access
to the I/O features of the DLP-FPGA.
The following features are provided:
• Ping
• Read the High/Low State of the Input-Only Pins
• Drive I/O Pins High/Low or Read their High/Low State
• Simple Loopback on Channel B
• Simple Read/Write of Each Address in the SRAM
This bit file is available from the DLP-FPGA’s download page.
Rev. 1.5 (September 2014) 5 © DLP Design, Inc.
7.0 USB DRIVERS
USB drivers for the following operating systems are available for download from the DLP Design
website at http://www.dlpdesign.com:
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Notes:
1. The bit file load utility only runs on the Windows platforms.
2. The bit file load utility requires the use of USB channel A, and channel A is dedicated to this
function.
3. If you are using the dual-mode drivers from FTDI (CDM2.02.04) and wish to use the Virtual
COM Port (VCP) drivers for Channel B communications, then it may be necessary to disable
the D2XX drivers first via Device Manager. To do so, right click on the Channel B entry under
USB Controllers that appears when the DLP-FPGA is connected, select Properties, select the
Advanced tab, check the option for “Load VCP” and click OK. Once you unplug and then
replug the DLP-FPGA, a COM port should appear in Device Manager under Ports (COM &
LPT).
8.0 USING THE DLP-FPGA
Select a power source via Header Pins 23 and 24, and connect the DLP-FPGA to the PC to initiate
the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each other.
This will result in operational power being taken from the host PC. Once the drivers are loaded, the
DLP-FPGA is ready for use.
FPGA
USB
Pin 25 Pin 26
Top View (Interface Headers on bott om of PCB)
Pin 1 Pin 50
SRAM
Rev. 1.5 (September 2014) 6 © DLP Design, Inc.
T
TA
AB
BL
LE
E
1
1
NN (dec)* NN (hex)* Name FPGA Pin JP2 Pin
0 0 user_io(0) U5 Pin 58 JP2 Pin 2
1 1 user_io(1) U5 Pin 59 JP2 Pin 4
2 2 user_io(2) U5 Pin 93 JP2 Pin 5
3 3 user_io(3) U5 Pin 94 JP2 Pin 6
4 4 user_io(4) U5 Pin 96 JP2 Pin 7
5 5 user_io(5) U5 Pin 97 JP2 Pin 8
6 6 user_io(6) U5 Pin 103 JP2 Pin 9
7 7 user_io(7) U5 Pin 104 JP2 Pin 10
8 8 user_io(8) U5 Pin 105 JP2 Pin 12
9 9 user_io(9) U5 Pin 106 JP2 Pin 13
10 A user_io(10) U5 Pin 112 JP2 Pin 14
11 B user_io(11) U5 Pin 113 JP2 Pin 15
12 C user_io(12) U5 Pin 116 JP2 Pin 16
13 D user_io(13) U5 Pin 117 JP2 Pin 17
14 E user_in(14) [INPUT ONLY!] U5 Pin 119 JP2 Pin 18
15 F user_in(15) [INPUT ONLY!] U5 Pin 120 JP2 Pin 19
16 10 user_io(16) U5 Pin 122 JP2 Pin 20
17 11 user_io(17) U5 Pin 123 JP2 Pin 21
18 12 user_io(18) U5 Pin 124 JP2 Pin 22
19 13 user_io(19) U5 Pin 125 JP2 Pin 27
20 14 user_io(20) U5 Pin 126 JP2 Pin 29
21 15 user_io(21) U5 Pin 130 JP2 Pin 30
22 16 user_io(22) U5 Pin 131 JP2 Pin 31
23 17 user_io(23) U5 Pin 132 JP2 Pin 32
24 18 user_io(24) U5 Pin 134 JP2 Pin 33
25 19 user_io(25) U5 Pin 135 JP2 Pin 34
26 1A user_io(26) U5 Pin 139 JP2 Pin 35
27 1B user_io(27) U5 Pin 140 JP2 Pin 36
28 1C user_io(28) U5 Pin 142 JP2 Pin 37
30 1E user_in(0) U5 Pin 10 JP2 Pin 49
31 1F user_in(1) U5 Pin 12 JP2 Pin 48
32 20 user_in(2) U5 Pin 29 JP2 Pin 47
33 21 user_in(3) U5 Pin 31 JP2 Pin 46
34 22 user_in(4) U5 Pin 36 JP2 Pin 45
35 23 user_in(5) U5 Pin 38 JP2 Pin 44
36 24 user_in(6) U5 Pin 41 JP2 Pin 43
37 25 user_in(7) U5 Pin 47 JP2 Pin 42
38 26 user_in(8) U5 Pin 48 JP2 Pin 41
39 27 user_in(9) U5 Pin 66 JP2 Pin 39
40 28 user_in(10) U5 Pin 69 JP2 Pin 38
Read: 29,
>40 Read:1D,
>29 Returns Read Pin Error E4 n/a n/a
Write: 14,
15, >30 Write: E, F,
>1E Returns Write Pin Error E2 for Pin
Clear (low), or E3 for Pin Set
(high)
n/a n/a
Ground 1,11,25,26,40,50
FPGA_RESET 128 3
5VIN – Module power source 23
PORTVCC – Power from Host PC 24
VCCSW – 5V power after host
enumerates the USB port 28
*
*N
No
ot
te
e:
:
This is the I/O number for use with the Test Bit File described in Section 7.
Rev. 1.5 (September 2014) 7 © DLP Design, Inc.
9.0 MECHANICAL DIMENSIONS IN INCHES (MM)
0.23 typ
(5.8 typ)
0.21 typ
(5.3 typ)
0.65 typ
(16.5 typ)
1.2 typ
(30.5 typ)
0.44 typ
(11.2 typ)
2.8 typ
(71.1 typ)
0.1 typ
(2.5 typ) 0.29 typ
(7.3 typ)
0.1 typ
(2.5 typ)
.9 typ
(22.9 typ)
1.2 typ
(30.5 typ)
Rev. 1.5 (September 2014) 8 © DLP Design, Inc.
10.0 DISCLAIMER
© DLP Design, Inc., 2007 - 2014
Neither the whole nor any part of the information contained herein nor the product described in this
manual may be adapted or reproduced in any material or electronic form without the prior written
consent of the copyright holder.
This product and its documentation are supplied on an as-is basis, and no warranty as to their
suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any
claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory
rights are not affected. This product or any variant of it is not intended for use in any medical
appliance, device, or system in which the failure of the product might reasonably be expected to result
in personal injury.
This document provides preliminary information that may be subject to change without notice.
11.0 CONTACT INFORMATION
DLP Design, Inc.
1605 Roma Lane
Allen, TX 75013
Phone: 469-964-8027
Fax: 415-901-4859
Email Sales: sales@dlpdesign.com
Email Support: support@dlpdesign.com
Website URL: http://www.d lpdesign.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I/O Set at
3.3V
Universal
Serial Bus
Connector
NC
Downloading
FPGA Code
EEPROM, 2 MHz, 128x16
NC
500mA 240-2390-2
MI0805K601R-10
For FPGA configuration via
SPI only.
DLP-FPGA
Page 1
FTDI_D1
FTDI_RD
FTDI_TXE
5VCC
FTDI_RXF
FTDI_D4
FTDI_WR
FTDI_D2
SPI_DIN
FTDI_D3
FTDI_D0
FTDI_D7
FTDI_SI
VCCSW
FTDI_D5
FTDI_D65VCC
SPI_INIT
USER_IN1
USER_IN4
USER_IN9
USER_IO1
USER_IN7
USER_IN2
USER_IN0
USER_IO2
USER_IN8
USER_IN6
USER_IO4 USER_IN5
USER_IO0
USER_IO17
USER_IO12
USER_IO16 USER_IO23
USER_IO22
USER_IO11
USER_IO19
USER_IO25
USER_IO20
USER_IO24
USER_IN3
USER_IO21
USER_IO10
USER_IN12
USER_IO18
USER_IN11
USER_IO13 USER_IO26
USER_IO6
USER_IO28
USER_IO5
USER_IO7
USER_IO27
USER_IO9
USER_IO8 USER_IN10
USER_IO3
PORTVCC
5VIN
GND
VCCSW
GND
GND
FPGA_RESET
GND
GND
GND
SPI_PROG
FPGA_RESET
SPI_CLK
SPI_MOSI
SPI_CSO_B
6MHz
5VIN
PORTVCC
3V3X
3V3X
CN1
CN-USB 1
2
3
4
5
FB1
Ferrite Bead
1 2
C34
10uF
R1
470
C7
0.033uF
C6
0.1uF
R2
27
R3
27
C2
0.1uF
C1
0.01uF
R6 1.5K
CR1
6.00MHz
U3
93C56B
1
2
3
4
8
7
6
5
CS
SK
DIN
DOUT
VCC
NC
ORG
GND
R7 10K R4 2.2K
R5
2.2K
C10
0.1uF
JP2
CONN PCB 25x2
8
7
6
1
2
3
4
5
10
9
12
11
13
15
14
17
16
18
20
19
25
24
23
22
21
34
33
32
31
30
29
28
27
26
40
39
38
37
36
35
50
49
48
47
46
45
44
43
42
41
8
7
6
1
2
3
4
5
10
9
12
11
13
15
14
17
16
18
20
19
25
24
23
22
21
34
33
32
31
30
29
28
27
26
40
39
38
37
36
35
50
49
48
47
46
45
44
43
42
41
FB2
Ferrite Bead
1 2
Q2
IRLML6402
U2
FT2232D
5
44
4
48
1
2
45
9
18
47
6
46
42
3
8
7
43
24
23
22
21
20
19
17
16
15
13
12
11
10
40
39
38
37
36
35
33
32
30
29
28
27
26
41
25
34 14
31
RSTOUT#
XTOUT
RESET#
EECS
EESK
EEDATA
AGND
GND
GND
TEST
3V3OUT
AVCC
VCC
VCC
USBDM
USBDP
XTIN
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AC0
AC1
AC2
AC3
SI/WUA
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BC0
BC1
BC2
BC3
SI/WUB
PWREN
GND
GND VCCIOA
VCCIOB
C5
0.1uF
R28
10K 5%
C39
0.1uF
C11
47pF
C8
0.01uF
UPLOAD
RED
C12
0.47uF
C4
0.033uF
R16 27
R17 27
R13
150 5%
C3
0.1uF C33
10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SRAM, 128K x 8
2.5 mS ramp up
2.5V REGULATOR
1.2V REGULATOR
1.5A Maximum
3.3V REGULATOR
200mA Maximum
200mA Maximum
SPI
Flash
TDI
TDO
TCK
TMS
DLP-FPGA
Page 2
DNS
DNS
SRAM_D6
SRAM_D2
SRAM_D4
SRAM_D1
SRAM_D5
SRAM_D3
FTDI_RD
FTDI_D4
FDTI_D2
FDTI_D3
FDTI_D1
FTDI_TXE
SPI_MOSI
FTDI_D0
FTDI_D5
FPGA_RESET
FDTI_D7
FDTI_D6
SPI_PROG
SPI_INIT
JTAG_DIN
JTAG_TMS
JTAG_TCK
FTDI_RXF
SPI_DIN
6MHz
SPI_CLK
SRAM_D7
SRAM_D6 SRAM_A6
SRAM_D0
SRAM_A8
SRAM_A9
SRAM_D1
SRAM_A5
SRAM_D4
SRAM_A2
SRAM_A0
SRAM_A10
SRAM_A12
SRAM_D2 SRAM_A1
SRAM_A4
SRAM_A16
SRAM_A3
SRAM_A11
SRAM_A13
SRAM_A7
SRAM_D5
SRAM_D3
SRAM_A14
SRAM_A15
SRAM_A2
SRAM_A5
SRAM_A16
SRAM_A13
SRAM_A15
SRAM_A11
SRAM_A12
SRAM_A1
SRAM_A6
SRAM_A8
SRAM_A4
SRAM_A9
SRAM_A14
SRAM_A0
SRAM_A7
SRAM_A3
USER_IN0
USER_IN1
FTDI_SI
USER_IN2
USER_IN3
SRAM_WE
SRAM_WE
USER_IN4
USER_IN5
USER_IN6
USER_IN7
USER_IN8
SRAM_OE
SRAM_D0
USER_IO0
USER_IO1
USER_IO2
USER_IO3
USER_IO4
USER_IO5
USER_IO6
USER_IO7
USER_IN9
USER_IO8
USER_IO9
USER_IO10
USER_IO11
USER_IO12
USER_IO13
USER_INA
USER_INB
USER_IO16
USER_IO17
USER_IO18
USER_IO19
USER_IO20
USER_IO21
USER_IO22
USER_IO23
USER_IO24
USER_IO25
USER_IO26
USER_IO27
USER_IO28
SRAM_A10
SRAM_D7
SRAM_OE
USER_IN10
LEDR_HEARTB
LEDG_DONE
JTAG_DOUT
JTAG_TMS
JTAG_TCK
JTAG_DIN
SPI_CSO_B
JTAG_DOUT
LEDG_DONE
FDTI_WR
LEDR_HEARTB
SPI_MOSI
SPI_DIN
SPI_CSO_B
SPI_CLK
VCCSW
3V3X
3V3X
2V5 (VCCAUX)
1V2 (VCCINT)
3V3X
2V5
1V2
3V3X
3V3X
3V3X
3V3
2V5
2V5
2V5 3V3X
3V3x
3V3X
C14
0.01 uF
0603
C35
0.01uF
HB
RED
C42
0.1uF
0603
C20
0.1uF
0603
R33
4.7K
C28
0.01uF
C31
0.1uF
R9
4.7K
C37
0.01uF
R14
0
R26
360
C22
22 uF
TANT
C32
0.01uF
Q3
IRLML6401
C19
2.2 uF
0805
C15
2.2 uF
0603
R8
4.7K
C27
0.1uF
U6
TPS79333DBVRQ1/SOT23-5
1
2
3 4
5
IN
GND
EN BYPASS
OUT
C40
0.01uF
C23
4.7uF
0603
C41
0.01uF
C38
0.01uF
J2
Traditional JTAG
1
2
3
4
5
6
R21 4.7K
D?
GREEN
U4
M25P20
6
7
8
3
1
4
5
2C
HOLD
VCC
W
S
VSS
>Din
<Dout
C29
0.01uF
C30
0.1uF
J3
Xilinx Parallel Cable Header
1
2
3
4
5
6
C24
0.1uF
C44
0.1uF
R30
100 5%
D1
BAT54CT
T1
PROM TYPE SEL
1
2
3
C43
0.1uF
C13
0.1uF
R12
220K 5%
R11
4.7K
C21
0.01uF
U8
ST1S06PU12R DFN6
3
2 1
4
5
6
SW
GND FB
VIN_SW
VIN_A
NC
R29 4.7K
U7
TPS79325DBVR / SOT23-5
1
2
3 4
5
IN
GND
EN BYPASS
OUT
C36
0.1uF
R15
49.9K 1%
R31 330
C18
0.1uF
0603
C17
0.01 uF
0603
R10
4.7K
U5
XC3S250E-4TQ144
45
33
7
69
93
18
1
2
4
5
8
911
12
13
14
15
16
17
19
21
22
23
24
25
26
27
28
30
3
10
20
29
41
56
49
100 78
77
76
92
97
96
91
90
89
88
87
86
85
81
80
79
75
74
50
32
34
35
39
36
37
38
40
52
42
43
44
47
48
72
71
68
67
65
64
62
61
63
60
54
55
59
53
51
66
73
82
95
58
84
6
31
46
57
70
83
94
98
99
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VCCINT
IO_L09N_3
IO_L03P_3
IP
IO_L07P_1/A4/RHCLK6
IP
JTAG_PROG_B
IO_L01P_3
IO_L02P_3
IO_L02N_3/VREF_3
IO_L03N_3
VCCINT GND
IP/VREF_3
VCCO_3
IO_L04P_3/LHCLK0
IO_L04N_3/LHCLK1
IO_L05P_3/LHCLK2
IO_L05N_3/LHCLK3
GND
IO_L06n_3/LHCLK5
IO_L07P_3/LHCLK6
IO_L07N_3/LHCLK7
IP
IO_L08P_3
IO_L08N_3
GND
VCCO_3
VCCAUX
IO_L01N_3
IP ****
IO_L06P_3/LHCLK4
IP ****
IP
IP_L06P_2/RDWR_B/GCLK0
VCCO_2
VCCO_1 IP
IO_L02N_1/A13
IO_L02P_1/A14
IO_L06N_1/A5/RHCLK5
IO_L08N_1/A1
IO_L08P_1/A2
IO_L06P_1/A6/RHCLK4
GND
IP
IO_L05N_1/A7/RHCLK3
IO_L05P_1/A8/RHCLK2
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L03P_1/A12
VCCINT
VCCO_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L04P_2/D7/GCLK12
IO_L09P_3
IO_L10P_3
IO_L10N_3
IO_L01P_2/CSO_B
IP
GND
IP
IO_L01N_2/INIT_B
IO/D5
VCCO_2
IO_L02P_2/DOUT/BUSY
IO_L02N_2/MOSI/CSI_B
IP_L03P_2
IP_L03N_2/VREF_2
JTAG_DONE
IO_L10N_2/CCLK
IO_L09N_2/VS1/A18
IO_L09P_2/VS2/A19
VCCAUX
VCC0_2
IO_L08P_2/M0
GND
IO_L08N_2/DIN/D0
IO/M1
IO_L05N_2/D3/GCLK15
GND
IO_L07N_2/D1/GCLK3
IO_L05P_2/D4/GCLK14
IO_L04N_2/D6/GCLK13
IO/VREF_2 ****
GND
IO_L03N_1/A11
IP/VREF_1
IO_L07P_2/D2/GCLK2
IP
IP
IO/VREF_3 ****
GND
IP_L06N_2/M2/GCLK1
IO_L10P_2/VS0/A17
IO/VREF_1
IO_L07N_1/A3/RHCLK7
IO/A0
GND
IP
VCCAUX
IO_L09P_1/HDC
IO_L09N_1/LDC0
IO_L10P_1/LDC1
IO_L10N_1/LDC2
IP
JTAG_TMS
JTAG_TDO
JTAG_TCK
IP
IO_L01P_0
IO_L01N_0
IP
VCCINT
IO_L02P_0
IO_L02N_0
GND
IP_L03P_0
IP_L03N_0
VCCO_0
IO_L04P_0/GCLK4
IO_L04N_0/GCLK5
IO/VREF_0
IO_L05P_0/GCLK6
IO_L05N_0/GCLK7
GND
IP_L06P_0/GCLK8
IP_L06N_0/GCLK9
IO_L07P_0/GCLK10
IO_L07N_0/GCLK11
IO
GND
IO_L08P_0
IO_L08N_0/VREF_0
IP
VCCAUX
VCCO_0
IO_L09P_0
IO_L09N_0
IP
IO_L10P_0
IO_L10N_0/HSWAP
JTAG_TDI
L1
3.3uH
C45
0.1uF
JP1
PROG
1
2
U1
CY62128DV30LL-70ZI / TSOP32
9
21
22
23
25
10
7
1
3
4
12
31
20
19
18
17
16
15
14
13
2
11
24
26
27
28
29
32
5
30
8
6
NC
D0
D1
D2
D3
A16
A15
A11
A8
A13
A12
A10
A0
A1
A2
A3
A4
A5
A6
A7
A9
A14
GND
D4
D5
D6
D7
OE
WE
CE1
VCC
CE2
