DS07-13707-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90520A/520B Series
MB90522A/523A/522B/523B/F523B/V520A
■DESCRIPTION
The MB90520A/520B series is a general-purpose 16-bit microcontroller designed for process control applications
in consumer products that require high-speed real-time processing.
The microcontroller instruction set is based on the AT architecture of the F2MC* f amily with additional instructions
for high-level languages, ex tended addressing modes, enhanced multiplication and division instructions, and a
complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator f or processing long
word (32-bit) data.
The MB90520A/520B series per ipheral resources include an 8/10-bit A/D converter, 8-bit D/A converter, UART
(SCI) , e xtended I/O serial interf aces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and
1, a range of I/O timers (16-bit free-run timers 1 and 2, input capture (ICU) 0 and 1, and output compare (OCU)
0 and 1) , an LCD controller/driver, 8 external interrupt inputs, and 8 wakeup interrupts.
* : F2MC stands for FUJITSU Flexible MicroController, a registered trademark of FUJITSU LIMITED.
■FEATURES
•Clock
• Internal PLL clock multiplication circuit
• Selectable machine clock (PLL clock) : Base oscillation divided by two or multiplied by one to four
(For a 4 MHz base oscillation, the machine clock range is 4 MHz to 16 MHz) .
(Continued)
■PACKAGES
120-pin, Plastic, LQFP 120-pin, Plastic, QFP
(FPT-120P-M05) (FPT-120P-M13)
MB90520A/520B Series
2
(Continued)
• Sub-clock (32.768 KHz) operation available
Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = ×4, VCC = 5.0 V)
•16MB CPU memory space
Internal 24-bit addressing
•Instruction set optimized for controller applications
Rich data types (bit, byte, word, long-word)
Extended addressing modes (23 types)
Enhanced signed multiplication and division instructions and RETI instruction
Enhanced calculation precision using a 32-bit accumulator
•Instruction set designed for high-level language (C) and multi-tasking
System stack pointer
Enhanced pointer-indirect instructions and barrel shift instructions
•Faster execution speed
4-byte instruction queue
ROM mirror function (48 Kbytes of bank FF is mirrored in bank 00)
•Program patch function : An address match detection function (2 × addresses)
•Interrupt function
32 programmable interrupts with 8 levels
•Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS) : Up to 16 channels
•Low-power consumption (stand-by) modes
Sleep mode (CPU operating clock stops, peripherals continue to operate.)
Pseudo-clock mode (Only oscillation clock and timebase timer continue to operate.)
Clock mode (Main oscillation clock stops, sub-clock and clock timer continue to operate.)
Stop mode (Main oscillation and sub-clock both stop.)
CPU intermittent operation mode
Hardware stand-by mode (Change to stop mpde by operating hardware stand-by pins.)
•Process
CMOS technology
•I/O ports
General-purpose I/O ports (CMOS input/output) : 53 ports
General-purpose I/O ports (inputs with pull-up resistors) : 24 ports
General-purpose I/O ports (Nch open-drain outputs) : 8 ports
•Timers
Timebase timer, clock timer, watchdog timer : 1 channel each
8/16-bit PPG timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel
16-bit reload timers 0 and 1 : 2 channels
16-bit I/O timers :
16-bit free-run timers 0 and 1 : 2 channels
16-bit input capture 0 : 2 channels (2 channels per unit)
16-bit output compare 0 and 1 : 8 channels (4 channels per unit)
8/16-bit up/down counter/timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel
Clock output function : 1 channel
•Communications macro (communication interface)
Extended I/O serial interfaces 0 and 1 : 2 channels
UART (full-duplex, double-buffered, SCI : Can also be used for synchronous serial transfer) : 1 channel
MB90520A/520B Series
3
•External event interrupt control function
DTP/e xternal interrupts : 8 channels (Can be set to detect rising edges, falling edges, “H” le v els, or “L” le vels)
Wake-up interrupts : 8 channels (Detects “L” levels only)
Delayed interrupt generation module : 1 channel (for task switching)
•Analog/digital conversion
8/10-bit A/D converter : 8 channels (Can be initiated by an external trigger. Minimum conversion time = 10.2
µs for a 16 MHz machine clock)
8-bit D/A converter : 2 channels (R-2R type. Settling time = 12.5 µs for a 16 MHz machine clock)
•Displa y function
LCD controller/driver : 32 × segment drivers + 4 × common drivers
•Other
Supports serial writing to flash memory. (Only on versions with on-board flash memory.)
Note : The MB90520A and 520B series cannot be used in ex ternal bus mode. Alw ays set these de vices to single-
chip mode.
MB90520A/520B Series
4
■PRODUCT LINEUP
(Continued)
Parameter
Part
Number MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A
Classification Mask ROM Flash ROM Evaluation
product
ROM size 64 Kbytes 128 Kbytes 64 Kbytes 128 Kbytes 128 Kbytes
RAM size 4 Kbytes 6 Kbytes
Separate emulator
power supply*1 No
Process CMOS
Operating power
supply voltage*2 3.0 V to 5.5 V 2.7 V to 5.5 V 3.0 V to 5.5 V
Internal regulator circuit not mounted mounted
CPU functions
Number of instructions : 340
Instruction sizes : 8-bit, 16-bit
Instruction length : 1 byte to 7 bytes
Data sizes : 1-bit, 8-bit, 16-bit
Minimum instruction execution time : 62.5 ns (for a 16 MHz machine clock)
Interrupt processing time : 1.5 µs min. (for a 16 MHz machine clock)
Low power operation
(standby modes) Sleep mode, clock mode, pseudo-clock mode, stop mode, hardware standby mode,
and CPU intermittent operation mode
I/O ports
General-purpose I/O ports (CMOS outputs) : 53
General-purpose I/O ports (inputs with pull-up resistors) : 24
General-purpose I/O ports (Nch open drain outputs) : 8
Total : 85
Timebase timer 18-bit counter
Interrupt interval : 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(for a 4 MHz base oscillation)
Watchdog timer Reset trigger period
• For a 4 MHz base oscillation : 3.58, 14.33, 57.23, 458.75 ms
• For 32.768 sub-clock operation : 0.438, 3.500, 7.000, 14.000 s
16-bit
I/O
timers
16-bit
freerun
timer
Number of channels : 2
Generates an interrupt on overflow
16-bit
output
compare
Number of channels : 8
Pin change timing : Free run timer register value equals output compare register value.
16-bit
input
capture
Number of channels : 2
Saves the value of the freerun timer register when a pin input occurs (rising edge, falling
edge, either edge) .
16-bit reload timer Number of channels : 2
Count clock frequency : 0.125, 0.5, or 2.0 µs for a 16 MHz machine clock
Can be used to count an external event clock.
MB90520A/520B Series
5
(Continued)
*1 : As for the necessity of a DIP switch setting (S2) when using the emulation pod (MB2145-507) .
Refer to the hardware manual for the emulation pod (MB2145-507) fomr details.
*2 : Take note of the maximum operating frequency and A/D converter precision restrictions when operating at 3.0 V
to 3.6 V. See the “Electrical Characteristics” section for details.
Parameter
Part
Number MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A
Clock timer 15-bit timer
Interrupt interval : 0.438, 0.5, or 2.0 µs for sub-clock frequency = 32.768 kHz
8/16-bit PPG timer Number of channels : 1 (Can be used in 2 × 8-bit channel mode)
Can generate a pulse waveform output with specified period and 0 to 100% duty ratio.
8/16 -bit up/down
counter/timers
Number of channels : 1 (Can be used in 2 × 8-bit channel mode)
External event inputs : 6 channels
Reload/compare function : 8-bit × 2 channels
Clock monitor Clock output frequency : Machine clock/21 to machine clock/28
Delayed interrupt
generation module Interrupt generation module for task switching. (Used by REALOS.)
DTP/External
interrupts
Input channels : 8
Generates interrupts to the CPU on rising edges, falling edges with input “H” level, or “L”
level.
Can be used for external event interrupts and to activate EI2OS.
Wakeup interrupts Input channels : 8
Triggered by “L” level.
8/10-bit A/D converter
(successive
approximation type)
Number of channels : 8
Resolution : 8-bit or 10-bit selectable
Conversion can be performed sequentially for multiple consecutive channels.
• Single-shot conversion mode : Converts specified channel once only.
• Continuous conversion mode : Repeatedly converts specified channel.
• Intermittent conversion mode : Converts specified channel then halts temporarily.
8-bit D/A converter
(R-2R type) Number of channels : 2
Resolution : 8-bit
UART (SCI)
Number of channels : 1
Clock synchronous transfer : 62.5 Kbps to 1 Mbps
Clock asynchronous transfer : 1202 bps to 31250 bps
Supports bi-directional and master-slave communications.
Extended I/O serial
interface
Number of channels : 2
Clock synchronous transfer : 31.25 Kbps to 1 Mbps (Using internal shift clock)
Transmission format : Selectable LSB-first or MSB-first
LCD controller/driver
Number of common outputs : 4
Number of segment outputs : 32
Number of power supply pins for LCD drive : 4
LCD display memory : 16 bytes
Divider resistor for LCD drive : Internal
MB90520A/520B Series
6
■PACKAGES AND CORRESPONDING PRODUCTS
: Available, : Not available
Note : See the “■ PACKAGE DIMENSIONS” section for more details.
Package MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A
FPT-120P-M05
(LQFP)
FPT-120P-M13
(QFP)
PGA-256C-A01
(PGA)
×
×
×××××
×
MB90520A/520B Series
7
■PIN ASSIGNMENT
(TOP VIEW)
(FPT-120P-M05)
(FPT-120P-M13)
RST
MD0
MD1
MD2
HST
V3
V2
V1
V0
P97/SEG31
P96/SEG30
P95/SEG29
P94/SEG28
P93/SEG27
P92/SEG26
P91/SEG25
X0A
X1A
P90/SEG24
P87/SEG23
P86/SEG22
P85/SEG21
P84/SEG20
P83/SEG19
P82/SEG18
P81/SEG17
P80/SEG16
VSS
P77/COM3
P76/COM2
P31/CKOT
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
P36/PG00
P37/PG01
VCC
P40/PG10
P41/PG11
P42/SIN0
P43/SOT0
P44/SCK0
P45/SIN1
P46/SOT1
P47/SCK1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
PA0/SEG8
PA1/SEG9
PA2/SEG10
PA3/SEG11
PA4/SEG12
PA5/SEG13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P30
VSS
P27/ADTG
P26/ZIN0/INT7
P25/BIN0
P24/AIN0
P23/IC11
P22/IC10
P21/IC01
P20/IC00
P17/WI7
P16/WI6
P15/WI5
P14/WI4
P13/WI3
P12/WI2
P11/WI1
P10/WI0
P07
P06/INT6
P05/INT5
P04/INT4
P03/INT3
P02/INT2
P01/INT1
P00/INT0
VCC
X1
X0
VSS
PA6/SEG14
PA7/SEG15
VSS
C
P50/SIN2/AIN1
P51/SOT2/BIN1
P52/SCK2/ZIN1
DVCC
DVSS
P53/DA0
P54/DA1
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VCC
P70/TI0/OUT4
P71/TO0/OUT5
P72/TI1/OUT6
P73/TO1/OUT7
P74/COM0
P75/COM1
MB90520A/520B Series
8
■PIN DESCRIPTIONS
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
Pin No. Pin Name Circuit
Type Function
LQFP-120*1
QFP-120*2
92, 93 X0, X1 A Oscillator pin
74, 73 X0A, X1A B Sub-oscillator pin
89 to 87 MD0 to
MD2 CInput pins for setting the operation mode.
Connect directly to VCC or VSS.
90 RST C External reset input pin
86 HST C Hardware standby input pin
95 to 101
P00 to
P06 D
General-purpose I/O ports
The settings in the pull-up resistor setup register (RDR0) are enabled
when ports are set as inputs.
The RDR0 settings are ignored when ports are set as outputs.
INT0 to
INT6 Event input pins for ch.0 to ch.6 of the DTP/external interrupt circuit
102 P07 D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR0) are enabled when
ports are set as inputs.
The RDR0 settings are ignored when ports are set as outputs.
103 to 110
P10 to
P17 D
General-purpose I/O ports
The settings in the pull-up resistor setup register (RDR1) are enabled when
ports are set as inputs.
The RDR1 settings are ignored when ports are set as outputs.
WI0 to
WI7 Event input pins for the wakeup interrupts.
111, 112,
113, 114
P20, P21,
P22, P23
E
General-purpose I/O ports
IC00, IC01,
IC10, IC11
Trigger input pins for input capture units (ICU) 0 and 1.
Input operates continuously when channels 0 and 1 of input capture units
(ICU) 0 and 1 are operating. Accordingly, output to the pins from other func-
tions that share this pin must be suspended unless performed intentionally.
115 P24 EGeneral-purpose I/O port
AIN0 Also can be used as the count clock A input to 8/16-bit up/down counter/
timer 0.
116 P25 EGeneral-purpose I/O port
BIN0 Also can be used as the count clock B input to 8/16-bit up/down counter/
timer 0.
117
P26
E
General-purpose I/O port
ZIN0 Also can be used as the control clock Z input to 8/16-bit up/down counter/
timer 0.
INT7 Event input pin for ch.7 of the DTP/external interrupt circuit
MB90520A/520B Series
9
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
Pin No. Pin Name Circuit
Type Function
LQFP-120*1
QFP-120*2
118
P27
E
General-purpose I/O port
ADTG
External trigger input to the 8/10-bit A/D converter
Input operates continuously when the 8/10-bit A/D converter is performing
input. Accordingly, output to the pin from other functions that share this
pin must be suspended unless performed intentionally.
120 P30 E General-purpose I/O port
1P31 EGeneral-purpose I/O port
CKOT Output pin for clock monitor function
The clock monitor is output when clock monitor output is enabled.
2P32 E
General-purpose I/O port
Only available when waveform output from output compare 0 is disabled.
OUT0 Event output pin for ch.0 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
3P33 E
General-purpose I/O port
Only available when waveform output from output compare 1 is disabled.
OUT1 Event output pin for ch.1 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
4P34 E
General-purpose I/O port
Only available when waveform output from output compare 2 is disabled.
OUT2 Event output pin for ch.2 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
5P35 E
General-purpose I/O port
Only available when waveform output from output compare 3 is disabled.
OUT3 Event output pin for ch.3 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
6P36 E
General-purpose I/O port
Only available when waveform output from PG00 is disabled.
PG00 Output pin for 8/16-bit PPG timer 0
Only available when waveform output is enabled for PG00.
7P37 E
General-purpose I/O port
Only available when waveform output from PG01 is disabled.
PG01 Output pin for 8/16-bit PPG timer 0
Only available when waveform output is enabled for PG01.
MB90520A/520B Series
10
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
Pin No. Pin Name Circuit
Type Function
LQFP-120*1
QFP-120*2
9, 10 P40, P41 D
General-purpose I/O ports
Only available when waveform outputs from PG10 and PG11 are disabled.
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
PG10,
PG11 Output pins for 8/16-bit PPG timer 1
Only available when waveform output is enabled for PG10 and PG11.
11
P42
D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
SIN0
UART (SCI) serial data input pin
Input operates continuously when the UART is performing input.
Accordingly, output to the pin from other functions that share this pin must
be suspended unless performed intentionally.
12 P43 D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
SOT0 UART (SCI) serial data output pin
Only available when serial data output is enabled for the UART (SCI) .
13 P44 D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
SCK0 UART (SCI) serial clock input/output pin
Only available when serial clock output is enabled for the UART (SCI) .
14
P45
D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports set as inputs. The RDR4 settings are ignored when ports set
are as outputs.
SIN1
Data input pin for extended I/O serial interface 1
Input operates continuously when the performing serial input. Accordingly,
output to the pin from other functions that share this pin must be
suspended unless performed intentionally.
15 P46 D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports set as inputs. The RDR4 settings are ignored when ports are
set as outputs.
SOT1 Data output pin for extended I/O serial interface 1
Only available when serial data output is enabled for SOT1.
MB90520A/520B Series
11
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
Pin No. Pin Name Circuit
Type Function
LQFP-120*1
QFP-120*2
16 P47 D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
SCK1 Serial clock input/output pin for extended I/O serial interface 1
Only available when serial clock output is enabled for SCK1.
35
P50
E
General-purpose I/O port
SIN2
Data input pin for extended I/O serial interface 2
Input operates continuously when the performing serial input.
Accordingly, output to the pin from other functions that share this pin must
be suspended unless performed intentionally.
AIN1 Also can be used as the count clock A input to 8/16-bit up/down counter/
timer 1.
36
P51
E
General-purpose I/O port
SOT2 Data output pin for extended I/O serial interface 2
Only available when serial data output is enabled for SOT2.
BIN1 Also can be used as the count clock B input to 8/16-bit up/down counter/
timer 1.
37
P52
E
General-purpose I/O port
SCK2 Serial clock input/output pin for extended I/O serial interface 2
Only available when serial clock output is enabled for SCK2.
ZIN1 Also can be used as the control clock Z input to 8/16-bit up/down counter/
timer 1.
40, 41 P53, P54 IGeneral-purpose I/O ports
DA0, DA1 Analog output pins for ch.0 and ch.1 of the 8-bit D/A converter
46 to 53
P60 to P67
K
General-purpose I/O ports
Port input is enabled when the analog input enable register (ADER) is set
to the ports.
AN0 to
AN7
Analog inputs for the 8/10-bit A/D converter
Analog input is enabled when the analog input enable register (ADER) is
set.
55, 57
P70, P72
E
General-purpose I/O ports
TI0, TI1
Event input pins for 16-bit reload timers 0 and 1
Input operates continuously when 16-bit reload timers 0 and 1 input an
external clock. Accordingly, output to these pins from other functions that
share the pins must be suspended unless performed intentionally.
OUT4,
OUT6 Event output pins for ch. 4 and ch. 6 of output compare unit 1 (OCU)
Only available when event output from output compare 1 is enabled.
MB90520A/520B Series
12
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
Pin No. Pin Name Circuit
Type Function
LQFP-120*1
QFP-120*2
56, 58
P71, P73
E
General-purpose I/O ports
Only available when event outputs from 16-bit reload timers 0 and 1 are
disabled.
TO0, TO1 Output pins for 16-bit reload timers 0 and 1.
Only available when output is enabled for 16-bit reload timers 0 and 1.
OUT5,
OUT7 Event output pins for ch. 5 and ch. 7 of output compare unit 1 (OCU)
Only available when event output from output compare 1 is enabled.
59 to 62
P74 to P77
L
General-purpose I/O ports
Only available when the LCD controller/driver control register is set to the
ports.
COM0 to
COM3
Common pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
common outputs.
64 to 71
P80 to P87
L
General-purpose I/O ports
Only available when the LCD controller/driver control register is set to the
ports.
SEG16 to
SEG23
LCD segment output pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
segment outputs.
72,
75 to 81
P90,
P91 to P97 M
General-purpose I/O ports (Support up to IOL = 10 mA)
Only available when the LCD controller/driver control register is set to the
ports.
SEG24,
SEG25 to
SEG31
LCD segment output pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
segment outputs.
17 to 24 SEG0 to
SEG7 F LCD segment 00 to 07 pins for the LCD controller/driver
25 to 32
PA0 to PA7
L
General-purpose I/O ports
Only available when the LCD controller/driver control register is set up to
the ports.
SEG8 to
SEG15
LCD segment 08 to 15 pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
segment outputs.
MB90520A/520B Series
13
(Continued)
*1 : FPT-120P-M05
*2 : FPT-120P-M13
Pin No. Pin Name Circuit
Type Function
LQFP-120*1
QFP-120*2
34 C G Capacitor connection pin for stabilizing power supply
Connect an external ceramic capacitor of approximately 0.1 µF. If operat-
ing at 3.3 V or lower, connect to VCC.
82 to 85 V0 to V3 N Power supply input pins for the LCD controller/driver
8, 54, 94 VCC Power
supply Power supply input pins for the digital circuit
33, 63, 91, 119 VSS Power
supply GND level power supply input pins for the digital circuit
42 AVCC HPower supply input for the analog circuit
Ensure that a voltage greater than AVCC is applied to VCC before turning
the analog power supply on or off.
43 AVRH J “H” reference voltage for the A/D converter
Ensure that a voltage greater than AVRH is applied to AVCC before turning
the power supply to this pin on or off.
44 AVRL H “L” reference voltage for the A/D converter
45 AVSS H GND level power supply input pin for the analog circuit
38 DVCC H“H” reference voltage for the D/A converter
Ensure that this voltage does not exceed VCC.
39 DVSS H“L” reference voltage for the D/A converter
Apply the same voltage level as VSS.
MB90520A/520B Series
14
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
• High-speed oscillation feedback
resistor
Approx. 1 MΩ
B
• Low-speed oscillation feedback
resistor
Approx. 10 MΩ
C
• Hysteresis input
D
• Selectable pull-up option
• CMOS hysteresis input
• CMOS level output
• With standby control
E
• CMOS hysteresis input
• CMOS level output
• With standby control
X0
X1 Nch
Nch
Pch Clock input
Standby control signal
Pch
X0A
X1A Nch Clock input
Standby control signal
Nch
Pch
Pch
RHysteresis input
R
IOL = 4 mA
Pch
Pull-up connect/
disconnect selection
signal
Pch
Nch
VCC
Digital output
Digital output
Hysteresis input
Standby control
VSS
IOL = 4 mA
Digital output
Digital output
Hysteresis input
Standby control
VCC
VSS
R
Nch
Pch
MB90520A/520B Series
15
(Continued)
Type Circuit Remarks
F
• Segment output pins
G
• Capacitor connection pin
(This is an N.C. pin on the
MB90522A and MB90523A.)
H
• Analog power supply input
protection circuit
I
• CMOS hysteresis input
• CMOS level output
(CMOS output is not available when
analog output is operating.)
• Also used as analog output
(Analog output has priority)
• With standby control
J
• A/D converter ref+ power supply
input pin
(Incorporates power supply
protection circuit.)
R
Nch
VCC
VSS
Pch
Nch
VCC
VSS
AVP
Pch
Nch
VCC
VSS
R
IOL = 4 mA
Digital output
Digital output
Hysteresis input
Standby control
Analog output
VCC
VSS
Nch
Pch
ANE
AVP
ANE
VCC
VSS
Pch Pch
Nch Nch
MB90520A/520B Series
16
(Continued)
Type Circuit Remarks
K
• CMOS hysteresis input
• CMOS level output
• Also used as analog input.
• With standby control
L
• CMOS hysteresis input
• CMOS level output
• Also used as segment output pin.
• With standby control
(only available when segment
output is not operating.)
M
• CMOS hysteresis input
• N-ch open-drain output
• Also used as segment output pin.
• With standby control
(only available when segment
output is not operaing.)
N
• Reference voltage pin for LCD
controller
R
Pch
Nch
VCC
VSS
IOL = 4 mA
Digital output
Digital output
Hysteresis input
Standby control
Analog input
IOL = 4 mA
Digital output
Digital output
Hysteresis input
Standby control
Segment output/common output
R
VCC
Pch
Nch
VSS
IOL = 10 mA
Open drain
Hysteresis input
Standby control
Segment output
R
VCC
Nch
Pch
VSS
R
IOL = 10 mA
Nch
Pch VCC
VSS
MB90520A/520B Series
17
■HANDLING DEVICES
Take note of the following points when handling devices :
• Do not exceed maximum rated voltage (to prevent latch-up)
• Supply voltage stability
• Power-on precautions
• Power supply pins
• Crystal oscillator circuit
• Notes on using an external clock
• Precautions when not using sub-clock mode
• Treatment of unused pins
• Treatment of N.C. pins
• Treatment of pins when A/D converter is not used
• Sequence for connecting and disconnecting the A/D converter power supply and analog input pins
• Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins
• Conditions when output from ports 0 and 1 is undefined
• Initialization
• Notes on using the DIV A, Ri and DIVW A, RWi instructions
• Notes on using REALOS
Device Handling Precautions
•Do not exceed maximum rated voltage (to prevent latch-up)
Latch-up occurs in CMOS ICs if a v oltage greater than VCC or less than VSS is applied to an input or output pin
(other than a high or medium withstand voltage pin) or if the voltage applied between VCC and VSS exceeds
the rating. If latch-up occurs, the po wer supply current increases rapidly resulting in thermal damage to circuit
elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation.
Similarly, when tur ning the analog power supply on or off, ensure the analog power supply voltages (AVCC,
AVRH, DVCC) and analog input voltages do not exceed the digital voltage (VCC) .
Also ensure that the voltages applied to the LCD power supply pins (V3 to V0) do not e xceed the power supply
voltage (VCC) .
•Supply voltage stability
Rapid changes in supply voltage may cause the device to misoperate, even if the voltage remains within the
allowed operating range. Accordingly, ensure that the VCC supply is stable.
The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the mains supply
frequency (50 to 60 Hz) of 10% or less of VCC and a transient voltage change rate of 0.1 V/ms or less when
turning the power supply on or off.
•Power-on precautions
To prevent misoperation of the internal regulator circuit at pow er-on, ensure that the power supply rising time
(0.2 V to 2.7 V) is at least 50 µs.
•Power supply pins
When multiple VCC and VSS pins are provided, connect all VCC and VSS pins to power supply or ground externally .
Although pins at the same potential are connected together in the internal device design so as to prevent
misoperation such as latch-up, connecting all VCC and VSS pins appropriately minimizes unwanted radiation,
prevents misoperation of strobe signals due to increases in the ground level, and keeps the overall output
current rating.
Also, ensure that the impedance of the VCC and VSS connections to the power supply are as low as possible.
MB90520A/520B Series
18
Connection of a bypass capacitor of approximately 0.1 µF between VCC and VSS is recommended to prevent
power supply noise. Connect the capacitor close to the VCC and VSS pins.
•Crystal oscillator circuit
Noise on the X0 and X1 pins can be a cause of device misoperation. Place the X0 and X1 pins, crystal oscillator
(or ceramic oscillator) , and b ypass capacitor to ground as close together as possib le . Also, design the circuit
board so that the X0 and X1 pin wiring does not cross other wiring.
Surrounding the X0/X1 and X0A/X1A pins with ground in the printed circuit board design is recommended to
ensure stable operation.
•Notes on using an external clock
When using an external clock, drive the X0 pin only and leave the X1 pin open.
The figure below shows an example of how to use an external clock.
•Precautions when not using sub-clock mode
Connect an oscillator to X0A and X1A, even if not using sub-clock mode.
•Treatment of unused pins
Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to
latchup. Always pull-up or pull-down unused pins using a 2 kΩ or larger resistor.
If some I/O pins are unused, either set as outputs and lea ve open circuit or set as inputs and treat in the same
way as input pins.
•Treatment of N.C. pins
Always leave N.C. (non connect) pins open circuit.
•Treatment of pins when A/D converter not used
When not using the A/D converter and D/A conv erter, always connect AVCC = DVCC = AVRH = VCC and AVSS =
AVRL = VSS.
•Sequence for connecting and disconnecting the A/D converter power supply and analog input pins
Do not apply voltage to the A/D and D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) or analog
inputs (AN0 to AN7) until the digital power supply (VCC) is turned on.
When turning the device off, turn off the digital power supply after disconnecting the A/D converter power
supply and analog inputs. When turning the power on or off, ensure that AVRH and DVCC do not exceed AVCC
(turning the analog and digital power supplies on and off simultaneously is OK) .
•Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins
The SEG08 to SEG31 and COM0 to COM3 pins are shared with general-purpose I/O por ts. The electrical
ratings f or SEG08 to SEG23 and COM0 to COM3 are the same as for CMOS outputs and the electrical ratings
for SEG24 to SEG31 are the same as for N-ch open-drain ports.
X0
Open circuit MB90520A/520B series
X1
Example of how to use an external clock
MB90520A/520B Series
19
•Conditions when output from ports 0 and 1 is undefined
After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabili-
zation delay time controlled by the regulator circuit (during the power-on reset) . The figure below shows the
timing.
Note that this undefined output period does not occur on products without an internal regulator circuit as these
products do not have an oscillation stabilization delay time.
Note : See the “■ PRODUCT LINEUP” section for details of which MB90520A/520B series products have an internal
regulator circuit.
•Initialization
The de vice contains internal registers that are only initialized b y a power-on reset. To initialize these registers,
restart the power supply.
•Notes on using the DIV A, Ri and DIVW A, RWi instructions
Set the corresponding bank registers (DTB, ADB, USB, SSB) to “00H” when using the signed division instruc-
tions “DIV A, Ri” and “DIVW A, RWi”.
If the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder value
produced by the instruction is not stored in the instruction operand register.
•Notes on using REALOS
The extended intelligent I/O service (EI2OS) cannot be used when using REALOS.
Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be w orking with the self-oscillating circuit e ven
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
VCC (Power supply pin)
PONR (Power-on reset) signal
RST (External asynchronous reset) signal
RST (Internal reset) signal
Oscillation clock signal
KA (Internal operating clock A) signal
KB (Internal operating clock B) signal
PORT (port output) signal
Oscillation stabilization delay time*2
Undefined output time
Regulator circuit stabilization
delay time*1
*1 : Regulator circuit oscillation stabilization delay time : 217/Oscillation clock frequency
(approx. 8.19 ms for a 16 MHz oscillation clock frequency)
*2 : Oscillation stabilization delay time : 218/Oscillation clock frequency
(approx. 16.38 ms for a 16 MHz oscillation clock frequency)
Timing chart for undefined output from ports 0 and 1
MB90520A/520B Series
20
• BLOCK DIAGRAM
F2MC-16LX
CPU
X0, X1
X0A, X1A
RST
HST
P00/INT0 to P06/INT6
P10/WI0 to P17/WI7
P60/AN0 to P67/AN7
SEG00 to SEG07
V0 to V3
P74/COM0 to P77/COM3
P70/TI0/OUT4
P71/TO0/OUT5
P72/TI1/OUT6
P73/TO1/OUT7
P20/IC00
P21/IC01
P22/IC10
P23/IC11
P24/AIN0
P25/BIN0
P26/ZIN0/INT7
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
P42/SIN0
P43/SOT0
P44/SCK0
P31/CKOT
P30
P37/PG01
P36/PG00
P41/PG11
P40/PG10
77
3
8
4
4
P80/SEG16 to P87/SEG23
8
24 P90/SEG24 to P97/SEG31
8
PA0/SEG08 to PA7/SEG15
8
4
AVCC
AVSS
DVCC
DVSS
AVRH
AVRL
P07
P45/SIN1
P46/SOT1
P47/SCK1
P27/ADTG
P50/SIN2/AIN1
P51/SOT2/BIN1
P52/SCK2/ZIN1
P53/DA0
P54/DA1
2
4
2
2
8
8
88
SIO ch.1
UART
(SCI)
Wakeup
interrupts
SIO ch.2
8-bit
D/A
converter
× 2 ch
RAM
ROM
4
2
Main clock
DTP/
external
interrupt
circuit
LCD
controller/
driver
8/16-bit
up/down
counter/
timer 0, 1
Port 0*2
Ports 8, 9*3, A
Port 4*2
Port 1*2
Port 2
Port 7
Port 6
Port 2
Port 5
Interrupt controller
8/10-bit
A/D
converter
Port 3
Clock controller*1
(Includes
timebase timer)
Sub-clock
16-bit
I/O timer 1
Input
capture 0
(ICU)
16-bit
reload
timer 0
Output
compare 1
(OCU)
16-bit
freerun
timer 1
16-bit
reload
timer 1
16-bit
I/O timer 2
16-bit
freerun
timer 0
Output
compare 0
(OCU)
8/16-bit
PPG
timer 0, 1
Clock
output
Other pins
MD0 to MD2, C,
VCC, VSS
Internal data bus
*1 : The clock control circuit includes the watchdog timer and timebase timer low power consumption control
circuits.
*2 : Incorporates a pull-up register setting register. CMOS level input and output.
*3 : As this port shares pins with the LCD output, the port uses N-ch open-drain circuits.
MB90520A/520B Series
21
■MEMORY MAP
Note : The upper part of 00 bank contains a mirror of the ROM data in FF bank. This is called the mirror ROM
function and enables use of the C compiler’s small memory model. As the lower 16 bits of the FF bank and
00 bank addresses are the same, tables located in ROM can be ref erenced without needing to declare far
pointers.
F or e xample, accessing 00C000H actually accesses the contents of R OM at FFC000H. Note that, as the FF
bank R OM area e xceeds 48 KBytes, the entire ROM image cannot be mirrored in 00 bank. Accordingly, as
ROM data from FF4000 H to FFFFFFH is mirrored in 004000H to 00FFFFH, alwa ys locate ROM data tab les in
the range FF4000H to FFFFFFH.
FFFFFFH
Address #1
Address #2
Address #3
FE0000H
010000H
004000H
002000H
000100H
0000C0H
000000H
Single chip mode with mirror function
ROM area
ROM area
(image of
FF bank)
RAM
Peripherals
Registers
: Internal memory access
* : The values of addresses #1, #2, and #3 vary by product.
: Access prohibited
Part No. Address #1*Address #2*Address #3*
MB90522A/B FF0000H004000H001100H
MB90523A/B FE0000H004000H001100H
MB90F523B FE0000H004000H001100H
MB90V520A 001900H
MB90520A/520B Series
22
■I/O MAP
(Continued)
Address Abbreviated
Register
Name Register Name Peripheral Name Initial Value
000000HPDR0 Port 0 data register Port 0 XXXXXXXXB
000001HPDR1 Port 1 data register Port 1 XXXXXXXXB
000002HPDR2 Port 2 data register Port 2 XXXXXXXXB
000003HPDR3 Port 3 data register Port 3 XXXXXXXXB
000004HPDR4 Port 4 data register Port 4 XXXXXXXXB
000005HPDR5 Port 5 data register Port 5 XXXXXXXXB
000006HPDR6 Port 6 data register Port 6 XXXXXXXXB
000007HPDR7 Port 7 data register Port 7 XXXXXXXXB
000008HPDR8 Port 8 data register Port 8 XXXXXXXXB
000009HPDR9 Port 9 data register Port 9 XXXXXXXXB
00000AHPDRA Port A data register Port A XXXXXXXXB
00000BHLCDCMR Port 7/COM pin selection register Port 7,
LCD controller/driver XXXX 0 0 0 0B
00000CHOCP4 OCU compare register ch.4 16-bit I/O timer XXXXXXXXB
00000DHXXXXXXXXB
00000EH (Access prohibited)
00000FHEIFR Wakeup interrupt flag register Wakeup interrupts XXXXXXX0B
000010HDDR0 Port 0 direction register Port 0 0 0 0 0 0 0 0 0B
000011HDDR1 Port 1 direction register Port 1 0 0 0 0 0 0 0 0B
000012HDDR2 Port 2 direction register Port 2 0 0 0 0 0 0 0 0B
000013HDDR3 Port 3 direction register Port 3 0 0 0 0 0 0 0 0B
000014HDDR4 Port 4 direction register Port 4 0 0 0 0 0 0 0 0B
000015HDDR5 Port 5 direction register Port 5 XXX 0 0 0 0 0B
000016HDDR6 Port 6 direction register Port 6 0 0 0 0 0 0 0 0B
000017HDDR7 Port 7 direction register Port 7 0 0 0 0 0 0 0 0B
000018HDDR8 Port 8 direction register Port 8 0 0 0 0 0 0 0 0B
000019HDDR9 Port 9 direction register Port 9 0 0 0 0 0 0 0 0B
00001AHDDRA Port A direction register Port A 0 0 0 0 0 0 0 0B
00001BHADER Analog input enable register Port 6, A/D converter 1 1 1 1 1 1 1 1B
00001CHOCP5 OCU compare register ch.5 16-bit I/O timer XXXXXXXXB
00001DHXXXXXXXXB
00001EH (Access prohibited)
00001FHEICR Wakeup interrupt enable register Wakeup interrupts 0 0 0 0 0 0 0 0B
MB90520A/520B Series
23
(Continued)
Address Abbreviated
Register
Name Register Name Peripheral Name Initial Value
000020HSMR Serial mode register
UART
(SCI)
0 0 0 0 0 0 0 0B
000021HSCR Serial control register 0 0 0 0 0 1 0 0B
000022HSIDR/
SODR Serial input data register/
Serial output data register XXXXXXXXB
000023HSSR Serial status register 0 0 0 0 1 X 0 0B
000024HSMCS1 Serial mode control status register 1 Extended I/O serial
interface 1
XXXX 0 0 0 0B
000025H0 0 0 0 0 0 1 0B
000026HSDR1 Serial data register 1 XXXXXXXXB
000027HCDCR Communication prescaler control
register Communication prescaler
register 0 XXX 1 1 1 1B
000028HSMCS2 Serial mode control status register 2 Extended I/O serial
interface 2
XXXX 0 0 0 0B
000029H0 0 0 0 0 0 1 0B
00002AHSDR2 Serial data register 2 XXXXXXXXB
00002BH (Access prohibited)
00002CHOCS45 OCU control status register ch.45
16-bit I/O timer
0 0 0 0 XX 0 0B
00002DHXXX 0 0 0 0 0B
00002EHOCS67 OCU control status register ch.67 0 0 0 0 XX 0 0B
00002FHXXX 0 0 0 0 0B
000030HENIR DTP/interrupt enable register
DTP /external interrupt
circuit
0 0 0 0 0 0 0 0B
000031HEIRR DTP/interrupt request register XXXXXXXXB
000032HELVR Request level setting register 0 0 0 0 0 0 0 0B
000033H0 0 0 0 0 0 0 0B
000034HOCP6 OCU compare register ch.6 16-bit I/O timer XXXXXXXXB
000035HXXXXXXXXB
000036HADCS A/D control status register
8/10-bit A/D converter
0 0 0 0 0 0 0 0B
000037H0 0 0 0 0 0 0 0B
000038HADCR A/D data register XXXXXXXXB
000039H0 0 0 0 1 XXXB
00003AHDADR0 D/A converter data register ch.0
8-bit D/A converter
XXXXXXXXB
00003BHDADR1 D/A converter data register ch.1 XXXXXXXXB
00003CHDACR0 D/A control register 0 XXXXXXX 0B
00003DHDACR1 D/A control register 1 XXXXXXX 0B
00003EHCLKR Clock output enable register Clock monitor function XXXX 0 0 0 0B
MB90520A/520B Series
24
(Continued)
Address Abbreviated
Register
Name Register Name Peripheral Name Initial Value
00003FH (Access prohibited)
000040HPRLL0 PPG0 reload register L
8/16-bit PPG timer 0, 1
XXXXXXXXB
000041HPRLH0 PPG0 reload register H XXXXXXXXB
000042HPRLL1 PPG1 reload register L XXXXXXXXB
000043HPRLH1 PPG1 reload register H XXXXXXXXB
000044HPPGC0 PPG0 operation mode control register 0 X 0 0 0 XX 1B
000045HPPGC1 PPG1 operation mode control register 0 X 0 0 0 0 0 1B
000046HPPGOE PPG0, 1 output control register 0 0 0 0 0 0 0 0B
000047H (Access prohibited)
000048HTMCSR0 Timer control status register ch.0
16-bit reload timer 0
0 0 0 0 0 0 0 0B
000049HXXXX 0 0 0 0B
00004AHTMR0/
TMRLR0 16-bit timer register ch.0/
16-bit reload register ch.0 XXXXXXXXB
00004BHXXXXXXXXB
00004CHTMCSR1 Timer control status register ch.1
16-bit reload timer 1
0 0 0 0 0 0 0 0B
00004DHXXXX 0 0 0 0B
00004EHTMR1/
TMRLR1 16-bit timer register ch.1/
16-bit reload register ch.1 XXXXXXXXB
00004FHXXXXXXXXB
000050HIPCP0 ICU data register ch.0
16-bit I/O timer
XXXXXXXXB
000051HXXXXXXXXB
000052HIPCP1 ICU data register ch.1 XXXXXXXXB
000053HXXXXXXXXB
000054HICS01 ICU control status register 0 0 0 0 0 0 0 0B
000055H (Access prohibited)
000056HTCDT0 Freerun timer data register 0 16-bit I/O timer
0 0 0 0 0 0 0 0B
000057H0 0 0 0 0 0 0 0B
000058HTCCS0 Freerun timer control status register 0 0 0 0 0 0 0 0 0B
000059H (Access prohibited)
00005AHOCP0 OCU compare register ch.0
16-bit I/O timer
XXXXXXXXB
00005BHXXXXXXXXB
00005CHOCP1 OCU compare register ch.1 XXXXXXXXB
00005DHXXXXXXXXB
00005EHOCP2 OCU compare register ch.2 XXXXXXXXB
00005FHXXXXXXXXB
MB90520A/520B Series
25
(Continued)
Address Abbreviated
Register
Name Register Name Peripheral Name Initial Value
000060HOCP3 OCU compare register ch.3
16-bit I/O timer
XXXXXXXXB
000061HXXXXXXXXB
000062HOCS01 OCU control status register ch.0, ch.1 0 0 0 0 XX 0 0B
000063HXXX 0 0 0 0 0B
000064HOCS23 OCU control status register ch.2, ch.3 0 0 0 0 XX 0 0B
000065HXXX 0 0 0 0 0B
000066HTCDT1 Freerun timer data register 1 16-bit I/O timer
0 0 0 0 0 0 0 0B
000067H0 0 0 0 0 0 0 0B
000068HTCCS1 Freerun timer control status register 1 0 0 0 0 0 0 0 0B
000069H (Access prohibited)
00006AHLCR0 LCDC control register 0 LCD controller/driver 0 0 0 1 0 0 0 0B
00006BHLCR1 LCDC control register 1 0 0 0 0 0 0 0 0B
00006CHOCP7 OCU compare register ch.7 16-bit I/O timer XXXXXXXXB
00006DHXXXXXXXXB
00006EH (Access prohibited)
00006FHROMM ROM mirror function selection register ROM mirror function
selection module XXXXXXX1B
000070H
to
00007FHVRAM Data memory for LCD display LCD controller/driver XXXXXXXXB
000080HUDCR0 Up/down count register 0
8/16-bit up/down
counter/timer 0, 1
0 0 0 0 0 0 0 0B
000081HUDCR1 Up/down count register 1 0 0 0 0 0 0 0 0B
000082HRCR0 Reload compare register 0 0 0 0 0 0 0 0 0B
000083HRCR1 Reload compare register 1 0 0 0 0 0 0 0 0B
000084HCSR0 Counter status register 0 0 0 0 0 0 0 0 0B
000085H (Reserved) *3
000086HCCR0 Counter control register 0 8/16-bit up/down
counter/timer 0, 1
X 0 0 0 0 0 0 0B
000087H0 0 0 0 0 0 0 0B
000088HCSR1 Counter status register 1 0 0 0 0 0 0 0 0B
000089H (Reserved) *3
00008AHCCR1 Counter control register 1 8/16-bit up/down
counter/timer 0, 1 X 0 0 0 0 0 0 0B
00008BHX 0 0 0 0 0 0 0B
00008CHRDR0 Port 0
input pull-up resistor setup register Port 0 0 0 0 0 0 0 0 0B
00008DHRDR1 Port 1
input pull-up resistor setup register Port 1 0 0 0 0 0 0 0 0B
MB90520A/520B Series
26
(Continued)
Address Abbreviated
Register
Name Register Name Peripheral Name Initial Value
00008EHRDR4 Port 4
input pull-up resistor setup register Port 4 0 0 0 0 0 0 0 0B
00008FH
to
00009DH
(Access prohibited)
(Area reserved for system use) *4
00009EHPACSR Address detection control register Address match detection
function 0 0 0 0 0 0 0 0B
00009FHDIRR Delayed interrupt request output/clear
register Delayed interrupt
generation module XXXXXXX 0B
0000A0HLPMCR Low power consumption mode control
register Low power consumption
(standby) mode 0 0 0 1 1 0 0 0B
0000A1HCKSCR Clock selection register 1 1 1 1 1 1 0 0B
0000A2H
to
0000A7H (Access prohibited)
0000A8HWDTC Watchdog timer control register Watchdog timer XXXXXXXXB
0000A9HTBTC Timebase timer control register Timebase timer 1 XX 0 0 0 0 0B
0000AAHWTC Clock timer control register Clock timer 1 X 0 0 1 0 0 0B
0000ABH
to
0000ADH (Access prohibited)
0000AEHFMCS Flash memory control status register 1 Mbit flash memory 0 0 0 X 0 0 0 0B
0000AFH (Access prohibited)
0000B0HICR00 Interrupt control register 00
Interrupt controller
0 0 0 0 0 1 1 1B
0000B1HICR01 Interrupt control register 01 0 0 0 0 0 1 1 1B
0000B2HICR02 Interrupt control register 02 0 0 0 0 0 1 1 1B
0000B3HICR03 Interrupt control register 03 0 0 0 0 0 1 1 1B
0000B4HICR04 Interrupt control register 04 0 0 0 0 0 1 1 1B
0000B5HICR05 Interrupt control register 05 0 0 0 0 0 1 1 1B
0000B6HICR06 Interrupt control register 06 0 0 0 0 0 1 1 1B
0000B7HICR07 Interrupt control register 07 0 0 0 0 0 1 1 1B
0000B8HICR08 Interrupt control register 08 0 0 0 0 0 1 1 1B
0000B9HICR09 Interrupt control register 09 0 0 0 0 0 1 1 1B
0000BAHICR10 Interrupt control register 10 0 0 0 0 0 1 1 1B
0000BBHICR11 Interrupt control register 11 0 0 0 0 0 1 1 1B
0000BCHICR12 Interrupt control register 12 0 0 0 0 0 1 1 1B
0000BDHICR13 Interrupt control register 13 0 0 0 0 0 1 1 1B
MB90520A/520B Series
27
(Continued)
Initial value notation
*1 : Access is prohibited to the address range 0000C0H to 0000FFH. See the “■ MEMORY MAP” section.
*2 : See the “■ MEMORY MAP” section for details of the “ (RAM area) ”.
*3 : “ (Reserved areas) ” are addresses used internally by the system and may not be used.
*4 : The “ (Area reserved for system use) ” contains setting registers used by the evaluation tools.
Notes : • LPMCR, CKSCR, and WDTC are initialized by some types of reset and not by others. The initial values
listed are for the case when the registers are initialized.
• The boundary address “####H” between the “ (RAM area) ” and “ (Reserved area) ” differs depending on
the product. See the “■ MEMORY MAP” section for details.
• OCU compare registers ch.0 to ch.3 use 16-bit freerun timer 0 and OCU compare registers ch.4 to ch.7
use 16-bit freerun timer 1. Note that 16-bit freerun timer 0 is also used by input capture 0 and 1 (ICU) .
Address Abbreviated
Register
Name Register Name Peripheral Name Initial Value
0000BEHICR14 Interrupt control register 14 Interrupt controller 0 0 0 0 0 1 1 1B
0000BFHICR15 Interrupt control register 15 0 0 0 0 0 1 1 1B
0000C0H
to
0000FFH (Access prohibited) *1
000100H
to
00####H (RAM area) *2
00####H
to
001FEFH (Reserved area) *3
001FF0H
PADR0
Detection address setting register 0
(low byte)
Address match
detection function
XXXXXXXXB
001FF1HDetection address setting register 0
(middle byte) XXXXXXXXB
001FF2HDetection address setting register 0
(high byte) XXXXXXXXB
001FF3H
PADR1
Detection address setting register 1
(low byte) XXXXXXXXB
001FF4HDetection address setting register 1
(middle byte) XXXXXXXXB
001FF5HDetection address setting register 1
(high byte) XXXXXXXXB
001FF6H
to
001FFFH (Reserved area) *3
0 : Initial value of bit is “0”.
1 : Initial value of bit is “1”.
X : Initial value of bit is undefined.
MB90520A/520B Series
28
■INTERRUPTS, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
(Continued)
Interrupt EI2OS
Support Interrupt Vector Interrupt Control Register Priority
No. Address ICR Address
Reset #08 FFFFDCHHigh
INT 9 instruction #09 FFFFD8H
Exception #10 FFFFD4H
8/10-bit A/D converter #11 FFFFD0HICR00 0000B0H
Timebase timer #12 FFFFCCH
DTP0/DTP1
(external interrupt 0/external interrupt 1) #13 FFFFC8HICR01 0000B1H
16-bit freerun timer 0 overflow #14 FFFFC4H
Extended I/O serial interface 1 #15 FFFFC0HICR02 0000B2H
Wakeup interrupt #16 FFFFBCH
Extended I/O serial interface 2 #17 FFFFB8HICR03 0000B3H
DTP2/DTP3
(external interrupt 2/external interrupt 3) #18 FFFFB4H
8/16-bit PPG timer 0 counter borrow #19 FFFFB0HICR04 0000B4H
DTP4/DTP5
(external interrupt 4/external interrupt 5) #20 FFFFACH
8/16-bit up/down counter/timer 0
compare match #21 FFFFA8HICR05 0000B5H
8/16-bit up/down counter/timer 0
overflow, up/down direction change #22 FFFFA4H
8/16-bit PPG timer 1 counter borrow #23 FFFFA0HICR06 0000B6H
DTP6/DTP7
(external interrupt 6/external interrupt 7) #24 FFFF9CH
Output compare 1 (OCU) ch.4, ch.5 match #25 FFFF98HICR07 0000B7H
Clock timer #26 FFFF94H
Output compare 1 (OCU) ch.6, ch.7 match #27 FFFF90HICR08 0000B8H
16-bit freerun timer 1 overflow #28 FFFF8CH
8/16-bit up/down counter/timer 1
compare match #29 FFFF88HICR09 0000B9H
8/16-bit up/down counter/timer 1
overflow, up/down direction change #30 FFFF84H
Input capture 0 (ICU) capture #31 FFFF80HICR10 0000BAH
Input capture 1 (ICU) capture #32 FFFF7CH
Output compare 0 (OCU) ch.0 match #33 FFFF78HICR11 0000BBH
Output compare 0 (OCU) ch.1 match #34 FFFF74H
×
×
×
×
×
×
×
×
×
×
MB90520A/520B Series
29
(Continued)
: Supported
: Not supported
: Supported, includes EI2OS stop function
Interrupt EI2OS
Support Interrupt Vector Interrupt Control Register Priority
No. Address ICR Address
Output compare 0 (OCU) ch.2 match #35 FFFF70HICR12 0000BCH
Output compare 0 (OCU) ch.3 match #36 FFFF6CH
UART (SCI) receive complete #37 FFFF68HICR13 0000BDH
16-bit reload timer 0 #38 FFFF64H
UART (SCI) send complete #39 FFFF60HICR14 0000BEH
16-bit reload timer 1 #40 FFFF5CH
Flash memory #41 FFFF58HICR15 0000BFH
Delayed interrupt generation module #42 FFFF54HLow
×
×
×
MB90520A/520B Series
30
■PERIPHERAL RESOURCES
1. I/O Ports
• The I/O ports can be used as general-purpose I/O ports (parallel I/O ports) . The MB90520A and 520B series
have 11 ports (85 pins) . The ports share pins with the inputs and outputs of the peripheral functions.
• The por t data registers (PDR) are used to output data to the I/O pins and capture the input signals from the
I/O ports.
Similarly, the port direction registers (DDR) set the I/O direction (input or output) for each individual port bit.
• The following tables list the I/O ports and peripheral functions with which they share pins.
Notes
• Port 9 contains general-purpose I/O ports with N-ch open-drain output circuits.
• Connect an external pull-up resistor when using port 9 pins as outputs.
• Port 6 shares pins with the analog inputs. When using port 6 as a general-purpose port, ensure that the
corresponding analog input enable register (ADER) bits are set to “0”. ADER is initializ ed to “FFH” after a reset.
Pin Name
(Port) Pin Name (Peripheral) Peripheral Function that Shares Pin
Port 0 P00 − P06 INT0 − INT6 External interrupts
P07 Not shared
Port 1 P10 − P17 WI0 − WI7 Wakeup interrupts
Port 2
P20 − P23 IN00 − IN11 Input capture (unit 0)
P24, P25 AIN0, BIN0 8/16-bit up/down counter/timer 0
P26 ZIN0/INT7 8/16-bit up/down counter/timer 0, external interrupt
Port 3
P30 Not shared
P31 CKOT Clock monitor function
P32 − P35 OUT0 − OUT3 Output compare (unit 0)
P36, P37 PPG00, PPG01 8/16-bit PPG timer 0
Port 4
P40, P41 PPG10, PPG11 8/16-bit PPG timer 1
P42 − P44 SIN0, SOT0, SCK0 UART (SCI)
P45 − P47 SIN1, SOT1, SCK1 Extended I/O serial interface 0
Port 5 P50 − P52 SIN2/AIN1,
SOT1/BIN1,
SCK1/ZIN1
8/16-bit up/down counter/timer 0
Extended I/O serial interface 1
P53, P54 DA0, DA1 8-bit D/A converter
Port 6 P60 − P67 AN0 − AN7 8/16-bit A/D converter
Port 7 P70 − P73
TIN0/OUT4,
TOT0/OUT5,
TIN1/OUT6,
TOT1/OUT7
16-bit reload timers 0, 1
Output compare (unit 1)
P74 − P77 COM0 − COM3 LCD control driver common output
Port 8 P80 − P87 SEG16 − SEG23 LCD control driver segment output
Port 9 P90 − P97 SEG24 − SEG31 LCD control driver segment output
Port A PA0 − PA7 SEG8 − SEG15 LCD control driver segment output
MB90520A/520B Series
31
•Block diagrams
Pch
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read
Peripheral function input Pull-up resistor
option connect/
disconnect setting
Pin
Standby control (SPL = 1)
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P00 to P07, P10 to P17
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read
Peripheral function input
Pin
Standby control (SPL = 1)
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P20 to P27
MB90520A/520B Series
32
Pch
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read
Peripheral function input*
Pin
Standby control (SPL = 1)
Peripheral function output*
Peripheral function
output approval*
Pull-up resistor
option connect/
disconnect setting
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
* : Peripheral function I/O is equivalent to I/O of peripheral function.
P40 to P47
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read
Peripheral function input*
Standby control (SPL = 1)
Peripheral function output*
Peripheral function
output approval*
Pin
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
* : Peripheral function I/O is equivalent to I/O of peripheral function.
P30 to P37, P50 to P52, P70 to P73
MB90520A/520B Series
33
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read
D/A analog output
Standby control (SPL = 1)
D/A analog pin
output approval
Pin
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P53, P54
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read
LCD common output
Standby control (SPL = 1)
Common pin
output approval
Pin
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P74 to P77
MB90520A/520B Series
34
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read
Analog input
Standby control (SPL = 1)
Pin
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P60 to P67
Pch
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read Standby control (SPL = 1)
LCD Segment output
Segment pin
output approval
Pin
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P80 to P87, PA0 to PA7
MB90520A/520B Series
35
Nch
Internal data bus
PDR (Port data register)
PDR read
Output latch
PDR write
DDR (Port direction register)
Direction latch
DDR write
DDR read Standby control (SPL = 1)
LCD Segment output
Segment pin
output approval
Pin
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P90 to P97
MB90520A/520B Series
36
2. Timebase Timer
• The timebase timer is an 18-bit freerun timer (timebase timer/counter) that counts up synchronized with the
main clock (oscillation clock : HCLK divided by 2) .
• The timer can generate interrupt requests at a specified interval, with four different interval time settings
available.
• The timer supplies the operating cloc k for peripheral functions including the oscillation stabilization dela y timer
and watchdog timer.
•Timebase timer interval settings
• HCLK : Oscillation clock frequency
• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.
•Period of clocks supplied from timebase timer
• HCLK : Oscillation clock frequency
• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.
Internal Count Clock Period Interval Time
2/HCLK (0.5 µs)
212/HCLK (approx. 1.024 ms)
214/HCLK (approx. 4.096 ms)
216/HCLK (approx. 16.384 ms)
219/HCLK (approx. 131.072 ms)
Peripheral Function Clock Period
Oscillation stabilization delay
for the main clock
210/HCLK (approx. 0.256 ms)
213/HCLK (approx. 2.048 ms)
215/HCLK (approx. 8.192 ms)
217/HCLK (approx. 32.768 ms)
Watchdog timer
212/HCLK (approx. 1.024 ms)
214/HCLK (approx. 4.096 ms)
216/HCLK (approx. 16.384 ms)
219/HCLK (approx. 131.072 ms)
PPG timer 29/HCLK (approx. 0.128 ms)
MB90520A/520B Series
37
•Block diagram
The actual interrupt request number for the timebase timer is :
Interrupt request number : #12 (0CH)
TBIE TBOF TBR TBC1 TBC0
× 21× 22× 23× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
Counter clear
circuit Interval timer
selector
OF OF OF
To PPG timer To watchdog timer
To oscillation
stabilization delay
time selector
in clock controller
Timebase timer/counter
HCLK divided
by 2
Reset*1
Clear stop mode, etc.*2
Switch clock mode*3
TBOF clear TBOF set
Timebase timer control register
(TBTC)
Timebase timer interrupt signal
OF : Overflow
HCLK : Oscillation clock frequency
*1 : Power-on reset, release of hardware standby mode, watchdog reset
*2 : Clear stop mode, main clock mode, PLL clock mode, and pseudo-clock mode
*3 : Main → PLL clock, Sub → main clock, Sub → PLL clock
MB90520A/520B Series
38
3. Wa tchdog Timer
• The watchdog timer is a timer/counter used to detect faults such as program runaway.
• The watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer.
• Once star ted, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs,
the CPU is reset.
•Interval time for the watchdog timer
* : The diff erence between the maximum and minimum w atchdog timer interval times is due to the timing when the
counter is cleared.
* : As the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock timer,
clearing the timebase timer (when operating on HCLK) or the clock timer (when oper ating on SCLK) lengthens
the time until the watchdog timer reset is generated.
•Watchdog timer count clock
• Events that stop the watchdog timer
1 : Stop due to a power-on reset
2 : Reset due to recovery from hardware standby mode
3 : Watchdog reset
• Events that clear the watchdog timer
1 : External reset input from the RST pin.
2 : Writing “0” to the software reset bit.
3 : Writing “0” to the watchdog control bit (second and subsequent times) .
4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) .
5 : Changing to pseudo-clock mode (clears the watchdog timer and temporarily halts the count) .
6 : Changing to clock mode (clears the watchdog timer and temporarily halts the count) .
7 : Changing to stop mode (clears the watchdog timer and temporarily halts the count) .
HCLK : Oscillation Clock (4 MHz) SCLK : Sub-Clock (8.192 kHz)
Min Max Clock Period Min Max Clock Period
Approx. 3.58 ms Approx. 4.61 ms 214 ± 211 / HCLK Approx. 0.438 s Approx. 0.563 s 212 ± 29 / SCLK
Approx. 14.33 ms Approx. 18.30 ms 216 ± 213 / HCLK Approx. 3.500 s Approx. 4.500 s 215 ± 212 / SCLK
Approx. 57.23 ms Approx. 73.73 ms 218 ± 215 / HCLK Approx. 7.000 s Approx. 9.000 s 216 ± 213 / SCLK
Approx. 458.75 ms Approx. 589.82 ms 221 ± 218 / HCLK Approx. 14.00 s Approx. 18.00 s 217 ± 214 / SCLK
WTC : WDCS HCLK : Oscillation clock
PCLK : PLL clock SCLK : Sub-clock
“0” Count the clock timer output. Count the clock timer output.
“1” Count the timebase timer output.
MB90520A/520B Series
39
•Bloc k diagram
PONR STBR WRST ERST SRST WTE WT1 WT0
× 21× 22× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
2
4
× 21× 22× 25× 26× 27× 28× 29× 210 × 211 × 212 × 213 × 214 × 215
4
Watchdog timer control register (WDTC)
Watchdog timer
Reset
Change to sleep mode
Change to pseudo-clock mode
Change to clock mode
Change to stop mode
Counter
clear
control circuit
Counter
clock
selector
Watchdog timer
reset
generation circuit
2-bit
counter
Start
To
internal
reset
circuit
Clear
Main clock
(HCLK divided by 2)
Sub-clock
(Timebase timer/counter)
(Clock counter)
HCLK : Oscillation clock frequency
MB90520A/520B Series
40
4. 8/16-bit PPG (Programmable Pulse Generator) Timers 0 and 1
The 8/16-bit PPG timer is a two-channel reload timer module (PPG0 and PPG1) that can generate pulse outputs
with the periods specified in the table below and with duty ratios between 0 and 100%. Note that the pulse
periods are different depending on the operation mode.
*1 : 8 + 8-bit PPG output operation mode consists of using the lower 8 bits as a prescaler for the PPG timer.
*2 : The values enclosed in ( ) indicate the times for a machine clock frequency of 16 MHz.
Operation
Mode Count Clock*2 PPG00, PPG01 (PPG ch0) PPG10, PPG11 (PPG ch1)
Interval Time Output Pulse
Width Interval Time Output Pulse
Width
8-bit
PPG output
Independent
2ch operation
mode
φ/1 (62.5 ns) 1/φ to 28/φ1/φ to 29/φ1/φ to 28/φ1/φ to 29/φ
φ/2 (125 ns) 2/φ to 29/φ22/φ to 210/φ2/φ to 29/φ22/φ to 210/φ
φ/4 (250 ns) 22/φ to 210/φ23/φ to 211/φ22/φ to 210/φ23/φ to 211/φ
φ/8 (500 ns) 23/φ to 211/φ24/φ to 212/φ23/φ to 211/φ24/φ to 212/φ
φ/16 (1000 ns) 24/φ to 212/φ25/φ to 213/φ24/φ to 212/φ25/φ to 213/φ
HCLK/512 (128 µs) 29/HCLK to
217/HCLK 210/HCLK to
218/HCLK 29/HCLK to
217/HCLK 210/HCLK to
218/HCLK
16-bit
PPG output
operation
mode
φ/1 (62.5 ns) 1/φ to 216/φ1/φ to 217/φ1/φ to 216/φ1/φ to 217/φ
φ/2 (125 ns) 2/φ to 217/φ22/φ to 218/φ2/φ to 217/φ22/φ to 218/φ
φ/4 (250 ns) 22/φ to 218/φ23/φ to 219/φ22/φ to 218/φ23/φ to 219/φ
φ/8 (500 ns) 23/φ to 219/φ24/φ to 220/φ23/φ to 219/φ24/φ to 220/φ
φ/16 (1000 ns) 24/φ to 220/φ25/φ to 221/φ24/φ to 220/φ25/φ to 221/φ
HCLK/512 (128 µs) 29/HCLK to
225/HCLK 210/HCLK to
226/HCLK 29/HCLK to
225/HCLK 210/HCLK to
226/HCLK
8 + 8-bit
PPG output
operation
mode*1
φ/1 (62.5 ns) 1/φ to 26/φ1/φ to 29/φ1/φ to 216/φ1/φ to 217/φ
φ/2 (125 ns) 2/φ to 29/φ22/φ to 210/φ2/φ to 217/φ22/φ to 218/φ
φ/4 (250 ns) 22/φ to 210/φ23/φ to 211/φ22/φ to 218/φ23/φ to 219/φ
φ/8 (500 ns) 23/φ to 211/φ24/φ to 212/φ23/φ to 219/φ24/φ to 220/φ
φ/16 (1000 ns) 24/φ to 212/φ25/φ to 213/φ24/φ to 220/φ25/φ to 221/φ
HCLK/512 (128 µs) 29/HCLK to
217/HCLK 210/HCLK to
218/HCLK 29/HCLK to
225/HCLK 210/HCLK to
226/HCLK
MB90520A/520B Series
41
• PPG timer channels and PPG pins
The figure below shows the relationship between the 8/16-bit PPG channels and PPG pins on the MB90520A/
520B series.
PPG0
PPG1
Pin
Pin
Pin
Pin
PPG00 output pin
PPG01 output pin
PPG10 output pin
PPG11 output pin
MB90520A/520B Series
42
•Bloc k diagram
PPG00
Pin
Pin
CLK
R
SQ
PEN0 PE00 PIE0
PUF0 Reserved
PCS2 PCS0 PCM2
PCM1 PCM0 PE11 PE01
PCS1
PPG01
3
2
PPG0 reload
register
PRLH0
("H" level register)
PPG0 temporary
buffer (PRLBH0)
Reload register
"L" level/"H" level
selector
PPG0 down counter
(PCNT0)
PRLL0
("L" level register)
Select signal
Reload
Underflow
Clear
Count start value
Timebase timer output
(HCLK/512)
Peripheral clock (φ/1)
Peripheral clock (φ/2)
Peripheral clock (φ/4)
Peripheral clock (φ/8)
Peripheral clock (φ/16)
"H" level data bus
"L" level data bus
PPG0 operation mode control register
(PPGC0)
Interrupt
request output
Operation mode control signal
PPG1 underflow
PPG0 underflow
(to PPG1)
Pulse selector
PPG0
output latch
Invert
PPG output control circuit
Count
clock
selector
Select signal
PPG01 output control register (PPGOE)
: Undefined
Reserved : Reserved bit
HCLK : Oscillation clock frequency
φ : Machine clock frequency
8/16-bit PPG timer 0
MB90520A/520B Series
43
PPG10
PPG11
CLK
MD0
R
SQ
PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved
PCS2 PCS0 PCM2
PCM1 PCM0 PE11 PE01
PCS1
3
2
Pin
Pin
PPG1
reload
register PRLH1
("H" level register)
PPG1 temporary
buffer (PRLBH1)
Reload selector
"L" level/"H"
level selector
PPG1 down counter
(PCNT1)
PRLL1
("L" level register)
Select signal
Reload
Underflow
Clear
Count start value
Timebase timer output
(HCLK/512)
Peripheral clock (φ/1)
Peripheral clock (φ/2)
Peripheral clock (φ/4)
Peripheral clock (φ/8)
Peripheral clock (φ/16)
"H" level data bus
"L" level data bus
PPG1 operation mode control register
(PPGC1)
Interrupt
request output
Operation
mode control signal
PPG1
output latch
Invert
PPG output control circuit
Count
clock
selector Select signal
PPG01 output control register (PPGOE)
PPG1 underflow
(to PPG0)
PPG0 underflow
(from PPG0)
: Undefined
Reserved : Reserved bit
HCLK : Oscillation clock frequency
φ : Machine clock frequency
8/16-bit PPG timer 1
MB90520A/520B Series
44
5. 16-bit Reload Timers 0 and 1 (With Event Count Function)
The 16-bit reload timers have the following functions.
• The count clock can be selected from three internal clock and the external event clock.
• Either software trigger or e xternal trigger can be selected as the start signals for 16-bit reload timers 0 and 1.
• An interrupt to the CPU can be generated when an underflow occurs on 16-bit reload timer 0 and 1. This
interrupt allows the timers to be used as interval timers.
• Two diff erent operation modes can be selected when an underflow occurs on 16-bit reload timer 0 and 1 : one-
shot mode in which timer operation halts when an underflow occurs or reload mode in which the reload register
value is loaded into the timer and counting continues.
• Extended intelligent I/O service (EI2OS) is supported.
• The MB90520A/520B series contains two 16-bit reload timer channels.
•16-bit reload timer operation modes
•Interval times for the 16-bit reload timers
Note : The values enclosed in ( ) and the example interval times are for a machine clock frequency of 16 MHz.
“T” is the machine cycle and is 1/ (machine clock frequency) .
Count Clock Start Trigger Operation when an Underflow Occurs
Internal clock
(3 clocks available)
Software trigger One-shot mode
Reload mode
External trigger One-shot mode
Reload mode
Event clock
Software trigger One-shot mode
Reload mode
External trigger One-shot mode
Reload mode
Count Clock Count Clock Period Example Interval Times
Internal clock
21T (0.125 µs) 0.125 µs to 8.192 ms
23T (0.5 µs) 0.5 µs to 32.768 ms
25T (2.0 µs) 2.0 µs to 131.1 ms
Event clock 23T or longer 0.5 µs or longer
MB90520A/520B Series
45
•Bloc k diagram
TMRLR
TMR
CLK
TIN
UF
EN TOT
CLK
3
32
φ
CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD UFINTE CNTE TRG
Internal data bus
16-bit reload register
Reload signal Reload
control circuit
16-bit timer register
Count clock generation circuit
Machine
clock Prescaler
Gate
input Clock
pulse
detection
circuit
Clear
trigger
Internal
clock
Pin Input
control
circuit
Clock
selector
External clock Select
signal
Function selection
Timer control status register (TMCSR)
Wait signal
Output to internal
peripheral functions
Output control circuit
Output signal
generation
circuit Pin
Operation
control
circuit
Interrupt
request output
MB90520A/520B Series
46
6. 16-bit I/O Timers
The 16-bit I/O timers consist of a two-channel 16-bit freerun timer, two-channel input capture, and eight-channel
output compare. The output compare channels can be used to generate eight independent wavefor m outputs
based on the 16-bit freerun timer. The input capture channels can be used to measure input pulse widths and
external clock periods.
•Structure of I/O timers in the MB90520A/520B series
• 16-bit freerun timer functions
• The count value for the 16-bit freerun timer sets the base time for the input capture and output compare
functions.
• An interrupt can be generated when the 16-bit freerun timer overflows.
• Extended intelligent I/O service (EI2OS) can be generated.
• 16-bit freerun timers 0 and 1 can be cleared to “0000H” when an external reset is input, on setting the timer
clear bit (TCCS : CLR = 1) , and when a compare match occurs on output compare 0 to 4.
• The count clock frequency can be selected from the following four clocks :
4/φ (250 ns) , 16/φ (1.0 µs) , 64/φ (4.0 µs) , 256/φ (16.0 µs)
Note : φ is the machine clock frequency. The values in ( ) are for 16 MHz machine clock.
•Input capture functions
• The input capture saves the value of the 16-bit freerun timer and generates an interrupt request when the
specified edge is detected on the trigger input from the external trigger input pin (IC00 or IC01/IC10 or IC11) .
• Input capture channels 0 and 1 can perform input capture and generate interrupt request independently.
• Extended intelligent I/O service (EI2OS) can be generated.
• Detection of rising edges, falling edges, or either edge can be selected as the trigger edge.
• When using input capture 0, either the IC00 or IC01 pin can be used. Note, however, that masking one pin
only is not possible.
• When using input capture 1, either the IC10 or IC11 pin can be used. Note, however, that masking one pin
only is not possible.
• Output compare functions
• The output compare channels compare the values set in output compare registers 0 to 7 with the 16-bit freerun
timers 0 and 1 count v alues and in vert the level of the corresponding output compare pin and clear the 16-bit
freerun timer to “0000H” when a match is detected.
• Extended intelligent I/O service (EI2OS) can be generated.
• The initial output levels at the output compare pins can be set after the microcontroller boots.
• The output levels from the eight output compare channels are controlled independently. Similarly, interrupt
requests are also generated independently by each channel.
16-bit Freerun Timer Output Compare Input Capture
16-bit I/O timer
(unit 0) 16-bit freerun timer 0 Output compare 0 to 3
(unit 0) Input capture 0 and 1
(unit 0)
16-bit I/O timer
(unit 1) 16-bit freerun timer 1 Output compare 4 to 8
(unit 1)
MB90520A/520B Series
47
•Bloc k diagram
IVFReserved IVFE STOP MODE CLR CLK1 CLK0
OF
2
φ
STOPCLK CLR
Timer data registers
(TCDT0, TCDT1* )
16-bit counter
Prescaler
Timer control
status registers
(TCCS0,TCCS1 *)
Counter value output
to input capture
and output compare
Internal data bus
Output compare register 0
(Output compare register 4* )
match signal
Freerun timer
overflow interrupt request
φ : Machine clock frequency
OF : Overflow
* : Name for 16-bit freerun timer channel 1
16-bit freerun timer
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
22
IN00
IN01
IN10
IN11
Edge detection circuit
Pin
Pin
Pin
Pin
Input capture
control status register
(ICS01)
16-bit freerun timer 0
Input capture register 1 (IPCP0)
Input capture register 0 (IPCP1)
Internal data bus
Input capture
interrupt request
Input capture
MB90520A/520B Series
48
CMOD OTE1 OTE0 OTD1OTD0 IOP1 IOP0 IOE1 IOE0 CST1 CST0
CMOD OTE1 OTE0 OTD1OTD0 IOP1 IOP0 IOE1 IOE0 CST1 CST0
2
22
2
OUT3 (OUT7*)
OUT2 (OUT6*)
OUT1 (OUT5*)
OUT0 (OUT4*)
OCP3 (OCP7*)
OCP2 (OCP6*)
OCP1 (OCP5*)
OCP0 (OCP4*)
Internal data bus
Output compare control
status registers
(OSC23, OSC67*)
Timer data registers
(TCDT0, TCDT1* )
16-bit freerun timer 0 (1*)
Compare control circuit 3 (7*)
Output compare register 3 (7*)
Compare control circuit 2 (6*)
Output compare register 2 (6*)
Compare control circuit 1 (5*)
Output compare register 1 (5*)
Compare control circuit 0 (4*)
Output compare register 0 (4*)
Output compare control
status registers
(OSC01, OSC45*)
Output compare
interrupt request
Output control
circuit 3 (7*)
Output control
circuit 2 (6*)
Output control
circuit 1 (5*)
Output control
circuit 0 (4*)
Pin
Pin
Pin
Pin
Output compare
interrupt request
* : Name for output compare unit 1
Output compare
MB90520A/520B Series
49
7. 8/16-bit Up/Down Counter/Timers 0 and 1
• The 8/16-bit up/down counter/timers can operate in timer mode, up/down count mode, and phase difference
count mode.
• The unit can be used as either a 2-channel × 8-bit or 1-channel × 16-bit up/down counter/timer.
•8/16-bit up/down counter/timer functions
Operation
Mode Count Mode Count Clock
(Count Edge) Function of
ZIN Pin Other Functions
8-bit
× 2-channel
mode
Timer mode 2/φ, 4/φ
(φ : Machine clock frequency)
• Compare function
• Reload function
• Compare/reload function
• Compare/reload prohibit
• The direction of the
previous count can be
determined from the up/
down flag.
• Interrupt requests can be
generated on the following
conditions :
1 : Compare match
2 : Underflow or overflow
3 : Count direction
change
Up/down count
mode
Counts up on detecting speci-
fied edge on the AIN pin.
Counts down on detecting spec-
ified edge on the BIN pin.
Counter clear
function
Gate function
Phase
difference count
mode
(multiply by 2)
Reads the AIN pin input level on
detecting a rising or falling edge
on the BIN pin and counts up or
counts down.
Counter clear
function
Gate function
Phase
difference count
mode
(multiply by 4)
Reads the AIN pin input level on
detecting a rising or falling edge
on the BIN pin and counts up or
counts down. Similarly, reads
the BIN pin input level on detect-
ing a rising or falling edge on the
AIN pin and counts up or counts
down.
Counter clear
function
Gate function
16-bit
× 1-channel
mode
Timer mode 2/φ, 4/φ
(φ : Machine clock frequency)
Up/down count
mode
Counts up on detecting speci-
fied edge on the AIN pin.
Counts down on detecting spec-
ified edge on the BIN pin.
Counter clear
function
Gate function
Phase
difference count
mode
(multiply by 2)
Reads the AIN pin input level on
detecting a rising or falling edge
on the BIN pin and counts up or
counts down.
Counter clear
function
Gate function
Phase
difference count
mode
(multiply by 4)
Reads the AIN pin input level on
detecting a rising or falling edge
on the BIN pin and counts up or
counts down. Similarly, reads
the BIN pin input level on detect-
ing a rising or falling edge on the
AIN pin and counts up or counts
down.
Counter clear
function
Gate function
MB90520A/520B Series
50
•Bloc k diagram
RCR0
UDCR0
ZIN0
BIN0
AIN0
CTUTUCRERLDE UDCC CGSC CGE1CGE0
CITE UDIE CMPFOVFFUDFFUDF1 UDF0CSTR
CDCF CFIE CLKSCMS1CMS0CES1 CES0M16E
Internal data bus
Reload compare register 0 Reload
control circuit
Up/down count register 0
Carry/
Borrow
(to
channel
1)
Counter control
register 0 (CCR0: L)
Pin
Pin
Pin
Edge/level
detection
circuit
Counter
clear circuit
Overflow
Underflow
Compare
control circuit
Machine clock Pre-
scaler Up/down
count
selector
Count clock
Counter status
register 0 (CSR0)
Edge
detection
circuit Interrupt
request
Interrupt
request
Counter control register 0 (CCR0: H) M16E
(to channel 1)
8/16-bit up/down counter/timer 0
MB90520A/520B Series
51
• Pins and interrupt numbers
8/16-bit up/down counter/timer 0
AIN0 pin : P24/AIN0
BIN0 pin : P25/BIN0
ZIN0 pin : P26/ZIN0
Compare match interrupt number : #21 (15H)
Interrupt number for underflow/overflow interrupt, count direction change interrupt : #2 (16H)
8/16-bit up/down counter/timer 1
AIN1 pin : P50/AIN1
BIN1 pin : P51/BIN1
ZIN1 pin : P52/ZIN1
Compare match interrupt number : #29 (1DH)
Interrupt number for underflow/overflow interrupt, count direction change interrupt : #3 (1EH)
RCR1
UDCR1
ZIN1
AIN1
BIN1
CTUTUCRERLDE UDCC CGSC CGE1CGE0
CITE UDIE CMPFOVFFUDFFUDF1 UDF0CSTR
CDCF CFIE CLKSCMS1CMS0CES1 CES0
Internal data bus
Reload compare register 1
Reload
control circuit
Up/down count register 1
Counter control
register 1 (CCR1: L)
Pin
Pin
Pin
Edge/level
detection
circuit
Counter
clear circuit
Overflow
Underflow
Compare
control circuit
Machine clock Pre-
scaler Up/down
count clock
selector
Count clock
Counter status
register 1 (CSR1)
Edge
detection
circuit
Interrupt
request
Interrupt
request
Counter control register 1 (CCR1: H)
Carry/Borrow
(from channel 0)
M16E
(from
channel 1)
8/16-bit up/down counter/timer 1
MB90520A/520B Series
52
8. Extended I/O Serial Interfaces 0 and 1
• The extended I/O serial interfaces are serial I/O interfaces that perform clock-synchronized data transfer.
• The MB90520A/520B series contain two internal extended I/O serial interf ace channels.
• Either LSB-first or MSB-first data transmission format can be selected.
•Extended I/O serial interface functions Function
Transmission direction • Transmit and receive can be handled simultaneously. (A setting is required to select
transmit or receive.)
Transmission mode • Clock synchronous (data transfer only)
Transmission clock • Internal shift clock mode (Uses the communications prescaler output clock.)
• External shift clock mode (Inputs the clock signal from SCK1 and SCK2.)
Transmission speed
• When using internal shift clock :
Up to 1 MHz operation can be achieved (for a 16 MHz machine clock with the divisor
setting for the communication prescaler set to 8) . Speeds faster than 1 MHz are not
possible.
• When using an external shift clock :
As a minimum of 5 machine cycles are required, when the machine clock is 16 MHz
the maximum input frequency for the external shift clock is 16 MHz / 5 = 3.2 MHz.
Data transmission
format
• LSB-first or MSB-first, selectable
• Data transfer only
• Number of data bits = 8 (fixed)
Interrupt request
generation • Interrupt generated when transfer completes
EI2OS support • Supports use of the extended intelligent I/O service.
MB90520A/520B Series
53
•Bloc k diagram
MODE BDS SOE SCOE
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT
MD DIV3 DIV2 DIV1 DIV0
SIN
SCK
SOT
Internal data bus
(MSB-first)
D7 to D0 D7 to D0 (LSB-first)
Transmission direction selection
Pin
Pin
Serial data register
(SDR)
Read
Write
Pin
Control circuit Shift clock counter
Machine clock
Communications
prescaler
Serial mode control
status register (SMCS) Interrupt request
Communications prescaler
register (CDCR)
MB90520A/520B Series
54
9. UART (SCI : Serial Communication Interface)
• The UART (SCI) is a general-pur pose ser ial communications interface for perfor ming synchronous or asyn-
chronous communications with external devices.
• The interface provides bi-directional communications in both clock synchronous and clock asynchronous
modes.
• Includes a master-slave communication function (multi-processor mode) .
• Can generate interrupt requests at receive complete, receive error detected, and transmit complete timings.
Also supports EI2OS.
•UART (SCI) functions Function
Data buffer • Full-duplex double-buffered
Transmission modes • Clock synchronous (with no start/stop bit, no parity bit)
• Clock asynchronous (start-stop sync)
Baud rate
• Can use dedicated baud rate generator.
• Can use external clock input.
• Can use clock supplied by 16-bit reload timer 0.
• For machine clock speeds of 6 MHz, 8 MHz, 10 MHz, 12 MHz, and 16 MHz :
Available speeds for asynchronous communications : 31250 bps, 9615 bps,
4808 bps, 2404 bps, and 1202 bps
Available speeds for synchronous communications : 1 Mbps, 500 Kbps,
250 Kbps, 125 Kbps, and 62.5 Kbps
Number of data bits • 7 bits (when parity is used for asynchronous normal mode)
• 8 bits (when parity is not used)
Signal format • Non return to zero (NRZ) format
Receive error detection
• Framing errors (not available in clock synchronous mode)
• Overrun errors
• Parity errors (not available in clock synchronous mode and multi-processor
mode)
Interrupt requests • Receive interrupt (Receive complete or receive error detected)
• Transmit interrupt (Transmission complete)
• Both transmit and receive support the extended intelligent I/O service (EI2OS) .
Master/slave communication
function
(multi-processor mode) • Used for 1 (master) to n (slave) communications. (Can only be used as master)
EI2OS support • Supports the extended intelligent I/O service (EI2OS)
MB90520A/520B Series
55
•UART (SCI) operation modes
: Available
: Not available
+1 : Address/data bit used for communication control
Notes :
• The number of data bits must be set to eight for multi-processor and clock synchronous modes.
• A parity bit cannot be used in multi-processor and clock synchronous modes.
• Only data can be transferred in clock synchronous mode. Star t and stop bits cannot be added to the trans-
mission data.
Operation Mode No. of Data Bits Parity Bit No. of Stop Bits
7 bits 8 bits None Use 1 bit 2 bits
Mode 0 Asynchronous Normal mode
(1-to-1)
Mode 1 Asynchronous Multi-processor mode
(1-to-n) (+1)
Mode 2 Clock
synchronous
Clock synchronous
mode
(one-to-one)
× ×
××××
×
MB90520A/520B Series
56
•Bloc k diagram
SCK
Pin
Pin
SIN
SOT
MD1
MD0
CS2
CS1
CS0
SOE
SCKE
MD
DIV3
DIV2
DIV0
DIV1
PEN
P
SBL
CL
A/D
REC
TXE
RXE
PE
ORE
FRE
RDRF
TDRE
TIE
RIE
Control bus
Dedicated baud rate
generator
16-bit
reload timer 0 Clock
selector Receive clock
Transmit
clock
Receive
control
circuit
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Receive
shift register
Serial input
data register
Transmission
control circuit
Transmission
start circuit
Transmit
bit counter
Transmit
parity counter
Transmission
shift register
Serial output
data register
Receive complete
Receive status
evaluation circuit
Receive
interrupt
request output
Transmit
interrupt
request output
Pin
Transmission start
Receive error
detection signal
for EI2OS
Internal data bus
Communi-
cation
prescaler
register
Serial
mode
register
Serial
control
register
Serial
status
register
MB90520A/520B Series
57
10. DTP (Data Transfer Peripheral) /External Interrupt Circuit
The DTP/exter nal interrupt function detects interrupt requests and data transfer requests input from external
devices and passes these to the CPU as external interrupt requests. This block can also activate the extended
intelligent I/O service (EI2OS) .
•DTP/external interrupt functions
External Interrupt DTP Function
Input pins • 8 channels (INT0 to INT7)
Interrupt
conditions
• Can be set independently for each channel (each pin) in the detection level setup register
(ELVR) .
• “H” level, “L” level,
rising edge, or falling edge input “H” level or “L” level input
Interrupt control • Interrupts can be enabled or disabled in the DTP/external interrupt enable register (ENIR) .
Interrupt flag • The DTP/external interrupt request register (EIRR) stores interrupt requests.
Processing
selection • Set EI2OS to be disabled (ICR : ISE = 0) • Set EI2OS to be enabled (ICR : ISE = 1)
Interrupt
execution • Jumps to interrupt handler routine • Jumps to interrupt handler routine after
automatic data transfer by EI2OS completes.
EI2OS support • Supports the extended intelligent I/O service (EI2OS)
MB90520A/520B Series
58
•Bloc k diagram
INT7
INT6
INT5
INT4
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
ER7 ER6 ER5 ER4 ER3 ER2
INT3
INT2
INT1
INT0
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
ER1 ER0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
Detection level setting register (ELVR)
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Internal data bus
DTP/external interrupt input
detection circuit DTP/external interrupt request
register (EIRR)
DTP/external interrupt enable
register (ENIR)
Interrupt request
signal
Interrupt request
signal
MB90520A/520B Series
59
11. Wakeup Interrupts
• The wak eup interrupt function detects wak eup interrupt requests from external devices b y detecting “L” le v els
input to the wakeup interrupt input pins (WI0 to WI7) and passes these to the CPU for interrupt processing.
• Wakeup interrupts can be used to wakeup the microcontroller from standby mode. (However, wakeup interrupts
cannot be used to recover from hardware standby mode.)
• Not supported by the extended intelligent I/O service (EI2OS) .
•Wakeup interrupt functions
•Bloc k diagram
Function and Control
Input pins • 8 channels (8 pins : WI0 to WI7)
Interrupt trigger • “L” level inputs. One interrupt flag is shared by all eight channels.
Interrupt control • Interrupt requests can be enabled or disabled in the wakeup interrupt control
register (EICR) .
Interrupt flag • Interrupt requests are stored in the wakeup interrupt flag register (EIFR) .
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
WIF
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
WI0
WI1
WI2
WI3
WI4
WI5
WI6
WI7
Internal data bus
Wakeup interrupt
control register (EICR) Wakeup interrupt
flag register (EIFR)
Interrupt request detection circuit
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Wakeup
interrupt request
: Undefined
MB90520A/520B Series
60
12. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this
hardware interrupt can be specified by software.
•Delayed interrupt generation module functions
•Bloc k diagram
Function and Control
Interrupt trigger
• Writing “1” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0 = 1) generates an interrupt request.
• Writing “0” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0 = 0) clears the interrupt request.
Interrupt control • No enable/disable register is provided for this interrupt.
Interrupt flag • Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0) .
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
R0
Internal data bus
Delayed interrupt request generation/clear
register (DIRR)
Interrupt
request latch
S
RInterrupt request
signal
: Undefined
MB90520A/520B Series
61
13. 8/10-bit A/D Converter
• The 8/10-bit A/D con verter uses RC successive approximation to convert analog input voltages to an 8-bit or
10-bit digital value.
• The input signals can be selected from the eight analog input pin channels.
• Either a software trigger, internal timer output, or external pin trigger can be selected to trigger the start of A/
D conversion.
•8/10-bit A/D converter functions
•8/10-bit A/D converter conversion modes
Function
A/D conversion
time
• Sampling time : Can be selected from 64, 128, or 4096 machine cycles.
The minimum is 4 µs.
• Compare time : Can be selected from 44, 99, or 176 machine cycles.
The minimum is 4.4 µs.
• A/D conversion time = sampling time + conversion time.
The minimum A/D conversion time is 10.2 µs.
Conversion method • RC successive approximation with sample & hold circuit
Resolution • 8-bit or 10-bit, selectable
Analog input pins • Up to eight channels can be used. However, two or more channels cannot be used
simultaneously.
Interrupts • An interrupt request can be generated when A/D conversion completes.
A/D conversion
start trigger • Selectable : software, internal timer output, or falling edge on input from external pin
EI2OS support • Supported by the extended intelligent I/O service (EI2OS) .
Description
Single-shot
conversion mode Performs A/D conversion sequentially from the start channel to the end channel. A/D con-
version halts after conversion completes for the end channel.
Continuous
conversion mode Performs A/D conversion sequentially from the start channel to the end channel. A/D con-
version starts again from the start channel after conversion completes for the end channel.
Incremental
conversion mode
A/D conversion is performed for one channel then halts until the next trigger. After conver-
sion is performed for the end channel, the next conversion is performed for the start chan-
nel, and repeated this operation.
MB90520A/520B Series
62
•Bloc k diagram
BUSY INT INTE PAUS STS1 STS0 STAT Re-
served MD1 MD0 ANS2 ANS1ANS0 ANE2 ANE1ANE0
AN7
AN6
ADTG
TO
AN5
AN4
AN3
AN2
AN1
AN0 AVRH, AVRL
AVCC
AVSS
26
2
2
2
φ
SELB ST1 ST0 CT1 CT0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A/D control
status register
(ADCS)
Interrupt request output
Trigger
selector Decoder
Internal data bus
Analog
channel
selector
Sample &
hold circuit
Comparator
Control circuit
D/A converter
A/D data
register
(ADCR)
TO : Internal timer output
: Undefined
Reserved : Always set to “0”.
φ : Machine clock
MB90520A/520B Series
63
14. 8-bit D/A Converter
• The 8-bit D/A converter performs R-2R D/A conversion with 8-bit resolution.
• Two D/A converter channels with independent analog outputs are provided.
•D/A converter functions
•D/A conver ter theoretical output voltage
Note : DVCC voltage : D/A converter reference voltage. This must not exceed VCC.
Also, always ensure that DVSS is equipotential to VSS.
Function
D/A conversion time •The settling time is 12.5 µs. This is independent of the machine clock.
Conversion method • R-2R conversion
Resolution • 8-bit
Analog output pins • Two output pins are provided. Both pins can be used simultaneously.
Interrupts • None
D/A conversion trigger • Set the digital value in the D/A data register (DADR) , then enable D/A output in the
D/A control register (DACR) to start analog output from the D/A output pin.
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
D/A Data Register Setting Theoretical Output Voltage Value
00H0 / 256 × DVCC voltage ( = 0 V)
00H1 / 256 × DVCC voltage
••• •••
FEH254 / 256 × DVCC voltage
FFH255 / 256 × DVCC voltage
MB90520A/520B Series
64
•Block diagram
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
DAE
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
2R
DVR
DVSS
DA
2R
2R
2R
2R
2R
2R
2R
R
R
R
R
R
R
R
2R
Internal data bus
Internal data bus
D/A data register (DADR)
D/A conversion circuit
Pin
Standby control (SPL = 1)
D/A control register (DACR)
Standby control : Controls stop mode (SPL = 1) , pseudo-clock mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode.
MB90520A/520B Series
65
15. Clock Timer
• The clock timer is a 15-bit freerun timer that counts up synchronized with the sub-clock.
• Seven different interval time settings are available.
• This timer provides the clock for the sub-clock’s oscillation stabilization delay timer and the watchdog timer.
• This timer always counts the sub-clock, regardless of the settings in the clock selection register (CKSC) .
•Clock timer functions
•Clock timer interval times
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
•Cloc k periods generated by clock timer
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
Function
Interval time • Selectable from the seven settings shown in the table below.
Clock timer size • 15-bit
Clock supply • Oscillation stabilization delay timer for sub-clock and watchdog timer
Source clock • Sub-oscillation clock divided by four. (SCLK : Sub-clock)
Interrupts • Interval time overflow
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
Sub-Clock Period Interval Time
SCLK (122 µs)
29/SCLK (approx. 62.5 ms)
210/SCLK (approx. 125.0 ms)
211/SCLK (approx. 250.0 ms)
212/SCLK (approx. 500.0 ms)
213/SCLK (approx. 1.0 s)
214/SCLK (approx. 2.0 s)
216/SCLK (approx. 4.0 s)
Clock Supply Clock Period
Oscillation stabilization delay timer
for sub-clock 214/SCLK (approx. 2.0 s)
Watchdog timer
210/SCLK (approx. 125.0 ms)
213/SCLK (approx. 1.0 s)
214/SCLK (approx. 2.0 s)
216/SCLK (approx. 4.0 s)
MB90520A/520B Series
66
•Bloc k diagram
OF : Overflow
SCLK : Sub-clock frequency
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
× 21× 22× 23× 24× 25× 26× 27× 28× 29× 210 × 211 × 212 × 213 × 215
× 214
OF OF OF OF OF OF
OF
SCLK
Clock timer counter
To
watchdog
timer
Power-on reset
Change to hardware standby mode
Change to stop mode
Counter
clear circuit
Interval
timer selector
To oscillation stabilization
delay timer for sub-clock
Clock timer interrupt
Clock timer control register (WTC)
MB90520A/520B Series
67
16. LCD Controller/Driver
• The LCD controller/driver can drive an LCD (Liquid Crystal Display) directly.
• The LCD is driven by 4 common outputs and 32 segment outputs.
• The output mode can be set to 1/2, 1/3, or 1/4 duty.
•LCD controller/driver functions
•Bias, duty, and common output combinations
Function
Divider resistor for LCD
drive power • Either the internal resistor (approx. 100 kΩ) or an externally connected resistor
can be selected.
Common outputs • Max 4 outputs (The corresponding pins cannot be used as I/O ports when using
an LCD.)
Segment outputs • Max 32 outputs (of these, 24 pins can be used as I/O ports in blocks of 8 pins.)
Display data memory • 16 bytes of RAM for internal display are provided
Duty • 1/2, 1/3, or 1/4 can be selected.
Bias • 1/3 only supported
Drive clock • Either the oscillation clock (HCLK) or sub-clock (SCLK) can be used.
Interrupts • None
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
Bias 1/2 Duty Output Mode 1/3 Duty Output Mode 1/4 Duty Output Mode
1/3 bias COM0 and COM1 outputs
used COM0 to COM2 outputs
used COM0 to COM3 outputs
used
MB90520A/520B Series
68
•Bloc k diagram
6
32
22
4
HCLK
SCLK
CSS LCEN VSEL BK MS1
V0
V1
V2
V3
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG29
SEG30
SEG31
MS0 FP1 FP0
COM3 COM2 COM1 COM0
SEG5
Re-
served Re-
served
SEG4 SEG3 SEG2 SEG1 SEG0
Common pin selection register
(LCDCMR)
LCDC control
register 0
(LCR0)
Internal data bus
Prescaler Timing
controller
Display data memory
(16 bytes)
LCDC control register 1
(LCR1)
Controller
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Internal
divider
resistor
Common
driver
Segment
driver
AC
conversion circuit
Driver
: Undefined bit
HCLK : Main clock
SCLK : Sub-clock
MB90520A/520B Series
69
17. Communications Prescaler
• Supplies the clock to the dedicated baud rate generator used by the UART (SCI) and extended I/O serial
interfaces.
• By dividing the machine cloc k to produce the clock supply to the dedicated baud rate gener ator, the baud rate
can be specified independently of the machine clock speed.
• The communications prescaler can divide the machine clock frequency φ by the following seven ratios to
generate the clock supply to the dedicated baud rate generator and extended I/O serial interface :
φ/2, φ/3, φ/4, φ/5, φ/6, φ/7, φ/8
•Communications prescaler functions
Note : As the same output from the communications prescaler is supplied to both the U ART (SCI) and the extended
I/O serial interface, the transfer clock speed settings must be revised if the communications prescaler settings
are changed.
•Bloc k diagram
Function
Clock supply • Dedicated baud rate generator for the UART (SCI) and the extended I/O serial
interface. However, the same clock is supplied to both peripherals.
Divided clock frequency • φ/2, φ/3, φ/4, φ/5, φ/6, φ/7, φ/8 (φ : Machine clock frequency)
Interrupts • None
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
MD DIV3 DIV2 DIV1 DIV0
φ/2 φ/3 φ/4 φ/5 φ/6 φ/7 φ/8
φ
SMCS:SMD2 ∼ SMD0 = 000B ∼ 100B
SMR:CS2 ∼ CS0 = 000B ∼ 100B
UART
CDCR Extended serial I/O
Communications prescaler
: Undefined
φ : Machine clock frequency
MB90520A/520B Series
70
18. Address Match Detection Function
• If the program address during program e xecution matches the v alue set in one of the detection address setting
registers (PADR) , the address match detection function replaces the instruction being ex ecuted with the INT9
instruction and executes the interrupt handler program.
• The address match detection function provides a simple method of correcting prog r amming errors (patching)
using RAM or similar.
•Address match detection functions
•Bloc k diagram
Function
No. of address settings • Two channels (two addresses can be set)
Interrupts • An interrupt is generated when the program address matches the detection
address setting register.
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
ADE1Reserved Reserved Reserved Reserved ADD1 ADE0 ADD0
PADR1 (24 bit)
PADR0 (24 bit)
Address latch
PACSR
Internal data bus
Detection address setting register
Detection address setting register
Address detection control register (PACSR)
Comparator
INT9 instruction
(generates an INT9 interrupt)
Reserved : Always set to “0”.
MB90520A/520B Series
71
19. ROM Mirror Function Selection Module
The ROM mirror function selection module enables ROM data in FF bank to be read by accessing 00 bank.
•ROM mirror function selection module functions
•Relationship between addresses in the ROM mirror function
•Bloc k diagram
Function
Mirror setting address • Data in FFFFFFH to FF4000H in FF bank can be read from 00FFFFH to 004000H
in 00 bank.
Interrupts • None
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
004000H
00FFFFH
FE0000H
FEFFFFH
FF0000H
FF4000H
FFFFFFH
00 bank mirror area
Mirrored ROM data area
in FF bank
ROM area in MB90523A, 523B, and F523B
ROM area in MB90522A and 522B
MI
ROM
ROM mirror function selection register (ROMM)
Internal data bus
Address
Data
Address space
FF bank 00 bank
MB90520A/520B Series
72
20. Low Power Consumption (Standby) Modes
The power consumption of F2MC-16LX devices can be reduced by various settings relating to the operating
clock selection.
•Functions of each CPU operation mode
CPU Operation
Clock Operation
Mode Explanation
PLL clock
Normal run The CPU and peripheral functions operate using the oscillation clock (HCLK) mul-
tiplied by the PLL circuit.
Sleep The peripheral functions only operate using the oscillation clock (HCLK) multiplied
by the PLL circuit.
Pseudo-
clock The timebase timer only operates using the oscillation clock (HCLK) multiplied by
the PLL circuit.
Stop The oscillation clock is stopped and the CPU and peripherals halt operation.
Main clock
Normal run The CPU and peripheral functions operate using the oscillation clock (HCLK) di-
vided by 2.
Sleep The peripheral functions only operate using the oscillation clock (HCLK) divided
by 2.
Stop The oscillation clock is stopped and the CPU and peripherals halt operation.
Sub-clock
Normal run The CPU and peripheral functions operate using the sub-clock (SCLK) . The os-
cillation clock stops.
Sleep The peripheral functions only operate using the sub-clock (SCLK) . The oscillation
clock stops.
Clock The clock timer only operates using the sub-clock (SCLK) . The oscillation clock
stops.
Stop The oscillation clock and sub-clock are stopped and the CPU and peripherals halt
operation.
CPU
intermittent
operation Normal run The oscillation clock (HCLK) divided by 2 operates intermittently for fixed time in-
tervals.
Hardware
standby Stop The oscillation clock and sub-clock are stopped and the CPU and peripherals halt
operation.
MB90520A/520B Series
73
21. Clock Monitor Function
The clock monitor function outputs the machine clock divided by a specified amount to the clock monitor pin
(CKO T) .
•Clock monitor functions
•Output frequency of the clock monitor function
•Block diagram
Function
Output frequency • Machine clock divided by 2 to 32 (8 settings available)
Interrupts • None
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
FRQ2 - 0
Bits Machine Clock
Divide Ratio When φ
φφ
φ =
==
= 16 MHz When φ
φφ
φ =
==
= 8 MHz When φ
φφ
φ =
==
= 4 MHz
Period Frequency Period Frequency Period Frequency
000Bφ/21125 ns 8 MHz 250 ns 4 MHz 500 ns 2 MHz
001Bφ/22250 ns 4 MHz 500 ns 2 MHz 1.0 µs1 MHz
010Bφ/23500 ns 2 MHz 1.0 µs1 MHz2.0 µs 500 kHz
011Bφ/241.0 µs1 MHz2.0 µs500 kHz4.0 µs 250 kHz
100Bφ/252.0 µs 500 kHz 4.0 µs250 kHz8.0 µs 125 kHz
101Bφ/264.0 µs 250 kHz 8.0 µs 125 kHz 16.0 µs62.5 kHz
110Bφ/278.0 µs 125 kHz 16.0 µs 62.5 kHz 32.0 µs 31.25 kHz
111Bφ/2816.0 µs 62.5 kHz 32.0 µs31.25 kHz64.0 µs 15.625 kHz
CKENFRQ2
CKOT
Pin
FRQ1 FRQ0
3
φ
Internal data bus
Prescaler Count
clock
selector
Output enable
Clock output enable
register (CLKR)
: Undefined
φ : Machine clock frequency
MB90520A/520B Series
74
22. 1 Mbit Flash Memory
• This section describes the flash memory on the MB90F523B and does not apply to evaluation products and
MASK ROM versions.
• The flash memory is located in banks FE to FF in the CPU memory map.
•Flash memory functions
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
•Sector configuration of flash memory
Function
Memory size • 1 Mbit (128 KBytes)
Memory configuration • 128 KWords × 8 bits or 64 KWords × 16 bits
Sector configuration • 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes + 64 KBytes
Sector protect function • Selectable for each sector
Programming algorithm • Automatic programming algorithm (Embedded Algorithm* : Equivalent to
MBM29F400TA)
Operation commands
• Compatible with JEDEC standard commands
• Includes an erase pause and restart function
• Data polling and toggle bit write/erase completion
• Erasing by sector available (sectors can be combined in any combination)
No. of write/erase cycles • Min 10,000 guaranteed
Memory write/erase
method
• Can be written and erased using a parallel writer
(Minato Electronics model 1890A, Ando Denki AF9704, AF9705, AF9706,
AF9708, and AF9709)
• Can be written and erased using a dedicated serial writer
(YDC AF200, AF210, AF120, and AF110)
• Can be written and erased by the program
Interrupts • Write and erase completion interrupts
EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) .
SA0 (64 Kbyte)
SA1 (32 Kbyte)
SA2 (8 Kbyte)
SA3 (8 Kbyte)
SA4 (16 Kbyte)
FE0000H
FEFFFH
FF0000H
FF7FFFH
FF8000H
FF9FFFH
FFA000H
FFBFFFH
FFC000H
FEFFFFH
60000H
6FFFFH
70000H
77FFFH
78000H
79FFFH
7A000H
7BFFFH
7C000H
7FFFFH
Flash memory CPU address Writer address*
* : The writer address is the address to use instead of the CPU address when writing data from a parallel
flash memory wr iter. Use the writer address when programming or erasing using a general-purpose
parallel writer.
MB90520A/520B Series
75
•Pins used for Fujitsu standard serial on-board programming
• Overall configuration of connection between serial writer and MB90F523A
Fujitsu standard serial on-board programming uses a flash microcontroller writer made by YDC.
Note : Contact YDC for details of the functions and operation of the flash microcontroller writer (AF220, AF210,
AF120, or AF110) , standard connection cable (AZ210) , and connectors.
Pin Function Explanation
MD2, MD1,
MD0 Mode pins Setting MD2 = MD1 = 1, MD0 = 0 selects flash memory serial program-
ming mode.
X0, X1 Oscillation input pin Flash memory serial programming mode uses the PLL clock with the
multiplier set to 1 as the machine clock. Set the oscillation frequency
used for serial programming to between 3 MHz and 16 MHz.
P00, P01 Write program activation
pins Input P00 = 0 (“L” level) and P01 = 1 (“H” level)
RST Reset pin
HST Hardware standby pin Input an “H” level during flash memory serial programming mode.
SIN0 Serial data input pin
Uses the UART (SCI) in clock synchronous mode.SOT0 Serial data output pin
SCK0 Serial clock input pin
CC pin Capacitor pin for power supply stabilization. Connect an external capac-
itor of approx. 0.1 µF.
VCC Power supply voltage pins If the user system can provide the programming voltage (5 V ± 10%) ,
do not need to connect to the flash microcontroller writer.
VSS GND pin Connect to common GND with the flash microcontroller writer.
Host interface cable (AZ221) Standard cable (AZ210)
Flash microcontroller
writer
+
memory card
Clock synchronous
serial MB90F523A/B
user system
Can operate standalone
RS232C
MB90520A/520B Series
76
■Electrical Characteristics\
1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V)
*1 : AVCC, AVRH, AVRL, and DVCC shall never exceed VCC . AVRH and AVRL shall never exceed AVCC.
Also, AVRL shall never exceed AVRH.
*2 : VCC ≥ AVCC ≥ DVCC ≥ 3.0 V.
*3 : VI and VO shall never exceed VCC + 0.3 V.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output current is the average current value for a single pin during a 100 ms period.
*6 : The total average current is the average current for all pins during a 100 ms period.
Note : Average output current = operating current × operating ratio
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V *1
AVRH,
AVRL VSS − 0.3 VSS + 6.0 V *1
DVCC VSS − 0.3 VSS + 6.0 V *2
Input voltage VIVSS − 0.3 VSS + 6.0 V *3
Output voltage VOVSS − 0.3 VSS + 6.0 V *3
“L” level maximum output current IOL 15 mA *4
“L” level average output current IOLAV 4mA*
5
“L” level total maximum output current ΣIOL 100 mA
“L” level total average output current ΣIOLAV 50 mA *6
“H” level maximum output current IOH −15 mA *4
“H” level average output current IOHAV −4mA*
5
“H” level total maximum output current ΣIOH −100 mA
“H” level total average output current ΣIOHAV −50 mA *6
Power consumption Pd 400 mW MB90522A/523A/
F523B
300 mW MB90522B/523B
Operating temperature Ta −40 +85 °C
Storage temperature Tstg −55 +150 °C
MB90520A/520B Series
77
2. Recommended Operating Conditions (VSS = AVSS = 0.0 V)
Note : Use a ceramic capacitor or other capacitor with equiva lent frequency characteristics. The capacitance of
the smoothing capacitor connected to the VCC pin must be greater than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage VCC 3.0 5.5 V
Smoothing capacitor CS0.1 1.0 µF
Operating temperature Ta −40 +85 °C
C
CS
C pin diagram
MB90520A/520B Series
78
3. DC Characteristics (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
(Continued)
Parameter Sym-
bol Pin Name Condition Value Unit Remarks
Min Typ Max
“H” level input
voltage
VIHS
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7
VCC = 3.0 V to 5.5 V
0.8 VCC VCC +
0.3 V
VIHM MD0 to MD2 VCC −
0.3 VCC +
0.3 V
“L” level input
voltage
VILS
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7
VSS −
0.3 0.2 VCC V
VILM MD0 to MD2 VSS −
0.3 VSS +
0.3 V
“H” level
output voltage VOH All output pins
other than P90
to P97
VCC = 4.5 V
IOH = −2.0 mA VCC −
0.5 V
“L” level output
voltage VOL All output pins VCC = 4.5 V
IOL = 2.0 mA 0.4 V
Input leak
current IIL All output pins
other than P90
to P97
VCC = 5.5 V
VSS < VI < VCC − 5 5µA
Open-drain
output leak
current Ileak P90 to P97
output pins 0.1 5 µA
Pull-up
resistor RUP
P00 to P07,
P10 to P17
P40 to P47,
MD0, MD1 50 100 200 kΩ
Pull-down
resistor RDOWN MD2 50 100 200 kΩ
Power supply
current*ICC VCC
For VCC = 5 V,
internal frequency
= 16 MHz,
normal operation
40 65 mA MB90522A/
523A
30 60 mA MB90F523B
30 40 mA MB90522B/
523B
MB90520A/520B Series
79
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
(Continued)
Parameter Sym-
bol Pin Name Condition Value Unit Remarks
Min Typ Max
Power supply
current*
ICC
VCC
For VCC = 5 V,
internal frequency
= 8 MHz,
normal operation
20 25 mA MB90522A/
523A
15 20 mA MB90F523B
15 20 mA MB90522B/
523B
For VCC = 5 V,
internal frequency
= 16 MHz,
A/D operation in
progress
50 70 mA MB90522A/
523A
45 65 mA MB90F523B
35 45 mA MB90522B/
523B
For VCC = 5 V,
internal frequency
= 8 MHz,
A/D operation in
progress
25 30 mA MB90522A/
523A
20 25 mA MB90F523B
20 25 mA MB90522B/
523B
For VCC = 5 V,
internal frequency
= 16 MHz,
D/A operation in
progress
55 70 mA MB90522A/
523A
50 70 mA MB90F523B
40 50 mA MB90522B/
523B
For VCC = 5 V,
internal frequency
= 8 MHz,
D/A operation in
progress
30 35 mA MB90522A/
523A
25 30 mA MB90F523B
20 25 mA MB90522B/
523B
Writing or erasing
flash memory 50 75 mA MB90F523B
ICCS
For VCC = 5 V,
internal frequency
= 16 MHz,
sleep mode
815mA
MB90522A/
523A
15 20 mA MB90F523B
/522B/523B
For VCC = 5 V,
internal frequency
= 8 MHz,
sleep mode
710mA
MB90522A/
523A
12 18 mA MB90F523B
/522B/523B
ICCL
For VCC = 5 V,
internal frequency
= 8 kHz,
sub-clock mode,
Ta = 25 °C
0.1 1.0 mA MB90522A/
523A/522B/
523B
4 7 mA MB90F523B
MB90520A/520B Series
80
(Continued)
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
* : Current values are provisional and are subject to change without notice to allow for improvements to the char-
acteristics. The power supply current is measured with an external clock.
Parameter Sym-
bol Pin Name Condition Value Unit Remarks
Min Typ Max
Power supply
current*
ICCLS
VCC
For VCC = 5 V,
internal frequency
= 8 kHz,
sub-sleep mode,
Ta = 25 °C
30 50 µA
ICCT
For VCC = 5 V,
internal frequency
= 8 kHz,
clock mode,
Ta = 25 °C
15 30 µA
ICCH Sleep mode,
Ta = 25 °C520µA
Input
capacitance CIN Other than
AVCC, AVSS, C,
VCC, and VSS 10 80 pF
LCD divider
resistor RLCD V0 − V1,
V1 − V2,
V2 − V3 50 100 200 kΩ
Output
impedance for
COM0 to
COM3
RVCOM COM0 to COM3
V1 to V3 = 5.0 V
2.5 kΩ
Output
impedance for
SEG00 to
SEG31
RVSEG SEG00 to
SEG31 15 kΩ
LCDC leak
current ILCDC
V0 to V3,
COM0 to
COM3,
SEG00 to
SEG31
±5µA
MB90520A/520B Series
81
4. AC Characteristics
(1) Reset and Hardware Standby Input Timings
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
* : See “ (3) Clock Timings” for more information about tCP (internal operating clock cycle time) .
Parameter Symbol Pin
Name Condition Value Unit Remarks
Min Typ
Reset input time tRSTL RST 4 tCP*ns
Hardware standby input time tHSTL HST 4 tCP*ns
RST
HST 0.2 VCC
tRSTL, tHSTL
0.2 VCC
CL
Pin
CL is the load capacitance for the pin during testing.
Measurement conditions for AC ratings
MB90520A/520B Series
82
(2) Power-On Reset (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
* : VCC must be less than 0.2 V before power-on.
Notes : • The above rating values are for generating a power-on reset.
• When HST = “L”, always apply the power supply in accordance with the above ratings regardless of whether
a power-on reset is required.
• Some internal registers are only initialized by a power-on reset. Always apply the power supply in cordance
with the above ratings if you wish to initialize these registers.
Parameter Symbol Pin
Name Condi-
tion Value Unit Remarks
Min Typ
Power supply rise time tRVCC 0.05 30 ms *
Power supply cutoff time tOFF VCC 4ms For repeated operation
VCC
VCC
3.0 V
VSS
tR
0.2 V0.2 V 2.7 V
tOFF
0.2 V
Maintain RAM data
Recommended rate of voltage
rise is 50 mV/ms or less.
Sudden changes in the power supply voltage may cause a power-on reset.
The recommended practice if you wish to change the power supply voltage while the device is operating is
to raise the voltage smoothly as shown below. Also, changes to the supply voltage should be performed when
the PLL clock is not in use. The PLL clock may be used, however, if the rate of voltage change is 1 V/s or less.
MB90520A/520B Series
83
(3) Clock Timings (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter Sym-
bol Pin
Name Condi-
tion Value Unit Remarks
Min Typ Max
Clock frequency FCX0, X1 316 MHz
FCL X0A, X1A 32.768 kHz
Clock cycle time tHCYL X0, X1 62.5 333 ns
tLCYL X0A, X1A 30.5 µs
Input clock pulse width
PWH
PWL X0 10 ns Recommended duty
ratio = 30% to 70%
PWLH
PWLL X0A 15.2 µs
Input clock rise/fall
time tCR
tCF X0 5ns
When using an
external clock
Internal operating
clock frequency fCP 1.5 16 MHz When using main clock
fLCP 8.192 kHz When using sub-clock
Internal operating
clock cycle time tCP 62.5 666 ns When using main clock
tLCP 122.1 µs When using sub-clock
0.8 VCC 0.8 VCC0.8 VCC
0.2 VCC 0.2 VCC
X0
tHCYL
PWH PWL
tCF tCR
X0 and X1 clock timing
0.8 VCC 0.8 VCC0.8 VCC
0.2 VCC 0.2 VCC
X0A
tLCYL
PWLH PWLL
tCF tCR
X0A and X1A clock timing
MB90520A/520B Series
84
The AC ratings are measured at the following reference voltages.
5.5
4.5
3.0
2.7
16
12
8
9
4
6
3
2
3468
Source Oscillation Clock fCP (MHz)
12 16
1.5 3 8
Internal Clock fCP (MHz)
10 16
Supply Voltage VCC (V)
Guaranteed operation range for MB90V520A
PLL guaranteed
operation range A/D, D/A guaranteed
voltage range
Guaranteed operation
range for MB90522A, 523A,
MB90522B, 523B, and F523B
×4×3×2×1
Divided by 2
Internal Clock fCP (MHz)
Relationship between internal operating clock frequency and power supply voltage
Relationship between oscillation frequency and internal operating clock frequency
PLL guaranteed operation range
0.8 VCC
0.2 VCC
2.4 V
0.8 V
0.7 VCC
0.3 VCC
Input signal waveform
Hysteresis input pin
Pins other than hysteresis input or MD input pins
Output signal waveform
Output pin
MB90520A/520B Series
85
(4) Clock Output Timings (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter Symbol Pin
Name Condition Value Unit Remarks
Min Typ
Cycle time tCYC CLK VCC = 5.0 V ± 10%62.5 ns
CLK ↑ → CLK ↓tCHCL 20 ns
CLK
tCYC
2.4 V 2.4 V
0.8 V
tCHCL
MB90520A/520B Series
86
(5) UART (SCI) Timings (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
* : See “ (3) Clock Timings” for more information about tCP (internal operating clock cycle time) .
Notes : • These are the AC ratings for CLK synchronous mode.
• CL is the load capacitor connected to the pin for testing.
Parameter Sym-
bol Pin Name Condition Value Unit Re-
marks
Min Typ
Serial clock cycle time tSCYC SCK0 to SCK2
Internal shift clock
mode, output pin
load is
CL = 80 pF + 1 TTL
8 tCP*ns
SCK ↓ → SOT delay time tSLOV SCK0 to SCK2
SOT0 to SOT2 −80 80 ns
Valid SIN → SCK ↑tIVSH SCK0 to SCK2
SIN0 to SIN2 100 ns
SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK2
SIN0 to SIN2 60 ns
Serial clock “H” pulse width tSHSL SCK0 to SCK2
External shift clock
mode, output pin
load is
CL = 80 pF + 1 TTL
4 tCP*ns
Serial clock “L” pulse width tSLSH SCK0 to SCK2 4 tCP*ns
SCK ↓ → SOT delay time tSLOV SCK0 to SCK2
SOT0 to SOT2 150 ns
Valid SIN → SCK ↑tIVSH SCK0 to SCK2
SIN0 to SIN2 60 ns
SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK2
SIN0 to SIN2 60 ns
MB90520A/520B Series
87
SCK0 to SCK2
SOT0 to SOT2
SIN0 to SIN2
SCK0 to SCK2
SOT0 to SOT2
SIN0 to SIN2
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLSH tSHSL
tSLOV
tIVSH tSHIX
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Internal shift clock mode
External shift clock mode
MB90520A/520B Series
88
(6) Timer Input Timings (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
* : See “ (3) Clock Timings” for more information about tCP (internal operating clock cycle time) .
(7) Timer Output Timings (AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter Symbol Pin Name Condition Value Unit Remarks
Min Typ
Input pulse width tTIWH
tTIWL
IC00/01,
IC10/11
TI0, TI1 4 tCP*ns
Parameter Symbol Pin Name Condition Value Unit Remarks
Min Typ
CLK ↑ → TOUT change time tTO
OUT0 to OUT7
PG00/01
PG10/11
TO0, TO1
30 ns
IC00/01
IC10/11
TI0, TI1
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
CLK
(TOUT : OUT0 to OUT7, PG00/01, PG10/11, TO0, TO1)
2.4 V
tTO
2.4 V
0.8 V
TOUT
MB90520A/520B Series
89
5. Electrical Characteristics for the A/D Converter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, Ta = −40 °C to +85 °C)
* : Current when 8/10-bit A/D converter not used and CPU in stop mode (VCC = AVCC = AVRH = 5.0 V)
Note : See “ (3) Clock Timings” in “4. AC Ratings” for more information about tCP (internal operating clock cycle time) .
Parameter Sym-
bol Pin Name Value Unit Remarks
Min Typ Max
Resolution 8/10 bit
Total error ±5.0 LSB
Linearity error ±2.5 LSB
Differential linearity error ±1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVSS
− 3.5 LSB AVSS
+ 0.5 LSB AVSS
+ 4.5 LSB mV
Full-scale transition voltage VFST AN0 to AN7 AVRH
− 6.5 LSB AVRH
− 1.5 LSB AVRH
+ 1.5 LSB mV
A/D conversion time 163 tcp ns At machine
clock = 16
MHz
Compare time 99 tcp ns At machine
clock = 16
MHz
Analog port input current IAIN AN0 to AN7 10 µA
Analog input voltage VAIN AN0 to AN7 AVRL AVRH V
Reference voltage AVRH AVRL + 3.0 AVCC V
AVRL 0 AVRH − 3.0 V
Power supply current IAAVCC 5mA
IAH AVCC 5µA*
Reference voltage supply
current IRAVRH 400 µA
IRH AVRH 5µA*
Variation between channels AN0 to AN7 4LSB
MB90520A/520B Series
90
6. A/D Converter Glossary
(Continued)
Resolution : The change in analog voltage that can be recognized by the A/D converter.
Linearity error : The deviation between the actual conversion characteristics and the line linking the
zero transition point (“00 0000 0000B” ←→ “00 0000 0001B”) and the full scale transi-
tion point (“11 1111 1110B” ←→ “11 1111 1111B”) .
Differential linearity error : The variation from the ideal input voltage required to change the output code by 1 LSB.
Total error : The total error is the difference between the actual value and the theoretical value.
This includes the zero-transition error, full-scale transition error, and linearity error.
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVRL
Digital Output
AVRH
0.5 LSB
0.5 LSB
VNT
(Measured value)
{1 LSB × (N − 1) + 0.5 LSB}
Total Error
Analog Input
Actual conversion
characteristic
Actual conversion
characteristic
Theoretical characteristic
1 LSB = (Theoretical value)
VOT (Theoretical value) = AVRL + 0.5 LSB [V]
VNT : Voltage at which digital output changes from (N − 1) to N
AVRH − AVRL
1024*[V]
Total error for digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB [LSB]
VFST (Theoretical value) = AVRH − 1.5 LSB [V]
* : For 10-bit resolution, this value is 1024 (210) . For 8-bit resolution, this value is 256 (28) .
MB90520A/520B Series
91
(Continued)
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVRL AVRH AVRL AVRH
N + 1
N
N − 1
N − 2
VNT
VNT
V (N + 1)T
VOT (Measured value)
VFST
{1 LSB × (N − 1)
+ VOT}
Digital Output
Linearity Error
Analog Input
Digital Output
Differential Linearity Error
Analog Input
Actual conversion characteristic
Actual conversion
characteristic
Actual conversion
characteristic
Actual conversion
characteristic
Theoretical characteristic
Theoretical characteristic
(Measured value)
(Measured value)
(Measured
value)
(Measured value)
VOT : Voltage at which digital output changes from “000H” to “001H”
VFST : Voltage at which digital output changes from “3FEH” to “3FFH”
Differential linearity error for digital output N =
Linearity error for digital output N =
V (N + 1) T − VNT
1 LSB − 1 LSB [LSB]
VNT − {1 LSB × (N − 1) + VOT}
1 LSB [LSB]
1 LSB = VFST − VOT
1022*[V]
* : For 10-bit resolution, this value is 1022 (210 − 2) . For 8-bit resolution, this value is 254 (28 − 2) .
MB90520A/520B Series
92
7. Notes for A/D Conversion
The recommended exter nal circuit impedance of analog inputs for MB90V520 is approximately 5 kΩ or less,
that for MB90F523B is approximately 15.5 kΩ or less, and that for MB90522A/523A/522B/523B is appro ximately
10 kΩ or less.
If using an external capacitor, the capacitance should be several thousand times the level of the chip’s internal
capacitor to allow for the partial potential between the external and internal capacitance.
If the impedance of the exter nal circuit is too high, the analog voltage sampling inter val may be too short. (for
sampling time = 4 µs, machine clock frequency = 16 MHz) .
•Error
The relative error increases as |AVRH − AVRL| becomes smaller.
CRON
Analog input
Comparator
MB90522A/523A/522B/523B
RON = 2.2 kΩ approx.
C = 45 pF approx.
MB90F523B
RON = 2.6 kΩ approx.
C = 28 pF approx.
Note : The values listed are an indication only.
• Block diagram of analog input circuit model
MB90520A/520B Series
93
8. Electrical Characteristics for the D/A Converter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
9. Flash Memory Program/Erase
Parameter Symbol Pin
Name Value Unit Remarks
Min Typ Max
Resolution 8bit
Differential linearity error ±0.9 LSB
Absolute accuracy ±1.2 %
Linearity error ±1.5 LSB
Conversion time 10 20 µsFor load capacitance
= 20 pF
Analog reference voltage DVCC VSS + 3.0 AVCC V
Current consumption for
reference voltage IDVR DVCC 120 300 µA
IDVRS 10 µA Stop mode
Analog output impedance 20 kΩ
Parameter Condition Value Unit Remarks
Min Typ Max
Sector erase time
Ta = + 25 °C
VCC = 5.0 V
115s
Excludes 00H programming
prior erasure
Chip erase time 5sExcludes 00H programming
prior erasure
Word (16-bit width)
programming time 16 3,600 µs Excludes system-level overhead
Program/Erase cycle 10,000 cycle
Data hold time 100 K h
MB90520A/520B Series
94
■EXAMPLE CHARACTERISTICS
Power supply current (MB90523A)
(Continued)
ICC − VCC
Ta = +25 °C, External clock input ICCS − VCC
Ta = +25 °C, External clock input
ICCL − VCC
Ta = +25 °C, External clock input ICCLS − VCC
Ta = +25 °C, External clock input
VCC (V)
ICC (mA)
60
50
40
30
20
10
023 45 6
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
VCC (V)
ICCS (mA)
20
15
10
5
023456
f = 2 MHz
f = 4 MHz
f = 8 MHz
f = 10 MHz
f = 12 MHz
f = 16 MHz
VCC (V)
ICCL (µA)
70
60
50
40
30
20
10
023456
f = 8 kHz
VCC (V)
ICCLS (µA)
20
15
10
5
023456
f = 8 kHz
MB90520A/520B Series
95
(Continued)
ICCT − VCC
Ta = +25 °C, External clock input
Example MB90523A VOH − IOH Characteristics
Ta = +25 °C, VCC = 4.5 V Example MB90523A VOL − IOL Characteristics
Ta = +25 °C, VCC = 4.5 V
VCC (V)
ICCT (µA)
234 56
f = 8 kHz
0
2
4
6
8
10
IOH (mA)
VCC − VOH (mV)
1000
900
800
700
600
500
400
300
200
100
0210 3 4 5 6 7 8 9 10 11 12 IOL (mA)
VOL (mV)
1000
900
800
700
600
500
400
300
200
100
0210 3 4 5 6 7 8 9 10 11 12
MB90520A/520B Series
96
■ORDERING INFORMATION
Part No. Package Remarks
MB90522APFF
MB90523APFF
MB90522BPFF
MB90F523BPFF
120-pin, Plastic LQFP
(FPT-120P-M05)
MB90522APFV
MB90523APFV
MB90522BPFV
MB90F523BPFV
120-pin, Plastic QFP
(FPT-120P-M13)
MB90520A/520B Series
97
■PACKAGE DIMENSIONS
(Continued)
120-pin Plastic LQFP
(FPT-120P-M05) * : Pins width and pins thickness include plating thickness.
Dimensions in mm (inches)
C
1998 FUJITSU LIMITED F120006S-3C-4
0.07(.003) M
INDEX
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
130
31
6091
120
6190
LEAD No.
(Stand off)
0.10±0.10
(.004±.004)
0.25(.010)
(.018/.030)
0.45/0.75
(.020±.008)
0.50±0.20
(Mounting height)
0~8°
Details of "A" part
1.50 +0.20
–0.10
+.008
–.004
.059
"A"
0.40(.016) 0.16±0.03
(.006±.001) 0.145±0.055
(.006±.002)
0.08(.003)
MB90520A/520B Series
98
(Continued)
120-pin Plastic QFP
(FPT-120P-M13) * : Pins width and pins thickness include plating thickness.
Dimensions in mm (inches)
C
2000 FUJITSU LIMITED F120013S-c-3-5
0°~8°
.139 –.008
+.013
–0.20
+0.32
3.53
.008 –.006
+.004
–0.15
+0.10
0.20
(Stand off)
0.25(.010)
Details of "A" part
6190
60
31
301
LEAD No.
91
120
20.00±0.10(.787±.004)SQ
22.60±0.20(.890±.008)SQ
0.50(.020) 0.22±0.05
(.009±.002) 0.08(.003) M
"A"
0.08(.003)
(.006±.002)
0.145±0.055
INDEX
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mouting height)
MB90520A/520B Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0203
FUJITSU LIMITED Printed in Japan
