TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 Triple-Supply Power Management IC for Powering FPGAs and DSPs Check for Samples: TPS75003 FEATURES DESCRIPTION * The TPS75003 is a complete power management solution for FPGA, DSP and other multi-supply applications. The device has been tested with and meets all of the Xilinx Spartan-3, Spartan-3E and Spartan-3L start-up profile requirements, including monotonic voltage ramp and minimum voltage rail rise time. Independent Enables for each output allow sequencing to minimize demand on the power supply at start-up. Soft-start on each supply limits inrush current during start-up. Two integrated buck controllers allow efficient, cost-effective voltage conversion for both low and high current supplies such as core and I/O. A 300mA LDO is integrated to provide an auxiliary rail such as VCCAUX on the Xilinx Spartan-3 FPGA. All three supply voltages are offered in user-programmable options for maximum flexibility. 1 23 * * * * * * * Two 95% Efficient, 3A Buck Controllers and One 300mA LDO Tested and Endorsed by Xilinx for Powering the SpartanTM-3, Spartan-3E and Spartan-3L FPGAs Adjustable (1.2V to 6.5V for Bucks, 1.0V to 6.5V for LDO) Output Voltages on All Channels Input Voltage Range: 2.2V to 6.5V Independent Soft-Start for Each Supply Independent Enable for Each Supply for Flexible Sequencing LDO Stable with 2.2mF Ceramic Output Cap Small, Low-Profile 4.5mm x 3.5mm x 0.9mm QFN Package APPLICATIONS * * * * The TPS75003 is fully specified from -40C to +85C and is offered in a QFN package, yielding a highly compact total solution size with high power dissipation capability. FPGA/DSP/ASIC Supplies Set-Top Boxes DSL Modems Plasma TV Display Panels TPS75003 IN 1 IN 2 IN 3 EN 1 SS1 EN 2 SS2 EN 3 5V _Input V CCAUX IS 1 SW 1 FB 1 IS 2 3A SW 2 BU CK 2 FB 2 OU T3 300m A FB 3 LD O SS3 AG ND DGND DGND 3A BU CK 1 V CCINT 1.2V at 3A + DG ND V CCO 3.3V at 3A + V CCAUX 2.5V at 300mA 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Spartan is a trademark of Xilinx, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2010, Texas Instruments Incorporated TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) PRODUCT VOUT TPS75003 Buck1: Adjustable Buck2: Adjustable LDO: Adjustable For the most current specifications and package information, see the Package Option Addendum located at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) (1) VINX range (IN1, IN2, IN3) TPS75003 UNIT -0.3 to +7.0 V VENX range (EN1, EN2, EN3) -0.3 to VINX +0.3 V VSWX range (SW1, SW2, SW3) -0.3 to VINX +0.3 V VISX range (IS1, IS2, IS3) -0.3 to VINX +0.3 V -0.3 to +7.0 V -0.3 to VINX +0.3 V VOUT3 range VSSX range (SS1, SS2, SS3) VFBX range (FB1, FB2, FB3) Peak LDO output current (IOUT3) Continuous total power dissipation -0.3 to +3.3 V Internally limited -- See Dissipation Ratings Table -- Junction temperature range, TJ -55 to +150 C Storage temperature range -65 to +150 C ESD rating, HBM 1 kV ESD rating, CDM 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION THERMAL METRIC (1) (2) TPS75003 RHL (20 PINS) qJA Junction-to-ambient thermal resistance 42.6 qJCtop Junction-to-case (top) thermal resistance 51.8 qJB Junction-to-board thermal resistance 39.5 yJT Junction-to-top characterization parameter 0.6 yJB Junction-to-board characterization parameter 14.2 qJCbot Junction-to-case (bottom) thermal resistance 2.8 (1) (2) 2 UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2V, VIN3 = 3.0V, VOUT3 = 2.5V, COUT1 = COUT2 = 47mF, COUT3 = 2.2mF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. PARAMETER CONDITIONS MIN TYP MAX UNIT Supply and Logic VINX Input Voltage Range (IN1, IN2, IN3) (1) IQ Quiescent Current, IQ = IDGND + IAGND IOUT1 = IOUT2 = 0mA, IOUT3 = 1mA ISHDN Shutdown Supply Current VEN1 = VEN2 = VEN3 = 0V VIH1, 2 Enable High, enabled (EN1, EN2) VIH3 Enable High, enabled (EN3) VILX Enable Low, shutdown (EN1, EN2, EN3) IENX Enable pin current (EN1, EN2, EN3) 2.2 6.5 V 75 150 mA 0.05 3.0 mA 1.4 VINX V 1.14 VIN3 V 0 0.3 V 0.5 mA VINX V 0.01 Buck Controllers 1 and 2 VOUT1,2 Adjustable Output Voltage Range (2) VFB1,2 Feedback Voltage (FB1, FB2) Feedback Voltage Accuracy (FB1, FB2) VFBX 1.220 V (1) IFB1,2 Current into FB1, FB2 pins VIS1,2 Reference Voltage for Current Sense IIS1,2 Current into IS1, IS2 Pins -2 80 +2 % 0.01 0.5 mA 100 120 mV 0.01 0.5 mA VOUT%/VIN Line Regulation (1) Measured with the circuit in Figure 1, VOUT + 0.5V VIN 6.5V 0.1 %/V VOUT%/IOU Load Regulation Measured with the circuit in Figure 1, 30mA I OUT 2A 0.6 %/A n 1,2 Efficiency (3) Measured with the circuit in Figure 1, IOUT = 1A 94 % tSTR1,2 Startup Time (3) Measured with the circuit in Figure 1, RL = 6, COUT = 100mF, CSS = 2.2nF 5 ms Gate Driver P-Channel and N-Channel MOSFET On-Resistance VIN1,2 > 2.5V 4 RDS,ON1,2 VIN1,2 = 2.2V 6 ISW1,2 Gate Driver P-Channel and N-Channel MOSFET Drive Current tON Minimum On Time 1.36 1.55 1.84 ms tOFF Minimum Off Time 0.44 0.65 0.86 ms T (1) (2) (3) 100 mA To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external components. Minimum VIN3 = VOUT3 + VDO or 2.2V, whichever is greater. Maximum VOUT depends on external components and will be less than VIN. Depends on external components. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 3 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2V, VIN3 = 3.0V, VOUT3 = 2.5V, COUT1 = COUT2 = 47mF, COUT3 = 2.2mF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. PARAMETER CONDITIONS MIN TYP MAX UNIT LDO VOUT3 Output Voltage Range VFB3 Feedback Pin Voltage Feedback Pin Voltage Accuracy (4) VOUT%/VIN Line Regulation (4) VOUT%/IOU 1.0 6.5 - VDO 0.507 2.95V VIN3 6.5V 1mA IOUT3 300mA -4.0 VOUT3 + 0.5V VIN3 6.5V V V +4.0 % 0.075 %/V % / mA Load Regulation 10mA IOUT3 300mA 0.01 VDO Dropout Voltage (VIN = VOUT(NOM) - 0.1) (5) IOUT3 = 300mA 250 350 mV ICL3 Current Limit VOUT = 0.9 x VOUT(NOM) 600 1000 mA IFB3 Current into FB3 pin 0.03 0.1 mA T Vn Output Noise tSD Thermal Shutdown Temperature for LDO UVLO (4) (5) 4 375 BW = 100Hz - 100kHz, IOUT3 = 300mA 400 Shutdown, Temp Increasing 175 Reset, Temp Decreasing 160 mVRMS C Under-Voltage Lockout Threshold VIN Rising 1.80 V Under-Voltage Lockout Hysteresis 100 mV VIN Falling To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external components. Minimum VIN3 = VOUT3 + VDO or 2.2V, whichever is greater. VDO does not apply when VOUT + VDO < 2.2V. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 DEVICE INFORMATION Functional Block Diagram TPS75003 IN1 3A Buck Controller IS1 VIS 1 Switch Control Soft Start Control SS1 EN1 VR E F1 FB1 DGND IN2 3A Buck Controller IS2 VIS2 Switch Control SS2 SW1 SW2 Soft Start Control EN2 VR E F2 FB2 DGND 300mA LDO IN3 OUT3 Thermal/ Current Limit EN3 FB3 VREF 3 SS3 AGND Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 5 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com IN3 SS3 AGND EN1 SS1 DGND SW1 IN1 IS1 19 18 17 16 15 14 13 12 RHL PACKAGE 4.5mm x 3.5mm QFN (TOP VIEW) 20 11 FB1 10 FB2 DGND 2 3 4 5 6 7 8 9 EN3 EN2 SS2 DGND SW2 IN2 IS2 1 FB3 OUT3 TERMINAL FUNCTIONS TERMINAL 6 DESCRIPTION NAME RHL DGND 6, 15, PAD AGND 18 Ground connection for LDO. IN1 13 Input supply to BUCK1. IN2 8 Input supply to BUCK2. IN3 20 Input supply to LDO. EN1 17 Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown mode, reducing operating current. The enable pin does not trigger on fast negative going transients. EN2 4 Same as EN1 but for BUCK2 controller. EN3 3 Same as EN1 but for LDO. SS1 16 Connecting a capacitor between this pin and ground increases start-up time of the BUCK1 regulator by slowing the ramp-up of current limit. This high-impedance pin is noise-sensitive; careful layout is important. See the Typical Characteristics, Applications, and PCB Layout sections for details. SS2 5 Same as SS1 but for BUCK2 regulator. SS3 19 Connecting a capacitor from this pin to ground slows the start-up time of the LDO reference, therby slowing output voltage ramp-up. See the Applications section for details. IS1 12 Current sense input for BUCK1 regulator. The voltage difference between this pin and IN1 is compared to an internal reference to set current limit. For a robust output start-up ramp, careful layout and bypassing are required. See the Applications section for details. IS2 9 Same as IS1 but compared to IN2 and used for BUCK2 controller. SW1 14 Gate drive pin for external BUCK1 P-channel MOSFET. SW2 7 Same as SW1 but for BUCK2 controller. FB1 11 Feedback pin. Used to set the output voltage of BUCK1 regulator. FB2 10 Same as FB1 but for BUCK2 controller. FB3 2 Same as FB1 but for LDO. OUT3 1 Regulated LDO output. A small ceramic capacitor ( 2.2mF) is needed from this pin to ground to ensure stability. Ground connection for BUCK1 and BUCK2 converters. Pins 6 and 15 should be connected to the back side exposed pad by a short metal trace as shown in the PCB Layout section of this data sheet. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA L2 15H Sumida CDRH8D43-150 Q2 EN1 Siliconix Si2323DS 1.5nF 0.01F VCCINT 1.2V, 2A Vishay SS32 D2 100F Tantalum R1 33m IN3 VIN 100F 0.1F 12 IS1 IN1 13 14 SW1 DGND 15 SS1 16 EN1 17 18 19 SS3 AGND VIN 20 FB1 11 1F DGND 9 8 IS2 SW2 IN2 7 6 DGND 4 5 SS2 EN3 EN2 3 R3 61.9k FB2 10 FB3 10F 1 2 OUT3 VCCAUX 2.5V, 300mA VIN R4 15.4k R2 33m 1.5nF Q1 EN3 EN2 R6 36.5k 0.1F 10pF Siliconix Si2323DS R5 61.9k VCCO 3.3V, 2A 100F Tantalum L1 5H Sumida CDRH6D38-5R0 ON Semiconductor MBRM120 Figure 1. TYPICAL CHARACTERISTICS Measured using circuit in Figure 1. Buck Converter BUCK LOAD REGULATION BUCK LOAD REGULATION 5 5 4 VIN = 3.3V VOUT = 1.2V TA = -40_C 3 3 2 2 TA = +85_ C 1 TA = +25_ C 0 -1 VOUT (%) VOUT (%) VIN = 5V VOUT = 3.3V 4 0 -2 -3 -3 -4 -4 -5 TA = -40_ C -1 -2 TA = +85_ C TA = +25_ C 1 -5 0 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 0 Figure 2. 0.5 1.0 1.5 2.0 I OUT (A) 2.5 3.0 3.5 Figure 3. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 7 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 1. BUCK LINE REGULATION BUCK LINE REGULATION 5 5 VOUT = 1.2V IOUT = 2A 4 3 1 0 TA = +85_ C -1 TA = +85_C 1 0 -1 -2 -2 -3 -3 -4 -4 TA = -40_C -5 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 3.0 7.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VIN (V) VIN (V) Figure 4. Figure 5. BUCK SWITCHING FREQUENCY vs IOUT, TA BUCK SWITCHING FREQUENCY vs IOUT 500 600 VOUT = 1.2V 400 VIN = 3.3V 300 200 VIN = 5.0V -40_C 100 +25_C Switching Frequency (kHz) Switching Frequency (kHz) TA = +25_C 2 VOUT (%) VOUT (%) 3 TA = -40_C TA = +25_C 2 VOUT = 3.3V IOUT = 2A 4 500 7.0 VIN = 5.0V VOUT = 3.3V VIN = 2.2V VOUT = 1.2V 400 VIN = 3.3V VOUT = 1.2V 300 200 100 VIN = 5.0V VOUT = 1.2V +85_C 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0.01 0.1 1.0 IOUT (A) 10 IOUT (A) Figure 6. Figure 7. BUCK OUTPUT VOLTAGE RIPPLE EFFICIENCY vs IOUT 100 VIN = 5.0V VOUT = 3.3V IOUT = 2A 90 20mV/div Efficiency (%) 80 VIN = 5.0V VOUT = 3.3V 70 VIN = 5.0V VOUT = 1.2V 60 50 40 VIN = 3.3V 30 VOUT = 1.2V 20 10 0 1s/div 0.0001 0.001 0.01 0.1 1 10 IOUT (A) Figure 8. 8 Figure 9. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 1. BUCK START-UP vs VIN and IOUT (1) BUCK START-UP vs VIN and COUT (1) EN EN VIN = 5V, IOUT = 0.5A VIN = 5V, COUT = 330F VOUT (500mV/div) VOUT (500mV/div) VIN = 5V, I OUT = 1.0A VIN = 3.3V, IOUT = 1.0A VIN = 5V, I OUT = 2.0A VIN = 5V, COUT = 100F VIN = 3.3V, COUT = 680F VIN = 3.3V, COUT = 100F VIN = 3.3V, I OUT = 2.0A CSS = 0.01F VOUT = 1.2V CSS = 0.01F VOUT = 1.2V 20ms/div 20ms/div Figure 10. Figure 11. BUCK START-UP vs VIN and CSS (1) BUCK START-UP vs IOUT and CSS (1) VIN = 3.3V, C SS = 0.001F VIN = 5V VOUT = 3.3V VIN = 5V, CSS = 0.001F IOUT = 2A, CSS = 560pF VOUT (2V/div) VOUT (500mV/div) EN VIN = 5V, CSS = 0.01F VIN = 3.3V, C SS = 0.01F EN I OUT = 0.5A, CSS = 560pF IOUT = 0.5A, CSS = 1500pF IOUT = 1A VOUT = 1.2V I OUT = 2A, CSS = 1500pF 20ms/div 5ms/div Figure 12. Figure 13. BUCK START-UP vs VIN and RSENSE (1) VOUT = 1.2V, CSS = 0.01F VOUT (1V/div) EN VIN = 3.3V, IOUT = 1A, RS = 0.020 VIN = 3.3V, IOUT = 1A, RS = 0.033 VIN = 5V, IOUT = 1A, RS = 0.020 VIN =5V, IOUT = 1A, RS = 0.033 20ms/div Figure 14. (1)xxxSee the section, Soft-Start Capacitor Selection (Buck Controllers) . (1) See the section, Soft-Start Capacitor Selection (Buck Controllers) . Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 9 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 1. LDO Converter LDO LOAD REGULATION LDO LINE REGULATION 5 5 VIN = 3.3V VOUT = 2.5V 4 3 3 2 2 VOUT (%) VOUT (%) VOUT = 2.5V IOUT = 1mA 4 TA = -40_ C 1 0 -1 TA = +25_C -2 0 -1 TA = +85_C -2 TA = +85_C -3 TA = +25_C 1 TA = -40_C -3 -4 -4 -5 -5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 3.0 3.5 4.0 4.5 IOUT (A) 5.5 Figure 15. Figure 16. LDO DROPOUT vs IOUT LDO DROPOUT vs TA 6.0 6.5 7.0 450 500 VIN = 3.3V VOUT = 2.5V TA = +25_C VOUT = 2.5V IOUT = 300mA 400 400 350 TA = +85_C 300 VDO (mV) VDO (mV) 5.0 VIN (V) 300 200 TA = -40_ C 250 200 150 100 100 50 0 0 0 50 100 150 200 250 300 350 400 -40 450 -25 -10 5 Figure 17. 35 50 65 80 85 Figure 18. RDS,ON PMOS vs VIN RDS,ON NMOS vs VIN 12 12 10 10 TA = -40_ C RDS, ON ( ) 8 RDS,ON ( ) 20 Ambient Temperature (_C) I OUT (mA) 6 TA = +25_ C 4 TA = +25_ C 8 TA = +85_ C 6 4 TA = +85_ C 2 2 0 0 TA = -40_C 2.0 10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VIN (V) VIN (V) Figure 19. Figure 20. Submit Documentation Feedback 5.5 6.0 6.5 7.0 Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 1. LDO VOUT vs TA 2.525 VIN = 3.3V 2.520 2.515 VOUT (V) 2.510 2.505 2.500 2.495 2.490 2.485 2.480 2.475 -40 -15 10 35 60 85 Ambient Temperature (_C) Figure 21. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 11 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com APPLICATION INFORMATION The TPS75003 is an integrated power management IC designed specifically to power DSPs and FPGAs such as the Xilinx Spartan-3, Spartan-3E and Spartan-3L. Two non-synchronous buck controllers can be configured to supply up to 3A for both CORE and I/O rails. A low dropout linear regulator powers auxiliary rails up to 300mA. All channels have independent enable and soft-start, allowing control of inrush current and output voltage ramp time as required by the application. Figure 1 shows a typical application circuit for powering the Xilinx Spartan-3 FPGA. Table 1 through Table 4 show component values that have been tested for use with up to 3A load currents. Inductors in Table 1 are tested up to the respective saturation currents. Other similar external components can be substituted as desired; however, in all cases the circuits that are used should be tested for compliance to application requirements. Table 1. Inductors Tested with the TPS75003 PART NUMBER SLF7032T-100M1R4 SLF6025-150MR88 MANUFACTURER INDUCTANCE DC RESISTANCE SATURATION CURRENT TDK 10mH 20% 53m 20% 1.4A TDK 15mH 20% 85m 20% 0.88A CDRH6D28-5R0 Sumida 5mH 23m 2.4A CDRH6D38-5R0 Sumida 5mH 18m 2.9A CDRH103R-100 Sumida 10mH 45m 2.4A CDRH4D28-100 Sumida 10mH 96m 1.0A CDRH8D43-150 Sumida 15mH 42m 2.9A CDRH5D18-6R2 Sumida 6.2mH 71m 1.4A DO3316P-472 Coilcraft 4.7mH 18m 5.4A DT3316P-153 Coilcraft 15mH 60m 1.8A DT3316P-223 Coilcraft 22mH 84m 1.5A 744052006 Wurth 6.2mH 80m 1.45A 74451115 Wurth 15mH 90m 0.8A Table 2. PMOS Transistors Tested with the TPS75003 MANUFACTURER RDS,ON (TYP) VDS ID PACKAGE Si5447DC PART NUMBER Vishay Siliconix 0.11 at VGS = -2.5V -20V -3.5A at +25C 1206 Si5475DC Vishay Siliconix 0.041 at VGS = -2.5V -12V -6.6A at +25C 1206 Si2323DS Vishay Siliconix 0.052 at VGS = -2.5V -20V -4.1A at +25C SOT23 Si2301ADS Vishay Siliconix 0.19 at VGS = -2.5V -20V -1.4A at +25C SOT23 Si2323DS Vishay Siliconix 0.41 at VGS = -2.5V -20V -4.1A at +25C SOT23 FDG326P Fairchild 0.17 at VGS = -2.5V -20V -1.5A SC70 Table 3. Diodes Tested with the TPS75003 PART NUMBER MANUFACTURER VR IF PACKAGE MBRM120LT3 ON Semiconductor 20V 1.0A DO216AA MBR0530T1 ON Semiconductor 30V 1.5A SOD123 Zetex 40V 2.0A SOT23-6 B320 Diodes Inc. 20V 3.0A SMA SS32 Fairchild 20V 3.0A DO214AB ZHCS2000TA 12 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 Table 4. Capacitors Tested with the TPS75003 MANUFACTURER CAPACITANCE ESR VOLTAGE RATING 6TPB47M (PosCap) PART NUMBER Sanyo 47mF 0.1 6.3V T491D476M010AS 10V Kemet 47mF 0.8 B45197A Epco 47mF 0.175 16V B45294-R1107-M40 Epco 100mF 0.045 6.3V 594D476X0016C2 Vishay 47mF 0.11 16V 594D127X96R3C2 Vishay 120mF 0.085 6.3V AVX 100mF 0.15 6.3V Sanyo 100mF 0.45 6.3V TPSC107K006R0150 6TPS100MC OPERATION (BUCK CONTROLLERS) Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum off-time hysteretic control. (Refer to Figure 1.) For clarity, BUCK1 is used throughout the discussion of device operation. When VOUT1 is below its target, an external PMOS (Q1) is turned on for at least the minimum on-time, increasing current through the inductor (L1) until VOUT1 reaches its target value or the current limit (set by R1) is reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on again when necessary. When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node capacitance. This operation is normal; it does not affect circuit performance, and can be minimized if desired by using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22. Q L R D 0.1F f = measured resonant frequency at switch node R = 2fL Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at the switch node and VOUT is equal to VIN times the duty cycle of the switching waveform. When VIN approaches or falls below VOUT, the buck controllers operate in 100% duty cycle mode, fully turning on the external PMOS to allow regulation at lower dropout than would otherwise be possible. Enable (Buck Controllers) The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2, respectively. If the soft-start feature is being used, enable should be driven high at least 10ms after VIN is applied to ensure this discharge cycle occurs. UVLO (Buck Controllers) An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from mis-operation at low input voltages. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 13 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com Current Limit (Buck Controllers) An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an internal reference to determine if an over-current condition exists. When current limit is exceeded, the external PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10ns any time the PMOS is turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled. Current limit is calculated using the VIS1 or VIS2 specification in the Electrical Characteristics section, shown in Equation 1: VIS1,2 I LIMIT + R1,2 (1) The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current calculated by Equation 2: I RMS + I OUT D + I OUT VOUT V IN 2 P DISS + I RMS @ R (2) For low-cost applications the IS1,2 pin can be connected to the drain of the PMOS, using RDS,ON instead of R1 or R2 to set current limit. Variations in the PMOS RDS,ON must be taken into account to ensure that current limit will protect external components such as the inductor, the diode, and the switch itself from damage as a result of over-current. Short-Circuit Protection (Buck Controllers) In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the feedback pin is lower than the reference voltage. When the output is shorted (VFB is zero), minimum off-time is increased to approximately 4ms. The increase in off-time is proportional to the difference between the voltage at the feedback pin and the internal reference. Soft-Start (Buck Controllers) The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. Refer to the soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are very high-impedance and cannot be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low, any charge on the SS pin is discharged by an on-chip pull-down transistor. When EN1 is driven high, an on-chip current source starts charging the external soft-start capacitor CSS1. The voltage on the capacitor is compared to the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the soft-start time over a wide range for most applications. For detailed information on choosing CSS1 and CSS2, see the section, Soft-Start Capacitor Selection (Buck Controllers) . 14 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 IN1 IS1 V IS1 Switch Control SW1 Soft Start Control SS1 EN1 Figure 23. Soft-Start Circuitry VIN Current Limit VSS1 VEN1 Time Figure 24. Soft-Start Timing Diagram Input Capacitor CIN1, CIN2 Selection (Buck Controllers) It is good analog design practice to place input capacitors near the inputs of the device in order to ensure a low impedance input supply. 10mF to 22mF of capacitance for each buck converter is adequate for most applications, and should be placed within 100mils (0.01in, or 2.54mm) of the IN1 and IN2 pins to minimize the effects of pulsed current switching noise on the soft-start circuitry during the first ~1V of output voltage ramp. Low ESR capacitors also help to minimize noise on the supply line. The minimum value of capacitance can be estimated using Equation 3: 2 (12)L 0.3 I OUT (12)L (DI L) C IN, MIN + [ V (RIPPLE) V IN V(RIPPLE) V IN 2 (3) Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 15 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com Note that the capacitors must be able to handle the RMS current in continuous conduction mode, which can be calculated using Equation 4: I C,IN(RMS) [ I OUT VOUT V IN, MIN (4) Inductor Value Selection (Buck Controllers) The inductor is chosen based on inductance value and maximum current rating. Larger inductors reduce current ripple (and therefore, output voltage ripple) but are physically larger and more expensive. Inductors with lower DC resistance typically improve efficiency, but also have higher cost and larger physical size. The buck converters work well with inductor values between 4.7mH and 47mH in most applications. When selecting an inductor, the current rating should exceed the current limit set by RIS or RDS,ON (see the Current Limit section). To determine the minimum inductor size, first determine if the device will operate in minimum on-time or minimum off-time mode. The device will operate in minimum on-time mode if Equation 5 is satisfied: V IN*VOUT*I OUT r DS(on)*R L I OUT w t (OFF,min) VOUT)V SCHOTTKY)R L I OUT t ON, MIN (5) where RL = the inductor DC resistance. Minimum inductor size needed when operating in minimum on-time mode is given by Equation 6: L MIN + VIN*V OUT*I OUT r DS(on)*RL I OUT t ON, MIN DI L (6) Minimum inductor size needed when operating in minimum off-time mode is given by Equation 7: VOUT)V SCHOTTKY)R L I OUT t OFF, MIN L MIN + DI L (7) where IL = (20%-30%) x IOUT-MAX External PMOS Transistor Selection (Buck Controllers) The external PMOS transistor is selected based on threshold voltage (VT), on-resistance (RDS,ON), gate capacitance (CG) and voltage rating. The PMOS VT magnitude must be much lower than the lowest voltage at IN1 or IN2 that will be used. A VT magnitude that is 0.5V less than the lowest input voltage is normally sufficient. The PMOS gate will see voltages from 0V to the maximum input voltage, so gate-to-source breakdown should be a few volts higher than the maximum input supply. The drain-to-source of the device will also see this full voltage swing, and should therefore be a few volts higher than the maximum input supply. The RMS current in the PMOS can be estimated by using Equation 8: I PMOS(RMS) [ I OUT D + I OUT VOUT V IN (8) The power dissipated in the PMOS is comprised of both conduction and switching losses. Switching losses are typically insignificant. The conduction losses are a function of the RMS current and the RDS,ON of the PMOS, and are calculated by Equation 9: 2 P (cond) + I OUT D 16 r DS(on) 1)TC T J*25C [ I OUT D rDS(on) Submit Documentation Feedback (9) Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 Diode Selection (Buck Controllers) The diode is off when the PMOS is on, and on when the PMOS is off. Since it will be turned on and off at a relatively high frequency, a Schottky diode is recommended for good performance. The peak current rating of the diode should exceed the peak current limit set by the sense resistor RIS1,2. A diode with low reverse leakage current and low forward voltage at operating current will optimize efficiency. Equation 10 calculates the estimated average power dissipation: I (diode)(RMS) [ I OUT(1*D) + I OUT 1* V OUT V IN (10) Output Capacitor Selection (Buck Controllers) The output capacitor is selected based on output voltage ripple and transient response requirements. As a result of the nature of the hysteretic control loop, a minimum ESR of a few tens of m should be maintained for good operation unless a feed-forward resistor is used. Low ESR bulk tantalum or PosCap capacitors work best in most applications. A 1.0mF ceramic capacitor can be used in parallel with this capacitor to filter higher frequency spikes. The output voltage ripple can be estimated by Equation 11: DV PP + DI ESR) 8 1 COUT f [ 1.1DI ESR (11) To calculate the capacitance needed to achieve a given voltage ripple as a result of a load transient from zero output to full current, use Equation 12: C OUT + L DI OUT VIN*V OUT 2 DV (12) If only ceramic or other very low ESR output capacitor configurations are desired, additional voltage ripple must be passed to the feedback pin. See Application Note SLVA210, Using Ceramic Output Capacitors with the TPS6420x and TPS75003 Buck Controllers, available for download at www.ti.com, for detailed application information. Output Voltage Ripple Effect on VOUT (Buck Controllers) Output voltage ripple causes VOUT to be higher or lower than the target value by half of the peak-to-peak voltage ripple. For minimum on-time, the ripple adds to the voltage; for minimum off-time, it subtracts from the voltage. Soft-Start Capacitor Selection (Buck Controllers) The soft-start for BUCK1 and BUCK2 is not intended to be a precision function. However, the startup time (from a positive transition on Enable to VOUT reaching its final value) has a linear relationship to CSS up to approximately 800pF, which results in a startup time of approximately 4ms. Above this value of CSS, the variation in start-up time increases rapidly. This variation can occur from unit to unit and even between the two BUCK controllers in one device. Therefore, do not depend on the soft-start feature for sequencing multiple supplies if values of CSS greater than 800pF are used. BUCK1 is discussed in this section; it is identical to BUCK2. Soft-start is implemented on the buck controllers by ramping current limit from 0 to its target value (set by R1) over a user-defined time. This time is set by the external soft-start cap connected to pin SS1. If SS1 is left open, a small on-chip capacitor will provide a current limit ramp time of approximately 250ms. Figure 25 shows the effects of R1 and SS1 on the current limit start-up ramp. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 17 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 3.0A www.ti.com R1 = 33m CSS1 = 0.01F CSS1 = 0.022F Current Limit R1 = 143m 0.7A C SS1 = 0.022F CSS1 = 0.01F Time Figure 25. Effects of CSS1 and R1 on Current Ramp Limit This soft-start current limit ramp can be used to provide inrush current control or output voltage ramp control. While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a complex function of many variables. The dominant variables in this process are VOUT1, CSS1, IOUT1, and R1. Less important variables are VIN1 and L1. The best way to set a target start-up time is through bench measurement under target conditions, adjusting CSS1 to get the desired startup profile. To stay above a minimum start-up time, set the nominal start-up time to approximately five times the minimum. To stay below a maximum time, set the nominal start-up time at one-fifth of the maximum. Fastest start-up times occur at maximum VIN1, with minimum VOUT1, L1, COUT1, CSS1, and IOUT1. Slowest start-up times occur under opposite conditions. Refer to Figure 10 to Figure 14 for characterization curves showing how the start-up profile is affected by these critical parameters. Output Voltage Setting Selection (Buck Controllers) Output voltage is set using two resistors as shown for Buck2 in Figure 1. Output voltage is then calculated using Equation 13: V OUT + VFB RR )1 5 6 (13) where VFB = 1.22V. LDO OPERATION The TPS75003 LDO uses a PMOS pass element and is offered in an adjustable version for ease of programming to any output voltage. When used to power VCC,AUX it is set to 2.5V; it can optionally be set to other output voltages to power other circuitry. The LDO has integrated soft-start, independent enable, and short-circuit and thermal protection. The LDO can be used to power VCC,AUX on the Xilinx Spartan-3 FPGA when 3.3V JTAG signals are used as described in Application Note SLVA159 (available for download from www.ti.com). Input Capacitor Selection (LDO) Although an input capacitor is not required, it is good analog design practice to connect a 0.1mF to 10mF low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, stability, and ripple rejection. A higher value capacitor may be needed if large, fast rise-time load transients are anticipated, or if the device is located far from its power source. 18 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 Output Capacitor Selection (LDO) A 2.2mF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or lower ESR output capacitors can be used. Soft-Start (LDO) The LDO uses an external soft-start capacitor, CSS3, to provide an RC-ramped reference voltage to the control loop. (See the Functional Block Diagram.) This is a voltage-controlled soft-start, as compared to the current-controlled soft-start used by the buck controllers. The start-up waveform can be approximated by Equation 14: t V OUT t + V OUT,SET 1 * e *RC (14) 3 where R = 480 x 10 and C = capacitance in mF from SS3 to GND. The time taken to reach 90% of final VOUT can be approximated by Equation 15: T 90% + 2.3 @ 480x10 3 @ CSS3 (mF) (15) Setting Output Voltage (LDO) Output voltage is set using two resistors as shown in Figure 1. Output voltage is then calculated using Equation 16: V OUT + VFB RR )1 3 4 (16) where VFB = 0.507V. Internal Current Limit (LDO) The internal current limit of the LDO helps protect the regulator during fault conditions. When an over-current condition is detected, the output voltage will be reduced until the current falls to a level that will not damage the device. For good device reliability, the LDO should not operate at current limit. Enable Pin (LDO) The active high enable pin (EN3) can be used to put the device into shutdown mode. If shutdown and soft-start capability are not required, EN3 can be tied to IN3. Dropout Voltage (LDO) The LDO uses a PMOS transistor to achieve low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the pass device is in its linear region of operation, and the input-output resistance is the RDS,ON of the pass transistor. In this region, the regulator is said to be out of regulation; ripple rejection, line regulation, and load regulation degrade as (VIN - VOUT) falls much below 0.5V. Transient Response (LDO) The LDO does not have an on-chip pull-down circuit for output is over-voltage conditions. This feature permits applications that connect higher voltage sources such as an alternate power supply to the output. This design also results in an output overshoot of several percent if the load current quickly drops to zero. The amplitude of overshoot can be reduced by increasing COUT; the duration of overshoot can be reduced by adding a load resistor. Thermal Protection (LDO) Thermal protection disables the output when the junction temperature, TJ, reaches unsafe levels. When the junction cools, the output is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage. For good long term reliability, the device should not be continuously operated at or near thermal shutdown. Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 19 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 www.ti.com Power Dissipation (LDO) The TPS75003 comes in a QFN-style package with an exposed lead frame on the package underside. The exposed lead frame is the primary path for removing heat and should be soldered to a PC board that is configured to remove the amount of power dissipated by the LDO, as calculated by Equation 17: P D + VIN3*V OUT3 I OUT3 (17) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. The two buck converters do not contribute a significant amount of dissipated power. Using heavier copper will increase the overall effectiveness of removing heat from the device. The addition of plated through-holes to heat-dissipating layers will also improve the heatsink effectiveness. PCB Layout Considerations As with any switching regulators, careful attention must be paid to board layout. A typical application circuit and corresponding recommended printed circuit board (PCB) layout with emphasis on the most sensitive areas are shown in Figure 26 through Figure 28. L2 VOUT1 EN1 Q2 C13, C15 D2 C3, C17 C7 R5 IN3 VIN C1 C9 12 IS1 IN1 13 SW1 14 DGND 15 SS1 16 17 EN1 AGND 18 19 SS3 VIN 20 11 FB1 C6 DGND R9 9 8 7 6 5 4 3 FB2 R8 IS2 IN2 SW2 DGND SS2 EN2 C10 EN3 R6 10 FB3 C14 1 2 OUT3 VOUT3 VIN C5, C18 R7 C8 R4 Q1 EN3 EN2 VOUT2 L1 D1 Note: C12, C16 Most sensitive areas are highlighted by bold lines. Figure 26. Typical Application Circuit 20 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com Note: SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 Most sensitive areas are highlighted in green. Figure 27. Recommended PCB Layout, Component Side, Top View Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 21 TPS75003 SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 Note: www.ti.com Most sensitive areas are highlighted in green. Figure 28. Recommended PCB Layout, Bottom Side, Top View 22 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 TPS75003 www.ti.com SBVS052I - OCTOBER 2004 - REVISED AUGUST 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (August, 2008) to Revision I * Page Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 2 Submit Documentation Feedback Copyright (c) 2004-2010, Texas Instruments Incorporated Product Folder Link(s): TPS75003 23 PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS75003RHLR ACTIVE QFN RHL 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS75003RHLRG4 ACTIVE QFN RHL 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS75003RHLT ACTIVE QFN RHL 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TPS75003RHLTG4 ACTIVE QFN RHL 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TPS75003 : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 13-Jul-2010 * Enhanced Product: TPS75003-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS75003RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 TPS75003RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS75003RHLR QFN RHL 20 3000 367.0 367.0 35.0 TPS75003RHLT QFN RHL 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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