IN1
IN2
IN3
EN 1
SS1
EN 2
SS2
EN 3
IS1
SW 1
FB 1
IS2
SW 2
FB 2
OU T3
FB 3
DG ND
3A
BU CK 1
3A
BU CK 2
300m A
LD O
SS3
DGND
AG ND
DGND
TPS75003
+
+
VCCAUX
2.5Vat300mA
VCCO
3.3Vat3A
VCCINT
1.2Vat3A
VCCAUX
5V _Input
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Triple-Supply Power Management IC
for Powering FPGAs and DSPs
Check for Samples: TPS75003
1FEATURES DESCRIPTION
23• Two 95% Efficient, 3A Buck Controllers and The TPS75003 is a complete power management
One 300mA LDO solution for FPGA, DSP and other multi-supply
applications. The device has been tested with and
• Tested and Endorsed by Xilinx for Powering meets all of the Xilinx Spartan-3, Spartan-3E and
the Spartan™-3, Spartan-3E and Spartan-3L Spartan-3L start-up profile requirements, including
FPGAs monotonic voltage ramp and minimum voltage rail
• Adjustable (1.2V to 6.5V for Bucks, 1.0V to rise time. Independent Enables for each output allow
6.5V for LDO) Output Voltages on All Channels sequencing to minimize demand on the power supply
at start-up. Soft-start on each supply limits inrush
• Input Voltage Range: 2.2V to 6.5V current during start-up. Two integrated buck
• Independent Soft-Start for Each Supply controllers allow efficient, cost-effective voltage
• Independent Enable for Each Supply for conversion for both low and high current supplies
Flexible Sequencing such as core and I/O. A 300mA LDO is integrated to
provide an auxiliary rail such as VCCAUX on the Xilinx
• LDO Stable with 2.2mF Ceramic Output Cap Spartan-3 FPGA. All three supply voltages are
• Small, Low-Profile 4.5mm x 3.5mm x 0.9mm offered in user-programmable options for maximum
QFN Package flexibility.
The TPS75003 is fully specified from –40°C to +85°C
APPLICATIONS and is offered in a QFN package, yielding a highly
• FPGA/DSP/ASIC Supplies compact total solution size with high power
• Set-Top Boxes dissipation capability.
• DSL Modems
• Plasma TV Display Panels
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Spartan is a trademark of Xilinx, Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT
Buck1: Adjustable
TPS75003 Buck2: Adjustable
LDO: Adjustable
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document, or
see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)(1)
TPS75003 UNIT
VINX range (IN1, IN2, IN3) –0.3 to +7.0 V
VENX range (EN1, EN2, EN3) –0.3 to VINX +0.3 V
VSWX range (SW1, SW2, SW3) –0.3 to VINX +0.3 V
VISX range (IS1, IS2, IS3) –0.3 to VINX +0.3 V
VOUT3 range –0.3 to +7.0 V
VSSX range (SS1, SS2, SS3) –0.3 to VINX +0.3 V
VFBX range (FB1, FB2, FB3) –0.3 to +3.3 V
Peak LDO output current (IOUT3) Internally limited —
Continuous total power dissipation See Dissipation Ratings Table —
Junction temperature range, TJ–55 to +150 °C
Storage temperature range –65 to +150 °C
ESD rating, HBM 1 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION TPS75003
THERMAL METRIC(1)(2) UNITS
RHL (20 PINS)
qJA Junction-to-ambient thermal resistance 42.6
qJCtop Junction-to-case (top) thermal resistance 51.8
qJB Junction-to-board thermal resistance 39.5 °C/W
yJT Junction-to-top characterization parameter 0.6
yJB Junction-to-board characterization parameter 14.2
qJCbot Junction-to-case (bottom) thermal resistance 2.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
2Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2V, VIN3 = 3.0V, VOUT3 = 2.5V, COUT1 = COUT2 = 47mF, COUT3 = 2.2mF,
TA= –40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Supply and Logic
Input Voltage Range
VINX 2.2 6.5 V
(IN1, IN2, IN3)(1)
Quiescent Current, IQ= IDGND +
IQIOUT1 = IOUT2 = 0mA, IOUT3 = 1mA 75 150 mA
IAGND
ISHDN Shutdown Supply Current VEN1 = VEN2 = VEN3 = 0V 0.05 3.0 mA
Enable High, enabled
VIH1, 2 1.4 VINX V
(EN1, EN2)
VIH3 Enable High, enabled (EN3) 1.14 VIN3 V
Enable Low, shutdown
VILX 0 0.3 V
(EN1, EN2, EN3)
Enable pin current
IENX 0.01 0.5 mA
(EN1, EN2, EN3)
Buck Controllers 1 and 2
Adjustable Output Voltage
VOUT1,2 VFBX VINX V
Range(2)
VFB1,2 Feedback Voltage (FB1, FB2) 1.220 V
Feedback Voltage Accuracy(1) –2 +2 %
(FB1, FB2)
IFB1,2 Current into FB1, FB2 pins 0.01 0.5 mA
Reference Voltage for Current
VIS1,2 80 100 120 mV
Sense
IIS1,2 Current into IS1, IS2 Pins 0.01 0.5 mA
Measured with the circuit in Figure 1,
ΔVOUT%/ΔVIN Line Regulation(1) 0.1 % / V
VOUT + 0.5V ≤VIN ≤6.5V
ΔVOUT%/ΔIOU Measured with the circuit in Figure 1,
Load Regulation 0.6 % / A
T30mA ≤IOUT ≤2A
Measured with the circuit in Figure 1,
n1,2 Efficiency(3) 94 %
IOUT = 1A
Measured with the circuit in Figure 1,
tSTR1,2 Startup Time(3) 5 ms
RL= 6Ω, COUT = 100mF, CSS = 2.2nF
Gate Driver P-Channel and VIN1,2 > 2.5V 4
RDS,ON1,2 N-Channel MOSFET Ω
VIN1,2 = 2.2V 6
On-Resistance
Gate Driver P-Channel and
ISW1,2 N-Channel MOSFET Drive 100 mA
Current
tON Minimum On Time 1.36 1.55 1.84 ms
tOFF Minimum Off Time 0.44 0.65 0.86 ms
(1) To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external
components. Minimum VIN3 = VOUT3 + VDO or 2.2V, whichever is greater.
(2) Maximum VOUT depends on external components and will be less than VIN.
(3) Depends on external components.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS75003
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2V, VIN3 = 3.0V, VOUT3 = 2.5V, COUT1 = COUT2 = 47mF, COUT3 = 2.2mF,
TA= –40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.
PARAMETER CONDITIONS MIN TYP MAX UNIT
LDO
VOUT3 Output Voltage Range 1.0 6.5 – VDO V
VFB3 Feedback Pin Voltage 0.507 V
Feedback Pin Voltage 2.95V ≤VIN3 ≤6.5V –4.0 +4.0 %
Accuracy(4) 1mA ≤IOUT3 ≤300mA
ΔVOUT%/ΔVIN Line Regulation(4) VOUT3 + 0.5V ≤VIN3 ≤6.5V 0.075 % / V
ΔVOUT%/ΔIOU Load Regulation 10mA ≤IOUT3 ≤300mA 0.01 % / mA
TDropout Voltage
VDO IOUT3 = 300mA 250 350 mV
(VIN = VOUT(NOM) – 0.1)(5)
ICL3 Current Limit VOUT = 0.9 x VOUT(NOM) 375 600 1000 mA
IFB3 Current into FB3 pin 0.03 0.1 mA
BW = 100Hz – 100kHz,
VnOutput Noise 400 mVRMS
IOUT3 = 300mA
Shutdown, Temp Increasing 175
Thermal Shutdown Temperature
tSD °C
for LDO Reset, Temp Decreasing 160
Under-Voltage Lockout Threshold VIN Rising 1.80 V
UVLO Under-Voltage Lockout VIN Falling 100 mV
Hysteresis
(4) To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external
components. Minimum VIN3 = VOUT3 + VDO or 2.2V, whichever is greater.
(5) VDO does not apply when VOUT + VDO < 2.2V.
4Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
VREF1
Soft
Start
Control
Switch
Control
VIS1 IS1
SW1
FB1
EN1
SS1
IN1 ≤3A Buck Controller
DGND
VREF2
Soft
Start
Control
Switch
Control
VIS2 IS2
SW2
FB2
EN2
SS2
IN2 ≤3A Buck Controller
DGND
FB3
OUT3IN3
EN3
SS3
Thermal/
Current
Limit
300mA LDO
VREF3
AGND
TPS75003
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
DEVICE INFORMATION
Functional Block Diagram
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS75003
IN3
OUT3
FB1
FB2
20
1
11
10
DGND
SS3
AGND
EN1
SS1
DGND
SW1
IN1
IS1
19
18
17
16
15
14
13
12
FB3
EN3
EN2
SS2
DGND
SW2
IN2
IS2
2
3
4
5
6
7
8
9
RHL PACKAGE
4.5mm x 3.5mm QFN
(TOP VIEW)
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
TERMINAL FUNCTIONS
TERMINAL DESCRIPTION
NAME RHL
Ground connection for BUCK1 and BUCK2 converters. Pins 6 and 15 should be connected to the back
DGND 6, 15, PAD side exposed pad by a short metal trace as shown in the PCB Layout section of this data sheet.
AGND 18 Ground connection for LDO.
IN1 13 Input supply to BUCK1.
IN2 8 Input supply to BUCK2.
IN3 20 Input supply to LDO.
Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown
EN1 17 mode, reducing operating current. The enable pin does not trigger on fast negative going transients.
EN2 4 Same as EN1 but for BUCK2 controller.
EN3 3 Same as EN1 but for LDO.
Connecting a capacitor between this pin and ground increases start-up time of the BUCK1 regulator by
SS1 16 slowing the ramp-up of current limit. This high-impedance pin is noise-sensitive; careful layout is
important. See the Typical Characteristics, Applications, and PCB Layout sections for details.
SS2 5 Same as SS1 but for BUCK2 regulator.
Connecting a capacitor from this pin to ground slows the start-up time of the LDO reference, therby
SS3 19 slowing output voltage ramp-up. See the Applications section for details.
Current sense input for BUCK1 regulator. The voltage difference between this pin and IN1 is compared
IS1 12 to an internal reference to set current limit. For a robust output start-up ramp, careful layout and
bypassing are required. See the Applications section for details.
IS2 9 Same as IS1 but compared to IN2 and used for BUCK2 controller.
SW1 14 Gate drive pin for external BUCK1 P-channel MOSFET.
SW2 7 Same as SW1 but for BUCK2 controller.
FB1 11 Feedback pin. Used to set the output voltage of BUCK1 regulator.
FB2 10 Same as FB1 but for BUCK2 controller.
FB3 2 Same as FB1 but for LDO.
Regulated LDO output. A small ceramic capacitor (≥2.2mF) is needed from this pin to ground to ensure
OUT3 1 stability.
6Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
L1
5µH
Sumida
CDRH6D38−5R0
IN3
OUT3
FB1
FB2
20
1
11
10
DGND
SS3
AGND
EN1
SS1
DGND
SW1
IN1
IS1
19
18
17
16
15
14
13
12
FB3
EN3
EN2
SS2
DGND
SW2
IN2
IS2
2
3
4
5
6
7
8
9
R3
61.9kΩ
R4
15.4kΩ
EN3
EN2
VIN
EN1
VIN
1.5nF
1.5nF
0.01µFR1
33mΩ
10pF
100µF
Tantalum
100µF
Tantalum
Siliconix
Si2323DS
Siliconix
Si2323DS
Q2
L2
15µH
Sumida
CDRH8D43−150 VCCINT
1.2V, 2A
Vishay
SS32
D2
0.1µF
1µF
VCCAUX
2.5V, 300mA
10µF
0.1µF
R5
61.9kΩ
ON Semiconductor
MBRM120
R6
36.5kΩ
VCCO
3.3V, 2A
R2
33mΩ
100µF
VIN
Q1
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
IOUT (A)
VIN = 3.3V
VOUT = 1.2V
TA= +85_C
TA=−40_C
TA= +25_C
5
4
3
2
1
0
−1
−2
−3
−4
−5
∆VOUT (%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
IOUT (A)
VIN = 5V
VOUT = 3.3V
5
4
3
2
1
0
−1
−2
−3
−4
−5
∆VOUT (%)
TA= +85_C
TA=−40_C
TA= +25_C
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA
Figure 1.
TYPICAL CHARACTERISTICS
Measured using circuit in Figure 1.
Buck ConverterBUCK LOAD REGULATION BUCK LOAD REGULATION
Figure 2. Figure 3.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS75003
3.0 VIN (V)
5
4
3
2
1
0
−1
−2
−3
−4
−5
∆VOUT (%)
VOUT = 3.3V
IOUT = 2A
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
TA= +85_C
TA= +25_C
TA=−40_C
2.0 VIN (V)
5
4
3
2
1
0
−1
−2
−3
−4
−5
∆VOUT (%)
VOUT = 1.2V
IOUT = 2A
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
TA=−40_C
TA= +25_C
TA= +85_C
600
500
400
300
200
100
0
Switching Frequency(kHz)
0.01 0.1 1.0 10
IOUT (A)
VIN = 5.0V
VOUT = 1.2V
VIN = 3.3V
VOUT = 1.2V
VIN = 5.0V
VOUT = 3.3V
VOUT = 1.2V
VIN = 2.2V
1µs/div
VIN = 5.0V
VOUT = 3.3V
IOUT = 2A
20mV/div
100
90
80
70
60
50
40
30
20
10
0
Efficiency (%)
0.0001 0.001 0.01 0.1 1 10
IOUT (A)
VIN = 5.0V
VOUT = 3.3V
VIN = 3.3V
VOUT = 1.2V
VIN = 5.0V
VOUT = 1.2V
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 1.
BUCK LINE REGULATION BUCK LINE REGULATION
Figure 4. Figure 5.
BUCK SWITCHING FREQUENCY BUCK SWITCHING FREQUENCY
vs vs
IOUT, TAIOUT
Figure 6. Figure 7.
EFFICIENCY vs
BUCK OUTPUT VOLTAGE RIPPLE IOUT
Figure 8. Figure 9.
8Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
EN
VIN = 5V, COUT = 330µF
VIN = 5V, COUT = 100µF
VIN = 3.3V, COUT = 680µF
VIN = 3.3V, COUT = 100µF
CSS = 0.01µF
VOUT = 1.2V
20ms/div
VOUT (500mV/div)
EN VIN = 5V, IOUT = 0.5A
VIN = 5V, IOUT = 1.0A
VIN = 5V, IOUT = 2.0A
VIN = 3.3V, IOUT = 1.0A
CSS = 0.01µF
VOUT = 1.2V
20ms/div
VOUT (500mV/div)
VIN = 3.3V, IOUT = 2.0A
EN VIN = 3.3V, CSS = 0.001µF
VIN = 5V, CSS = 0.001µF
VIN = 5V, CSS = 0.01µF
VIN = 3.3V, CSS = 0.01µF
IOUT = 1A
VOUT = 1.2V
20ms/div
VOUT (500mV/div)
EN
IOUT = 2A,
CSS = 560pF
IOUT = 0.5A,
CSS = 560pF
IOUT = 0.5A, CSS = 1500pF
IOUT = 2A, CSS = 1500pF
VIN = 5V
VOUT = 3.3V
5ms/div
VOUT (2V/div)
EN VIN = 3.3V,
IOUT = 1A,
RS= 0.020
VIN =5V, IOUT = 1A,
RS= 0.033
VIN = 3.3V,
IOUT = 1A,
RS= 0.033
VIN = 5V,
IOUT = 1A,
RS= 0.020
VOUT = 1.2V, CSS = 0.01µF
20ms/div
VOUT (1V/div)
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 1.
BUCK START-UP BUCK START-UP
vs vs
VIN and IOUT (1) VIN and COUT (1)
Figure 10. Figure 11.
BUCK START-UP BUCK START-UP
vs vs
VIN and CSS (1) IOUT and CSS (1)
Figure 12. Figure 13.
BUCK START-UP
vs
VIN and RSENSE (1)
Figure 14.
(1)xxxSee the section, Soft-Start Capacitor Selection (Buck Controllers) .
(1) See the section, Soft-Start Capacitor Selection (Buck Controllers) .
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS75003
∆VOUT (%)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
5
4
3
2
1
0
−1
−2
−3
−4
−5
IOUT (A)
VIN = 3.3V
VOUT = 2.5V
TA= +25_C
TA= +85_C
TA=−40_C
∆VOUT (%)
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VIN (V)
VOUT = 2.5V
IOUT = 1mA
TA= +85_C
5
4
3
2
1
0
−1
−2
−3
−4
−5
TA= +25_C
TA=−40_C
450
400
350
300
250
200
150
100
50
0
VDO(mV)
Ambient Temperature (_C)
−40 −25 −10 5 20 35 50 65 8580
VOUT = 2.5V
IOUT = 300mA
500
400
300
200
100
0
VDO (mV)
0 50 100 150 200 250 300 350 400 450
IOUT (mA)
TA=−40_C
TA= +25_C
TA= +85_C
VIN = 3.3V
VOUT = 2.5V
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
12
10
8
6
4
2
0
RDS,ON (Ω)
VIN (V)
TA=−40_C
TA= +25_C
TA= +85_C
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
12
10
8
6
4
2
0
RDS, ON (Ω)
VIN (V)
TA=−40_C
TA= +25_C
TA= +85_C
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 1.
LDO Converter LDO LOAD REGULATION LDO LINE REGULATION
Figure 15. Figure 16.
LDO DROPOUT LDO DROPOUT
vs vs
IOUT TA
Figure 17. Figure 18.
RDS,ON PMOS vs VIN RDS,ON NMOS vs VIN
Figure 19. Figure 20.
10 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
2.525
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
2.475
VOUT (V)
−40 −15 10 35 60 85
Ambient Temperature (_C)
VIN = 3.3V
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 1.LDO VOUT
vs
TA
Figure 21.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS75003
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
APPLICATION INFORMATION
The TPS75003 is an integrated power management IC designed specifically to power DSPs and FPGAs such as
the Xilinx Spartan-3, Spartan-3E and Spartan-3L. Two non-synchronous buck controllers can be configured to
supply up to 3A for both CORE and I/O rails. A low dropout linear regulator powers auxiliary rails up to 300mA.
All channels have independent enable and soft-start, allowing control of inrush current and output voltage ramp
time as required by the application.
Figure 1 shows a typical application circuit for powering the Xilinx Spartan-3 FPGA. Table 1 through Table 4
show component values that have been tested for use with up to 3A load currents. Inductors in Table 1 are
tested up to the respective saturation currents. Other similar external components can be substituted as desired;
however, in all cases the circuits that are used should be tested for compliance to application requirements.
Table 1. Inductors Tested with the TPS75003
PART NUMBER MANUFACTURER INDUCTANCE DC RESISTANCE SATURATION CURRENT
SLF7032T−100M1R4 TDK 10mH ±20% 53mΩ±20% 1.4A
SLF6025−150MR88 TDK 15mH ±20% 85mΩ±20% 0.88A
CDRH6D28−5R0 Sumida 5mH 23mΩ2.4A
CDRH6D38-5R0 Sumida 5mH 18mΩ2.9A
CDRH103R−100 Sumida 10mH 45mΩ2.4A
CDRH4D28−100 Sumida 10mH 96mΩ1.0A
CDRH8D43-150 Sumida 15mH 42mΩ2.9A
CDRH5D18−6R2 Sumida 6.2mH 71mΩ1.4A
DO3316P−472 Coilcraft 4.7mH 18mΩ5.4A
DT3316P−153 Coilcraft 15mH 60mΩ1.8A
DT3316P−223 Coilcraft 22mH 84mΩ1.5A
744052006 Wurth 6.2mH 80mΩ1.45A
74451115 Wurth 15mH 90mΩ0.8A
Table 2. PMOS Transistors Tested with the TPS75003
PART NUMBER MANUFACTURER RDS,ON (TYP) VDS IDPACKAGE
Si5447DC Vishay Siliconix 0.11Ωat VGS = –2.5V –20V –3.5A at +25°C 1206
Si5475DC Vishay Siliconix 0.041Ωat VGS = –2.5V –12V –6.6A at +25°C 1206
Si2323DS Vishay Siliconix 0.052Ωat VGS = –2.5V –20V –4.1A at +25°C SOT23
Si2301ADS Vishay Siliconix 0.19Ωat VGS = –2.5V –20V –1.4A at +25°C SOT23
Si2323DS Vishay Siliconix 0.41Ωat VGS = –2.5V –20V –4.1A at +25°C SOT23
FDG326P Fairchild 0.17Ωat VGS = –2.5V –20V –1.5A SC70
Table 3. Diodes Tested with the TPS75003
PART NUMBER MANUFACTURER VRIFPACKAGE
MBRM120LT3 ON Semiconductor 20V 1.0A DO216AA
MBR0530T1 ON Semiconductor 30V 1.5A SOD123
ZHCS2000TA Zetex 40V 2.0A SOT23−6
B320 Diodes Inc. 20V 3.0A SMA
SS32 Fairchild 20V 3.0A DO214AB
12 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
0.1µF
RD
Q L
f = measured resonant
frequency at switch node
R = 2πfL
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Table 4. Capacitors Tested with the TPS75003
PART NUMBER MANUFACTURER CAPACITANCE ESR VOLTAGE RATING
6TPB47M (PosCap) Sanyo 47mF 0.1Ω6.3V
T491D476M010AS Kemet 47mF 0.8Ω10V
B45197A Epco 47mF 0.175Ω16V
B45294−R1107−M40 Epco 100mF 0.045Ω6.3V
594D476X0016C2 Vishay 47mF 0.11Ω16V
594D127X96R3C2 Vishay 120mF 0.085Ω6.3V
TPSC107K006R0150 AVX 100mF 0.15Ω6.3V
6TPS100MC Sanyo 100mF 0.45Ω6.3V
OPERATION (BUCK CONTROLLERS)
Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum
off-time hysteretic control. (Refer to Figure 1.) For clarity, BUCK1 is used throughout the discussion of device
operation. When VOUT1 is below its target, an external PMOS (Q1) is turned on for at least the minimum on-time,
increasing current through the inductor (L1) until VOUT1 reaches its target value or the current limit (set by R1) is
reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of
the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on
again when necessary.
When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching
cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current
reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node
capacitance. This operation is normal; it does not affect circuit performance, and can be minimized if desired by
using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22.
Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing
At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at
the switch node and VOUT is equal to VIN times the duty cycle of the switching waveform.
When VIN approaches or falls below VOUT, the buck controllers operate in 100% duty cycle mode, fully turning on
the external PMOS to allow regulation at lower dropout than would otherwise be possible.
Enable (Buck Controllers)
The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and
input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2,
respectively. If the soft-start feature is being used, enable should be driven high at least 10ms after VIN is applied
to ensure this discharge cycle occurs.
UVLO (Buck Controllers)
An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable
operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from
mis-operation at low input voltages.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS75003
ILIMIT +VIS1,2
R1,2
IRMS +IOUT D
Ǹ+IOUT VOUT
VIN
Ǹ
PDISS +ǒIRMSǓ2@R
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
Current Limit (Buck Controllers)
An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These
resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins
that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an
internal reference to determine if an over-current condition exists. When current limit is exceeded, the external
PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10ns any time the PMOS is
turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled.
Current limit is calculated using the VIS1 or VIS2 specification in the Electrical Characteristics section, shown in
Equation 1:
(1)
The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current
calculated by Equation 2:
(2)
For low-cost applications the IS1,2 pin can be connected to the drain of the PMOS, using RDS,ON instead of R1 or
R2 to set current limit. Variations in the PMOS RDS,ON must be taken into account to ensure that current limit will
protect external components such as the inductor, the diode, and the switch itself from damage as a result of
over-current.
Short-Circuit Protection (Buck Controllers)
In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be
exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the
feedback pin is lower than the reference voltage. When the output is shorted (VFB is zero), minimum off-time is
increased to approximately 4ms. The increase in off-time is proportional to the difference between the voltage at
the feedback pin and the internal reference.
Soft-Start (Buck Controllers)
The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing
requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the
turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. Refer
to the soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be
discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are very high-impedance and
cannot be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low,
any charge on the SS pin is discharged by an on-chip pull-down transistor. When EN1 is driven high, an on-chip
current source starts charging the external soft-start capacitor CSS1. The voltage on the capacitor is compared to
the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage
drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the
minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the
soft-start time over a wide range for most applications. For detailed information on choosing CSS1 and CSS2, see
the section, Soft-Start Capacitor Selection (Buck Controllers) .
14 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
Soft
Start
Control
Switch
Control
VIS1
EN1
SW1
IS1
IN1
SS1
VIN
Current
Limit
VSS1
VEN1
Time
CIN,MIN +(1ń2)L (DIL)2
V(RIPPLE) VIN [(1ń2)L ǒ0.3 IOUTǓ2
V(RIPPLE) VIN
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Figure 23. Soft-Start Circuitry
Figure 24. Soft-Start Timing Diagram
Input Capacitor CIN1, CIN2 Selection (Buck Controllers)
It is good analog design practice to place input capacitors near the inputs of the device in order to ensure a low
impedance input supply. 10mF to 22mF of capacitance for each buck converter is adequate for most applications,
and should be placed within 100mils (0.01in, or 2.54mm) of the IN1 and IN2 pins to minimize the effects of
pulsed current switching noise on the soft-start circuitry during the first ~1V of output voltage ramp. Low ESR
capacitors also help to minimize noise on the supply line. The minimum value of capacitance can be estimated
using Equation 3:
(3)
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS75003
IC,IN(RMS) [IOUT ǒVOUT
VIN,MINǓ
Ǹ
VIN*VOUT*IOUT rDS(on)*RL IOUT wt(OFF,min) ǒVOUT)VSCHOTTKY)RL IOUTǓ
tON,MIN
LMIN +ǒVIN*VOUT*IOUT rDS(on)*RL IOUTǓ tON,MIN
DIL
LMIN +ǒVOUT)VSCHOTTKY)RL IOUTǓ tOFF,MIN
DIL
IPMOS(RMS) [IOUT D
Ǹ+IOUT VOUT
VIN
Ǹ
P(cond) +ǒIOUT D
ǸǓ2 rDS(on) ǒ1)TC ƪTJ*25°CƫǓ[ǒIOUT D
ǸǓ rDS(on)
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
Note that the capacitors must be able to handle the RMS current in continuous conduction mode, which can be
calculated using Equation 4:
(4)
Inductor Value Selection (Buck Controllers)
The inductor is chosen based on inductance value and maximum current rating. Larger inductors reduce current
ripple (and therefore, output voltage ripple) but are physically larger and more expensive. Inductors with lower
DC resistance typically improve efficiency, but also have higher cost and larger physical size. The buck
converters work well with inductor values between 4.7mH and 47mH in most applications. When selecting an
inductor, the current rating should exceed the current limit set by RIS or RDS,ON (see the Current Limit section). To
determine the minimum inductor size, first determine if the device will operate in minimum on-time or minimum
off-time mode. The device will operate in minimum on-time mode if Equation 5 is satisfied:
(5)
where RL= the inductor DC resistance.
Minimum inductor size needed when operating in minimum on-time mode is given by Equation 6:
(6)
Minimum inductor size needed when operating in minimum off-time mode is given by Equation 7:
(7)
where ΔIL= (20%–30%) x IOUT-MAX
External PMOS Transistor Selection (Buck Controllers)
The external PMOS transistor is selected based on threshold voltage (VT), on-resistance (RDS,ON), gate
capacitance (CG) and voltage rating. The PMOS VTmagnitude must be much lower than the lowest voltage at
IN1 or IN2 that will be used. A VTmagnitude that is 0.5V less than the lowest input voltage is normally sufficient.
The PMOS gate will see voltages from 0V to the maximum input voltage, so gate-to-source breakdown should be
a few volts higher than the maximum input supply. The drain-to-source of the device will also see this full voltage
swing, and should therefore be a few volts higher than the maximum input supply. The RMS current in the PMOS
can be estimated by using Equation 8:
(8)
The power dissipated in the PMOS is comprised of both conduction and switching losses. Switching losses are
typically insignificant. The conduction losses are a function of the RMS current and the RDS,ON of the PMOS, and
are calculated by Equation 9:
(9)
16 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
I(diode)(RMS) [IOUT(1*D)+IOUTǒ1*VOUT
VIN Ǔ
DVPP +DI ƪESR)ǒ1
8 COUT fǓƫ[1.1DI ESR
COUT +L DIOUT2
ǒVIN*VOUTǓ DV
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Diode Selection (Buck Controllers)
The diode is off when the PMOS is on, and on when the PMOS is off. Since it will be turned on and off at a
relatively high frequency, a Schottky diode is recommended for good performance. The peak current rating of the
diode should exceed the peak current limit set by the sense resistor RIS1,2. A diode with low reverse leakage
current and low forward voltage at operating current will optimize efficiency. Equation 10 calculates the estimated
average power dissipation:
(10)
Output Capacitor Selection (Buck Controllers)
The output capacitor is selected based on output voltage ripple and transient response requirements. As a result
of the nature of the hysteretic control loop, a minimum ESR of a few tens of mΩshould be maintained for good
operation unless a feed-forward resistor is used. Low ESR bulk tantalum or PosCap capacitors work best in most
applications. A 1.0mF ceramic capacitor can be used in parallel with this capacitor to filter higher frequency
spikes. The output voltage ripple can be estimated by Equation 11:
(11)
To calculate the capacitance needed to achieve a given voltage ripple as a result of a load transient from zero
output to full current, use Equation 12:
(12)
If only ceramic or other very low ESR output capacitor configurations are desired, additional voltage ripple must
be passed to the feedback pin. See Application Note SLVA210,Using Ceramic Output Capacitors with the
TPS6420x and TPS75003 Buck Controllers, available for download at www.ti.com, for detailed application
information.
Output Voltage Ripple Effect on VOUT (Buck Controllers)
Output voltage ripple causes VOUT to be higher or lower than the target value by half of the peak-to-peak voltage
ripple. For minimum on-time, the ripple adds to the voltage; for minimum off-time, it subtracts from the voltage.
Soft-Start Capacitor Selection (Buck Controllers)
The soft-start for BUCK1 and BUCK2 is not intended to be a precision function. However, the startup time (from
a positive transition on Enable to VOUT reaching its final value) has a linear relationship to CSS up to
approximately 800pF, which results in a startup time of approximately 4ms. Above this value of CSS, the variation
in start-up time increases rapidly. This variation can occur from unit to unit and even between the two BUCK
controllers in one device. Therefore, do not depend on the soft-start feature for sequencing multiple supplies if
values of CSS greater than 800pF are used.
BUCK1 is discussed in this section; it is identical to BUCK2. Soft-start is implemented on the buck controllers by
ramping current limit from 0 to its target value (set by R1) over a user-defined time. This time is set by the
external soft-start cap connected to pin SS1. If SS1 is left open, a small on-chip capacitor will provide a current
limit ramp time of approximately 250ms. Figure 25 shows the effects of R1 and SS1 on the current limit start-up
ramp.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS75003
3.0A
Current
Limit
0.7A
Time
R1 = 33mΩ
R1 = 143mΩ
CSS1 = 0.022µF
CSS1 = 0.022µF
CSS1 = 0.01µF
CSS1 = 0.01µF
VOUT +VFBǒR5
R6)1Ǔ
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
Figure 25. Effects of CSS1 and R1on Current Ramp Limit
This soft-start current limit ramp can be used to provide inrush current control or output voltage ramp control.
While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a
complex function of many variables. The dominant variables in this process are VOUT1, CSS1, IOUT1, and R1. Less
important variables are VIN1 and L1.
The best way to set a target start-up time is through bench measurement under target conditions, adjusting CSS1
to get the desired startup profile. To stay above a minimum start-up time, set the nominal start-up time to
approximately five times the minimum. To stay below a maximum time, set the nominal start-up time at one-fifth
of the maximum. Fastest start-up times occur at maximum VIN1, with minimum VOUT1, L1, COUT1, CSS1, and IOUT1.
Slowest start-up times occur under opposite conditions.
Refer to Figure 10 to Figure 14 for characterization curves showing how the start-up profile is affected by these
critical parameters.
Output Voltage Setting Selection (Buck Controllers)
Output voltage is set using two resistors as shown for Buck2 in Figure 1. Output voltage is then calculated using
Equation 13:
(13)
where VFB = 1.22V.
LDO OPERATION
The TPS75003 LDO uses a PMOS pass element and is offered in an adjustable version for ease of
programming to any output voltage. When used to power VCC,AUX it is set to 2.5V; it can optionally be set to other
output voltages to power other circuitry. The LDO has integrated soft-start, independent enable, and short-circuit
and thermal protection. The LDO can be used to power VCC,AUX on the Xilinx Spartan-3 FPGA when 3.3V JTAG
signals are used as described in Application Note SLVA159 (available for download from www.ti.com).
Input Capacitor Selection (LDO)
Although an input capacitor is not required, it is good analog design practice to connect a 0.1mF to 10mF low ESR
capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and
improves transient response, stability, and ripple rejection. A higher value capacitor may be needed if large, fast
rise-time load transients are anticipated, or if the device is located far from its power source.
18 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
VOUTǒtǓ+VOUT,SETǒ1*e*t
RCǓ
T90% +2.3 @480x103@CSS3(mF)
VOUT +VFBǒR3
R4)1Ǔ
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Output Capacitor Selection (LDO)
A 2.2mF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with
any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or
lower ESR output capacitors can be used.
Soft-Start (LDO)
The LDO uses an external soft-start capacitor, CSS3, to provide an RC-ramped reference voltage to the control
loop. (See the Functional Block Diagram.) This is a voltage-controlled soft-start, as compared to the
current-controlled soft-start used by the buck controllers. The start-up waveform can be approximated by
Equation 14:
(14)
where R = 480 × 103and C = capacitance in mF from SS3 to GND. The time taken to reach 90% of final VOUT
can be approximated by Equation 15:
(15)
Setting Output Voltage (LDO)
Output voltage is set using two resistors as shown in Figure 1. Output voltage is then calculated using
Equation 16:
(16)
where VFB = 0.507V.
Internal Current Limit (LDO)
The internal current limit of the LDO helps protect the regulator during fault conditions. When an over-current
condition is detected, the output voltage will be reduced until the current falls to a level that will not damage the
device. For good device reliability, the LDO should not operate at current limit.
Enable Pin (LDO)
The active high enable pin (EN3) can be used to put the device into shutdown mode. If shutdown and soft-start
capability are not required, EN3 can be tied to IN3.
Dropout Voltage (LDO)
The LDO uses a PMOS transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage
(VDO), the pass device is in its linear region of operation, and the input-output resistance is the RDS,ON of the pass
transistor. In this region, the regulator is said to be out of regulation; ripple rejection, line regulation, and load
regulation degrade as (VIN – VOUT) falls much below 0.5V.
Transient Response (LDO)
The LDO does not have an on-chip pull-down circuit for output is over-voltage conditions. This feature permits
applications that connect higher voltage sources such as an alternate power supply to the output. This design
also results in an output overshoot of several percent if the load current quickly drops to zero. The amplitude of
overshoot can be reduced by increasing COUT; the duration of overshoot can be reduced by adding a load
resistor.
Thermal Protection (LDO)
Thermal protection disables the output when the junction temperature, TJ, reaches unsafe levels. When the
junction cools, the output is again enabled. Depending on power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the
regulator, protecting it from damage. For good long term reliability, the device should not be continuously
operated at or near thermal shutdown.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS75003
PD+ǒVIN3*VOUT3Ǔ IOUT3
L1
IN3
OUT3
FB1
FB2
20
1
11
10
DGND
SS3
AGND
EN1
SS1
DGND
SW1
IN1
IS1
19
18
17
16
15
14
13
12
FB3
EN3
EN2
SS2
DGND
SW2
IN2
IS2
2
3
4
5
6
7
8
9
R6
R7
EN3
EN2
VIN
EN1
VIN
C5,
C18
C3,
C17
C7 R5
C10
C12, C16
C13, C15
Q1
Q2
L2 VOUT1
D2
C9
C6
VOUT3
C14
C8
R9
D1
R8
VOUT2
R4
C1
VIN
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
Power Dissipation (LDO)
The TPS75003 comes in a QFN-style package with an exposed lead frame on the package underside. The
exposed lead frame is the primary path for removing heat and should be soldered to a PC board that is
configured to remove the amount of power dissipated by the LDO, as calculated by Equation 17:
(17)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage. The two buck converters do not contribute a significant amount of dissipated power. Using
heavier copper will increase the overall effectiveness of removing heat from the device. The addition of plated
through-holes to heat-dissipating layers will also improve the heatsink effectiveness.
PCB Layout Considerations
As with any switching regulators, careful attention must be paid to board layout. A typical application circuit and
corresponding recommended printed circuit board (PCB) layout with emphasis on the most sensitive areas are
shown in Figure 26 through Figure 28.
Note: Most sensitive areas are highlighted by bold lines.
Figure 26. Typical Application Circuit
20 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Note: Most sensitive areas are highlighted in green.
Figure 27. Recommended PCB Layout, Component Side, Top View
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS75003
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
www.ti.com
Note: Most sensitive areas are highlighted in green.
Figure 28. Recommended PCB Layout, Bottom Side, Top View
22 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS75003
TPS75003
www.ti.com
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (August, 2008) to Revision I Page
• Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 2
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS75003
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS75003RHLR ACTIVE QFN RHL 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS75003RHLRG4 ACTIVE QFN RHL 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS75003RHLT ACTIVE QFN RHL 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS75003RHLTG4 ACTIVE QFN RHL 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS75003 :
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2010
Addendum-Page 2
•Enhanced Product: TPS75003-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS75003RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
TPS75003RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS75003RHLR QFN RHL 20 3000 367.0 367.0 35.0
TPS75003RHLT QFN RHL 20 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated