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List of figures
Figure 1: Block diagram .............................................................................................................................. 6
Figure 2: Pin connection (top through view) ............................................................................................... 7
Figure 3: Rise/fall time test setup ............................................................................................................. 16
Figure 4: Normalized rise and fall time vs. output capacitor value (typ. values in push-pull configuration)
.................................................................................................................................................................. 16
Figure 5: A master transmitter addressing a slave receiver with a 7-bit address (the transfer is not
changed) ................................................................................................................................................... 19
Figure 6: A master reads data from the slave immediately after the first byte ......................................... 19
Figure 7: Transfer sequencing .................................................................................................................. 20
Figure 8: I2C communication ..................................................................................................................... 20
Figure 9: Status register............................................................................................................................ 22
Figure 10: Power-on bit behavior .............................................................................................................. 22
Figure 11: Overtemperature (OVT) bit behavior ....................................................................................... 23
Figure 12: Cut-off behavior ....................................................................................................................... 23
Figure 13: Control register 1 ..................................................................................................................... 24
Figure 14: Control register 2 ..................................................................................................................... 26
Figure 15: Configuration register .............................................................................................................. 27
Figure 16: LED1 registers ......................................................................................................................... 30
Figure 17: LED2 registers ......................................................................................................................... 30
Figure 18: Parity register........................................................................................................................... 30
Figure 19: Power stage, Q2 is not present on L+ output .......................................................................... 34
Figure 20: Fast demagnetization principle schematic. Load connected to L- .......................................... 34
Figure 21: Fast demagnetization waveform. Load connected to L- ......................................................... 35
Figure 22: Slow demagnetization block. Load connected to L- ................................................................ 35
Figure 23: Slow demagnetization waveform. Load connected to GND .................................................... 36
Figure 24: Device initialization .................................................................................................................. 37
Figure 25: Current write mode flow chart procedure ................................................................................ 38
Figure 26: Current write mode frames ...................................................................................................... 39
Figure 27: Sequential write mode flow chart procedure ........................................................................... 40
Figure 28: Sequential write mode frames ................................................................................................. 41
Figure 29: Microcontroller parity check calculus ....................................................................................... 41
Figure 30: Register sequence in sequential write mode ........................................................................... 42
Figure 31: Current read mode flow chart procedure ................................................................................. 43
Figure 32: Current read mode frames ...................................................................................................... 44
Figure 33: Current read communication flow ............................................................................................ 44
Figure 34: Sequential/random read mode ................................................................................................ 44
Figure 35: Sequential/random read communication flow ......................................................................... 45
Figure 36: Block diagram communication mode ...................................................................................... 47
Figure 37: System communication mode ................................................................................................. 47
Figure 38: C/Q or L+ channel cut-off protection ....................................................................................... 48
Figure 39: C/Q or L+ channel current limitation and cut-off protection with latched restart ..................... 48
Figure 40: LED drivers .............................................................................................................................. 49
Figure 41: Linear regulator ....................................................................................................................... 50
Figure 42: Linear regulator principle schematic ........................................................................................ 50
Figure 43: Application example ................................................................................................................ 51
Figure 44: Supply voltage protection with uni-directional Transil ............................................................. 52
Figure 45: Refined supply voltage protection ........................................................................................... 52
Figure 46: VH protection vs. VCC ............................................................................................................... 53
Figure 47: Typical protection in IO-Link applications ................................................................................ 54
Figure 48: IO-Link and SIO application extended protection .................................................................... 55
Figure 49: VFQFPN 26L (3.5x5x1.0 mm) package outline....................................................................... 57
Figure 50: VFQFPN 26L (3.5x5x1.0 mm) carrier tape outline .................................................................. 58