September 2001 AS7C513 AS7C3513 5V/3.3V 32Kx16 CMOS SRAM )HDWXUHV * AS7C513 (5V version) * AS7C3513 (3.3V version) * Industrial and commercial temperature * Organization: 32,768 words x 16 bits * Center power and ground pins * High speed - 12/15/20 ns address access time - 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE - 800 mW (AS7C513) / max @ 12 ns - 432 mW (AS7C3513) / max @ 12 ns * Low power consumption: STANDBY - 28 mW (AS7C513) / max CMOS - 18 mW (AS7C3513) / max CMOS * Easy memory expansion with CE, OE inputs * TTL-compatible, three-state I/O * 44-pin JEDEC standard package - 400 mil SOJ - 400 mil TSOP 2 * ESD protection 2000 volts * Latch-up current 200 mA /RJLFEORFNGLDJUDP 3LQDUUDQJHPHQW 44-Pin SOJ, TSOP 2 (400 mil) A2 A3 A4 A5 A6 VCC Row decoder A1 32K x 16 Array NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 A11 NC GND A7 I/O buffer Control circuit A14 A13 A12 A11 A8 A9 Column decoder WE A10 I/O0-I/O7 I/O8-I/O15 UB OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AS7C513 AS7C3513 A0 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A4 A5 A6 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC LB CE 6HOHFWLRQJXLGH -12 -15 -20 Unit Maximum address access time 12 15 20 ns Maximum output enable access time 5 7 9 ns AS7C513 160 150 140 mA AS7C3513 120 110 100 mA AS7C513 5 5 5 mA AS7C3513 5 5 5 mA Maximum operating current Maximum CMOS standby current Y $OOLDQFH6HPLFRQGXFWRU 3RI &RS\ULJKW$OOLDQFH6HPLFRQGXFWRU$OOULJKWVUHVHUYHG $6& $6& )XQFWLRQDOGHVFULSWLRQ The AS7C513 and the AS7C3513 are high performance CMOS 524,288-bit Static Random Access Memory (SRAM) devices organized as 32,768 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6, 7, 8 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high, the devices enter standby mode. The AS7C513 and AS7C3513 are guaranteed not to exceed 28/18 mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0-I/O7, and/or I/O8-I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0-I/O7, and UB controls the higher bits, I/O8-I/O15. All chip inputs and outputs are TTL-compatible. The AS7C513 and AS7C3513 are packaged in common industry standard packages. $EVROXWHPD[LPXPUDWLQJV Parameter Device Symbol Min Max Unit AS7C513 Vt1 -0.50 +7.0 V AS7C3513 Vt1 -0.50 +5.0 V Voltage on any pin relative to GND Vt2 -0.50 VCC +0.50 V Power dissipation PD - 1.0 W Voltage on VCC relative to GND Storage temperature (plastic) Tstg -65 +150 oC Ambient temperature with VCC applied Tbias -55 +125 o C DC current into outputs (low) IOUT - 50 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7UXWKWDEOH CE WE OE LB UB I/O0-I/O7 H X X X X High Z High Z Standby (ISB, ISBI) L H L L H DOUT High Z Read I/O0-I/O7 (ICC) L H L H L High Z DOUT Read I/O8-I/O15 (ICC) L H L L L DOUT DOUT Read I/O0-I/O15 (ICC) L L X L L DIN DIN Write I/O0-I/O15 (ICC) L L X L H DIN High Z Write I/O0-I/O7 (ICC) L L X H L High Z DIN Write I/O8-I/O15 (ICC) L L H X H X X H X H High Z High Z I/O8-I/O15 Mode Output disable (ICC) Key: X = Don't care; L = Low; H = High Y $OOLDQFH6HPLFRQGXFWRU 3RI $6& $6& 5HFRPPHQGHGRSHUDWLQJFRQGLWLRQV Parameter Device Symbol Min Typical Max Unit AS7C513 VCC 4.5 5.0 5.5 V AS7C3513 VCC 3.0 3.3 3.6 V AS7C513 VIH 2.2 - VCC + 0.5 V AS7C3513 VIH 2.0 - VCC + 0.5 VIL -0.5 - 0.8 V commercial TA 0 - 70 C industrial TA -40 - 05 C Supply voltage Input voltage Ambient operating temperature V min = -3.0V for pulse width less than t /2. IL RC '&RSHUDWLQJFKDUDFWHULVWLFV RYHUWKHRSHUDWLQJUDQJH -12 Parameter Symbol Test conditions Device -15 -20 Min Max Min Max Min Max Unit Input leakage current | ILI | VCC = Max VIN = GND to VCC - 1 - 1 - 1 A Output leakage current | ILO | VCC = Max VOUT = GND to VCC - 1 - 1 - 1 A Operating power supply current ICC VCC = Max, CE VIL f = fMax , IOUT = 0mA AS7C513 - 160 - 150 - 140 AS7C3513 - 120 - 110 - 100 ISB VCC = Max, CE VIL f = fMax , IOUT = 0mA AS7C513 - 40 - 40 - 40 AS7C3513 - 40 - 40 - 40 VCC = Max, CE VCC-0.2V VIN GND + 0.2V or VIN VCC -0.2V, f = 0 AS7C513 - 3 - 3 - 3 ISB1 AS7C3513 - 3 - 3 - 3 VOL IOL = 8 mA, VCC = Min - 0.4 - 0.4 - 0.4 V VOH IOH = -4 mA, VCC = Min 2.4 - 2.4 - 2.4 - V Standby power supply current Output voltage &DSDFLWDQFH I 0+]7D R&9&& 120,1$/ Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE, LB, UB Vin = 0V 5 pF I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF Y $OOLDQFH6HPLFRQGXFWRU 3RI mA mA mA $6& $6& 5HDGF\FOH RYHUWKHRSHUDWLQJUDQJH -12 Parameter -15 -20 Symbol Min Max Min Max Min Max Unit Read cycle time tRC 12 - 15 - 20 - ns Address access time tAA - 12 - 15 - 20 ns 3 Chip enable (CE) access time tACE - 12 - 15 - 20 ns 3 Output enable (OE) access time tOE - 6 - 7 - 8 ns Output hold from address change tOH 3 - 4 - 4 - ns 5 CE Low to output in low Z tCLZ 0 - 0 - 0 - ns 4, 5 CE High to output in high Z tCHZ - 6 - 7 - 8 ns 4, 5 OE Low to output in low Z tOLZ 0 - 0 - 0 - ns 4, 5 Byte select access time tBA - 6 - 7 - 8 ns Byte select Low to low Z tBLZ 0 - 0 - 0 - ns 4,5 Byte select High to high Z tBHZ - 6 - 7 - 9 ns 4,5 OE High to output in high Z tOHZ - 6 - 7 - 9 ns 4, 5 Power up time tPU 0 - 0 - 0 - ns 4, 5 Power down time tPD - 12 - 15 - 20 ns 4, 5 .H\WRVZLWFKLQJZDYHIRUPV Rising input Falling input 5HDGZDYHIRUP DGGUHVVFRQWUROOHG Undefined output/don't care tRC Address tOH Data OUT Y tAA Previous data valid tOH Data valid $OOLDQFH6HPLFRQGXFWRU 3RI Notes $6& $6& 5HDGZDYHIRUP &(2(8%/%FRQWUROOHG tRC Address tAA OE tOE tOH tOLZ CE tOHZ tACE tLZ tHZ LB, UB tBA tBLZ tBHZ Data OUT Data valid :ULWHF\FOH RYHUWKHRSHUDWLQJUDQJH -12 -15 -20 Parameter Symbol Min Max Min Max Min Max Unit Write cycle time tWC 12 - 15 - 20 - ns Chip enable (CE) to write end tCW 9 - 10 - 12 - ns Address setup to write end tAW 8 - 10 - 12 - ns Address setup time tAS 0 - 0 - 0 - ns Write pulse width tWP 8 - 10 - 12 - ns Write recovery time tWR 0 - 0 - 0 - ns Address hold from end of write tAH 0 - 0 - 0 - ns Data valid to write end tDW 6 - 8 - 10 - ns Data hold time tDH 0 - 0 - 0 - ns 5 Write enable to output in high Z tWZ - 6 - 7 - 9 ns 4, 5 Output active from write end tOW 3 - 3 - 3 - ns 4, 5 Byte select Low to end of write tBW 8 - 9 - 12 - ns Y $OOLDQFH6HPLFRQGXFWRU Notes 3RI $6& $6& :ULWHZDYHIRUP :(FRQWUROOHG tWC tWR Address tAH tBW LB, UB tAW tAS tWP WE tDW tDH Data valid Data IN tWZ Data OUT tOW Data undefined :ULWHZDYHIRUP &(FRQWUROOHG High-Z tWC tWR Address tAS tAH tCW CE tAW tBW LB, UB tWP WE tDH tDW Data valid Data IN tCLZ Data OUT Y High-Z tWZ Data undefined $OOLDQFH6HPLFRQGXFWRU tOW High-Z 3RI $6& $6& $&WHVWFRQGLWLRQV - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. 9 *1' 'RXW QV )LJXUH$,QSXWSXOVH 7KHYHQLQHTXLYDOHQW 'RXW 9 9DQG9 9 & *1' )LJXUH%92XWSXWORDG 9 'RXW & *1' )LJXUH&92XWSXWORDG 1RWHV 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C=30pF, except on High Z and Low Z parameters, where C=5pF. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6& $6& 7\SLFDO'&DQG$&FKDUDFWHULVWLFV 1.4 1.0 0.8 0.6 ISB 0.4 0.2 NOMINAL Supply voltage (V) 0.6 ISB 0.4 1.2 1.1 1.0 0.9 0.8 MIN NOMINAL Supply voltage (V) Output source current IOH vs. output voltage VOH 140 Output sink current (mA) VCC = VCC(NOMINAL)PL 100 Ta = 25C 80 1.3 1.2 1.1 1.0 0.9 60 40 20 0 VCC Output voltage (V) Y Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC VCC = VCC(NOMINAL) Ta = 25C 1.0 0.8 0.6 0.4 0.0 -10 35 80 125 Ambient temperature (C) 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change tAA vs. output capacitive loading Output sink current IOL vs. output voltage VOL 35 120 30 VCC = VCC(NOMINAL) 100 Ta = 25C 80 60 40 20 VCC = VCC(NOMINAL) 25 20 15 10 5 0 0 -10 35 80 125 Ambient temperature (C) 0.2 140 120 0.2 1.2 VCC = VCC(NOMINAL) 0.8 -55 MAX 1 1.4 Normalized ICC Normalized access time 1.3 5 -55 1.4 Ta = 25C VCC = VCC(NOMINAL) 25 -10 35 80 125 Ambient temperature (C) Normalized access time tAA vs. ambient temperature Ta 1.5 1.4 625 0.04 0.0 -55 MAX Normalized access time tAA vs. supply voltage VCC 1.5 Normalized access time 0.8 0.2 0.0 MIN Output source current (mA) ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta Change in tAA (ns) 1.4 Normalized supply current ICC, ISB vs. supply voltage VCC 0 0 VCC Output voltage (V) $OOLDQFH6HPLFRQGXFWRU 0 250 500 750 Capacitance (pF) 3RI 1000 $6& $6& 3DFNDJHGLPHQVLRQV 44-pin TSOP 2 c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Min (mm) A e He 44-pin TSOP 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 l A2 A A1 0-5 0.05 A2 0.95 1.05 b 0.25 0.45 18.28 18.54 e 10.06 10.26 He 11.56 11.96 l D E1 E2 Pin 1 B c A A1 b Y 0.80 (typical) 0.40 0.60 44-pin SOJ 400 mil Min Max 44-pin SOJ e 0.15 (typical) d E E b 1.2 A1 c d Max (mm) Seating Plane A2 E2 $OOLDQFH6HPLFRQGXFWRU A A1 A2 B b c D E E1 E2 e 0.128 0.148 0.025 1.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.120 1.130 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM 3RI $6& $6& 2UGHULQJFRGHV Package\Access time Plastic SOJ, 400 mil TSOP 2, 18.4x10.2 mm Volt/Temp 12 ns 15 ns 20 ns 5V commercial AS7C513-12JC AS7C513-15JC AS7C513-20JC 3.3V commercial AS7C3513-12JC AS7C3513-15JC AS7C3513-20JC 5V commercial AS7C513-12TC AS7C513-15TC AS7C513-20TC 3.3V commercial AS7C3513-12TC AS7C3513-15TC AS7C3513-20TC 3DUWQXPEHULQJV\VWHP AS7C X 513 -XX Voltage: SRAM prefix Blank= 5V CMOS Device number Access time 3= 3.3V CMOS Y X C Package: J = SOJ 400 mil T =TSOP 2 18.4x10.2 mm Temperature range: C = Commercial, 0C to 70C I = Industrial, -40C to 85C $OOLDQFH6HPLFRQGXFWRU 3RI (c) Copyright Alliance Semiconductor Corporation. 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