TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 www.ti.com SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 Processor Supervisory Circuits with Window-Watchdog Check for Samples: TPS3813J25, TPS3813L30, TPS3813K33, TPS3813I50 FEATURES 1 * 2 * * * * * * Window-Watchdog With Programmable Delay and Window Ratio 6-Pin SOT-23 Package Supply Current of 9 A (Typ) Power On Reset Generator With a Fixed Delay Time of 25 ms Precision Supply Voltage Monitor 2.5 V, 3 V, 3.3 V, 5 V Open-Drain Reset Output Temperature Range -40C to +85C APPLICATIONS * * * * Applications Using DSPs, Microcontrollers, or Microprocessors Safety Critical Systems Automotive Systems Heating Systems DESCRIPTION The TPS3813 family of supervisory circuits provide circuit initialization and timing supervision, primarily for DSPs and processor-based systems. During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 25 ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider. For safety critical applications the TPS3813 family incorporates a so-called window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813 within this window not to assert a RESET. The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in a 6-pin SOT-23 package. The TPS3813 devices are characterized for operation over a temperature range of -40C to 85C. VDD 0.1mF DBV PACKAGE SOT-23 (TOP VIEW) 0.1mF R VDD WDR RESET TPS3813 WDT WDI 1 6 RESET GND 2 5 WDR WDT 3 4 VDD VDD WDI GND RESET mC I/O GND CWP Typical Operating Circuit 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2012, Texas Instruments Incorporated TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE AND ORDERING INFORMATION PACKAGE INFORMATION (1) TA -40C to +85C (1) DEVICE NAME THRESHOLD VOLTAGE MARKING TPS3813J25DBV 2.25 V PCDI TPS3813L30DBV 2.64 V PEZI TPS3813K33DBV 2.93 V PFAI TPS3813I50DBV 4.55 V PFBI For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com. Figure 1. ORDERING INFORMATION TPS381 3 J 25 DBV R Reel Package Nominal Supply Voltage Nominal Threshold Voltage Functionality Family ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) UNIT Supply voltage (2) VDD 7V RESET -0.3 V to VDD + 0.3 V All other pins (2) -0.3 V to 7 V IOL Maximum low output current 5 mA IOH Maximum high output current -5 mA IIK Input clamp current (VI < 0 or VI > VDD) 20 mA IOK Output clamp current (VO < 0 or VO > VDD) 20 mA Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range -40C to +85C Tstg Storage temperature range -65C to +150C Soldering temperature (1) (2) +260C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. For reliable operation the device should not be operated at 7 V for more than t = 1000h continuously. DISSIPATION RATING TABLE 2 PACKAGE TA < +25C POWER RATING DERATING FACTOR ABOVE TA = +25C TA = +70C POWER RATING TA = +85C POWER RATING DBV 437 mW 3.5 mW/C 280 mW 227 mW Copyright (c) 2000-2012, Texas Instruments Incorporated TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 www.ti.com SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 RECOMMENDED OPERATING CONDITIONS At specified temperature range. MIN MAX UNIT VDD Supply voltage 2 6 V VI Input voltage 0 VDD + 0.3 V VIH High-level input voltage VIL Low-level input voltage t/V Input transition rise and fall rate tw Pulse width of WDI trigger pulse TA Operating free-air temperature range 0.7 x VDD V 0.3 x VDD V 100 ns/V -40 +85 C MIN TYP MAX 50 ns ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted). PARAMETER VOL TEST CONDITIONS Low-level output voltage Power up reset voltage (1) VDD = 2 V to 6 V, IOL = 500 A 0.2 VDD = 3.3 V IOL = 2 mA 0.4 VDD = 6 V, IOL = 4 mA 0.4 VDD 1.1 V, IOL = 50 A TPS3813J25 VIT Negative-going input threshold voltage (2) TPS3813L30 TPS3813K33 TA = -40C to +85C TPS3813I50 Vhys Hysteresis 0.2 2.2 2.25 2.3 2.58 2.64 2.7 2.87 2.93 3 4.45 4.55 4.65 TPS3813J25 30 TPS3813L30 35 TPS3813K33 40 TPS3813I50 IIH High-level input current IIL Low-level input current IOH High-level output current IDD Supply current Ci Input capacitance (1) (2) UNIT V V V mV 60 WDI, WDR WDI = VDD = 6 V, WDR = VDD = 6 V WDT WDT = VDD = 6 V, VDD > VIT, RESET = High WDI, WDR WDI = 0 V, WDR = 0 V, VDD = 6 V WDT WDT = 0 V, VDD > VIT, RESET = High -25 25 -100 100 -25 25 -100 100 VDD = VIT + 0.2 V, VOH = VDD 25 VDD = 2 V output unconnected 9 13 VDD = 5 V output unconnected 20 25 VI = 0 V to VDD 5 nA nA A pF The lowest supply voltage at which RESET becomes active. tr, VDD 15 s/V. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 F) should be placed near to the supply terminals. Copyright (c) 2000-2012, Texas Instruments Incorporated 3 TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 www.ti.com TIMING REQUIREMENTS At RL = 1 M, CL = 50 pF, and TA = -40C to +85C. PARAMETER tw TEST CONDITIONS Pulse width at VDD MIN VDD = VIT- + 0.2 V, VDD = VIT- - 0.2 V TYP MAX UNIT s 3 SWITCHING CHARACTERISTICS At RL = 1 M, CL = 50 pF, and TA = -40C to +85C. PARAMETER td Delay time tt(out) Watchdog time-out TEST CONDITIONS Upper limit MIN TYP MAX VDD VIT + 0.2 V, See timing diagram 20 25 30 WDT = 0 V 0.2 0.25 0.3 WDT = VDD 2 2.5 3 WDT = programmable (1) See WDR = 0 V, WDT = 0 V tPHL (1) (2) VDD to RESET delay s ms 1:32 WDR = 0 V, WDT = programmable 1:25.8 WDR = VDD, WDT = 0 V 1:124.9 WDR = VDD, WDT = VDD 1:127.7 WDR = VDD, WDT = programmable Propagation (delay) time, high-to-low-level output ms 1:31.8 WDR = 0 V, WDT = VDD Watchdog window ratio (2) UNIT VIL = VIT - 0.2 V, VIH = VIT + 0.2 V 1:64.5 30 50 s 155 pF < C(ext) < 63 nF (C(ext) / 15.55 pF + 1) x 6.25 ms Table 1. TPS3813 FUNCTION/TRUTH TABLE 4 VDD > VIT RESET 0 L 1 H Copyright (c) 2000-2012, Texas Instruments Incorporated TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 www.ti.com SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 RESET Oscillator WDT Reset Logic and Timer Detection Circuit VDD GND Power to circuitry Watchdog Ratio Detection R1 + _ WDR R2 Bandgap Voltage Reference GND GND Rising Edge Detection WDI GND VDD VIT 0.6 V t td td td RESET Output Condition Undefined Output Condition Undefined t WDI 1st Window Without Lower Boundary t 2nd Window With Lower Boundary 3rd Window With Lower Boundary Trigger Pulse 1st Window Lower Window Without Lower 2nd Window 1st Window Boundary Boundary With Lower Without Lower Boundary Boundary 3rd Window With Lower Boundary The lower boundary of the watchdog window starts with the rising edge of the WDI trigger pulse. At the same time, all internal timers will be reset. If an external capacitor is used, the lower boundary is impacted due to the different oscillator frequency. This is described in more detail in the following section. The timing diagram and especially the shaded boundary is prepared in a nonreal ratio scale to better visualize the description. Copyright (c) 2000-2012, Texas Instruments Incorporated 5 TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 www.ti.com PIN CONFIGURATIONS DBV PACKAGE SOT-6 (TOP VIEW) WDI 1 6 RESET GND 2 5 WDR WDT 3 4 VDD Terminal Functions TERMINAL NAME NO. I/O GND 2 I Ground DESCRIPTION RESET 6 O Open-drain reset output VDD 4 I Supply voltage and supervising input WDI 1 I Watchdog timer input. This input must be driven at all times and not left floating. WDR 5 I Selectable watchdog window ratio input. This input must be tied to VDD or GND and not left floating. WDT 3 I Programmable watchdog delay input space TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2 20 WDI = GND, WDT = GND, WDR = GND 16 85C 14 12 25C 10 8 -40C 6 0C 4 0 1 2 3 4 VDD - Supply Voltage - V Figure 2. 6 1.50 25C 1.25 1 0.75 85C 0C 0.50 -40C 0.25 2 0 VDD = 2 V, WDI = GND, WDT = GND, WDR = GND 1.75 VOL - Low-Level Output Voltage - V I DD - Supply Current - A 18 5 6 0 0 1 2 3 4 5 6 7 IOL - Low-Level Output Current - mA Figure 3. Copyright (c) 2000-2012, Texas Instruments Incorporated TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 www.ti.com SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) VIT - Normalized Input Threshold Voltage - V (25 C) INPUT CURRENT vs INPUT VOLTAGE AT WDT 1000 800 I - Input Current - nA 600 25C 400 85C 200 0C 0 -200 -40C -400 I VDD = 6 V, WDI = GND, WDR = GND -600 -800 -1000 0 1 2 4 3 5 6 NORMALIZED INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD 1.001 1.000 0.999 0.998 0.997 WDI = Triggered, WDR = GND, WDT = GND 0.996 0.995 -40 -20 0 20 40 60 80 TA - Free-Air Temperature At VDD - C VI - Input Voltage at WDT - V Figure 4. Figure 5. MINIMUM PULSE DURATION AT VDD vs VDD THRESHOLD OVERDRIVE VOLTAGE t W - Minimum Pulse Duration at V DD - s 20 18 16 14 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VDD - Threshold Overdrive Voltage - V Figure 6. Copyright (c) 2000-2012, Texas Instruments Incorporated 7 TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION IMPLEMENTED WINDOW-WATCHDOG SETTINGS There are two different ways to set up the watchdog window. The first way is to use the implemented timing which is a default setting. Or, the default settings can be activated by wiring the WDT and WDR pin to VDD or GND. There is a total of four different timings available with these settings. They are listed in the table below. SELECTED OPERATION MODE WDR = 0 V WDT = 0 V WDR = VDD WDR = 0 V WDT = VDD WDR = VDD WINDOW FRAME LOWER WINDOW FRAME Max = 0.3 s Max = 9.46 ms Typ = 0.25 s Typ = 7.86 ms Min = 0.2 s Min = 6.27 ms Max = 0.3 s Max = 2.43 ms Typ = 0.25 s Typ = 2 ms Min = 0.2 s Min = 1.58 ms Max = 3 s Max = 93.8 ms Typ = 2.5 s Typ = 78.2 ms Min = 2 s Min = 62.5 ms Max = 3 s Max = 23.5 ms Typ = 2.5 s Typ = 19.6 ms Min = 2 s Min = 15.6 ms To visualize the values named in the table, a timing diagram was prepared. It is used to describe the upper and lower boundary settings. For an application, the important boundaries are the tboundary,max and twindow,min. Within these values, the watchdog timer should be retriggered to avoid a timeout condition or a boundary violation in the event of a trigger pulse in the lower boundary. The values in the table above are typical and worst case conditions. They are valid over the whole temperature range of -40C to +85C. II II II II II II II II II II II II In the shaded area of Figure 7, it cannot be predicted if the device will detect a violation or not and release a reset. This is also the case between the boundary tolerance of tboundary,min and tboundary,max as well as between twindow,min and twindow,max. It is important to set up the trigger pulses accordingly to avoid violations in these areas. WDI Detection of Rising Edge tboundary, min tboundary, max Window Frame to Reset the WDI tboundary, typ twindow, typ t twindow, min twindow, max Figure 7. Upper and Lower Boundary Visualization TIMING RULES OF WINDOW-WATCHDOG After the reset of the supervisor is released, the lower boundary of the first WDI window is disabled. However, after the first WDI pulse low-to-high transition is detected, the lower boundary function of the window is enabled. All further WDI pulses will need to fit into the configured window frame. 8 Copyright (c) 2000-2012, Texas Instruments Incorporated TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 www.ti.com SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 PROGRAMMABLE WINDOW-WATCHDOG BY USING AN EXTERNAL CAPACITOR The upper boundary of the watchdog timer can be set by an external capacitor connected between the WDT pin and GND. Common consumer electronic capacitors can be used to implement this feature. They should have low ESR and low tolerances since the tolerances have to be considered if the calculations are performed. The first formula is used to calculate the upper window frame. After calculating the upper window frame, the lower boundary can be calculated. As in the last example, the most important values are the tboundary,max and twindow,min. The trigger pulse has to fit into this window frame. The external capacitor should have a value between a minimum of 155 pF and a maximum of 63 nF. SELECTED OPERATION MODE WDT = external capacitor C(ext) t window,typ + C WINDOW FRAME WDR = 0 V and WDR = VDD (ext) )1 15.55 pF twindow,max = 1.25 x twindow,typ twindow,min = 0.75 x twindow,typ 6.25 ms (1) LOWER BOUNDARY CALCULATION The lower boundary can be calculated based on the values given in the switching characteristics. Additionally, facts have to be taken into account to verify that the lower boundary is where it is expected. Since the internal oscillator of the window watchdog is running free, any rising edge at the WDI pin will be taken into account at the next internal clock cycle. This happens regardless of the external source. Since the shift between internal and external clock is not known, it is best to consider the worst case condition for calculating this value. SELECTED OPERATION MODE LOWER BOUNDARY OF FRAME tboundary,max = twindow,max / 23.5 WDR = 0 V tboundary,typ = twindow,typ / 25.8 tboundary,min = twindow,min / 28.7 WDT = external capacitor C(ext) tboundary,max = twindow,max / 51.6 WDR = VDD tboundary,typ = twindow,typ / 64.5 tboundary,min = twindow,min / 92.7 WATCHDOG SOFTWARE CONSIDERATIONS To benefit from the window watchdog feature and help the watchdog timer monitor the software execution more closely, it is recommended that the watchdog be set and reset at different points in the program rather than pulsing the watchdog input periodically by using the prescaler of a microcontroller or DSP. Furthermore, the watchdog trigger pulses should be set to different timings inside the window frame to release a defined reset, if the program should hang in any subroutine. This allows the window watchdog to detect timeouts of the trigger pulse as well as pulses that distort the lower boundary. POWER-UP CONSIDERATIONS Many microcontrollers use general-purpose input/output (GPIO) pins that can be programmed to be either inputs or outputs. During power-up, these I/O pins are typically configured as inputs. If a GPIO pin is used to drive the WDI input pin of the TPS3813, then a pull-down resistor (shown as R2 in Figure 8) should be added to keep the WDI pin from floating during power-up. In applications where the WDI input may experience a negative voltage while VDD is ramping between 0 V and 0.8 V, then the VDD slew rate in this range should be greater than 10 V/s. A negative voltage on the WDI input along with a slew rate less than 10 V/s could result in a greatly reduced watchdog window time and reset output delay time. Copyright (c) 2000-2012, Texas Instruments Incorporated 9 TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 www.ti.com APPLICATION EXAMPLE A typical application example (see Figure 8) is used to describe the function of the watchdog in more detail. To configure the window watchdog function, two pins are provided by the TPS3813. These pins set the window timeout and ratio. The window watchdog ratio is a fixed ratio, which determines the lower boundary of the window frame. It can be configured in two different frame sizes. If the window watchdog ratio pin (WDR) is set to VDD, Position 1 in Figure 8, then the lower window frame is a value based on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT) connected to GND, it is a ratio of 1:124.9, for WDT connected to VDD, it is a ratio of 1:127.7, and for an external capacitor connected to WDT, it is a ratio of 1:64.5. If the window watchdog ratio pin (WDR) is set to GND, Position 2, the lower window frame will be a value based on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT) connected to GND, it will be a ratio of 1:31.8, for WDT connected to VDD it will be 1:32, and for an external capacitor connected to WDT it will be 1:25.8. The watchdog timeout can be set in two fixed timings of 0.25 seconds and 2.5 seconds for the window or can by programmed by connecting a external capacitor with a low leakage current at WDT. Example: If the watchdog timeout pin (WDT) is connected to VDD, the timeout will be 2.5 seconds. If the window watchdog ratio pin (WDR) is set in this configuration to a ratio of 1:127.7 by connecting the pin to VDD, the lower boundary is 19.6 ms. VDD 0.1 mF 0.1 mF VDD R1 Position 1 Position 2 VDD WDR RESET RESET TPS3813 Position 4 Position 5 Position 3 mC I/O WDI WDT C(ext) VDD GND R2 (1) GND VDD (1) Use this pull-down resistor if a GPIO pin is used to drive the WDI input pin of the TPS3813 to keep the WDI pin from floating during power-up. Figure 8. Application Example 10 Copyright (c) 2000-2012, Texas Instruments Incorporated TPS3813J25, TPS3813L30 TPS3813K33, TPS3813I50 www.ti.com SLVS331F - DECEMBER 2000 - REVISED AUGUST 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April, 2008) to Revision D Page * Updated table pin descriptions ............................................................................................................................................. 6 * Changed external capacitor value recommendations in paragraph 2 of Programmable Window-Watchdog section .......... 9 * Added Power-Up Considerations section ............................................................................................................................. 9 * Changed Figure 8 ............................................................................................................................................................... 10 Changes from Revision D (October 2010) to Revision E * Page Added Pull-up resistor value to ROC table for RESET ........................................................................................................ 3 Changes from Revision E (October 2010) to Revision F Page * Changed from Rev E to Rev F, August 2012 ....................................................................................................................... 1 * Deleted the Pull-up resistor value row in the ROC table ...................................................................................................... 3 Copyright (c) 2000-2012, Texas Instruments Incorporated 11 PACKAGE OPTION ADDENDUM www.ti.com 2-Aug-2012 PACKAGING INFORMATION Orderable Device (1) Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPS3813I50DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813I50DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813I50DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813I50DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813J25DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813J25DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813J25DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813J25DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813K33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813K33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813K33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813K33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813L30DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813L30DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813L30DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3813L30DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 2-Aug-2012 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TPS3813I50, TPS3813K33 : * Automotive: TPS3813I50-Q1, TPS3813K33-Q1 * Enhanced Product: TPS3813K33-EP NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS3813I50DBVR SOT-23 DBV 6 3000 178.0 9.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 TPS3813I50DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS3813J25DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS3813J25DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS3813K33DBVR SOT-23 DBV 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS3813K33DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS3813K33DBVT SOT-23 DBV 6 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS3813K33DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS3813L30DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS3813L30DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3813I50DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPS3813I50DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TPS3813J25DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPS3813J25DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TPS3813K33DBVR SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3813K33DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPS3813K33DBVT SOT-23 DBV 6 250 203.0 203.0 35.0 TPS3813K33DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TPS3813L30DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPS3813L30DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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