TPS3813I50DBVTG4 - Texas Instruments

VDD

WDR

WDT

RESET

WDI

GND

TPS3813

VDD

RESET

I/O

GND

CWP

0.1 Fm0.1 Fm

GND

WDT VDD

RESET

WDI

WDR

DBVPACKAGE

SOT-23

(TOPVIEW)

TypicalOperatingCircuit

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

www.ti.com

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

Processor Supervisory Circuits with Window-Watchdog

Check for Samples: TPS3813J25,TPS3813L30,TPS3813K33,TPS3813I50

During power on, RESET is asserted when supply

1FEATURES voltage (VDD) becomes higher than 1.1 V. Thereafter,

2• Window-Watchdog With Programmable Delay the supervisory circuit monitors VDD and keeps

and Window Ratio RESET active as long as VDD remains below the

• 6-Pin SOT-23 Package threshold voltage (VIT). An internal timer delays the

return of the output to the inactive state (high) to

• Supply Current of 9 μA (Typ) ensure proper system reset. The delay time, td= 25

• Power On Reset Generator With a Fixed Delay ms typical, starts after VDD has risen above the

Time of 25 ms threshold voltage (VIT). When the supply voltage

• Precision Supply Voltage Monitor 2.5 V, 3 V, drops below the threshold voltage (VIT), the output

becomes active (low) again. No external components

3.3 V, 5 V are required. All the devices of this family have a

• Open-Drain Reset Output fixed-sense threshold voltage (VIT) set by an internal

• Temperature Range –40°C to +85°C voltage divider.

For safety critical applications the TPS3813 family

APPLICATIONS incorporates a so-called window-watchdog with

• Applications Using DSPs, Microcontrollers, or programmable delay and window ratio. The upper

Microprocessors limit of the watchdog time-out can be set by either

connecting WDT to GND, VDD, or using an external

• Safety Critical Systems capacitor. The lower limit and thus the window ratio is

• Automotive Systems set by connecting WDR to GND or VDD. The

• Heating Systems supervised processor now needs to trigger the

TPS3813 within this window not to assert a RESET.

DESCRIPTION The product spectrum is designed for supply voltages

The TPS3813 family of supervisory circuits provide of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are

circuit initialization and timing supervision, primarily available in a 6-pin SOT-23 package.

for DSPs and processor-based systems. The TPS3813 devices are characterized for operation

over a temperature range of –40°C to 85°C.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS381 3 J DBV R

Reel

Package

Nominal Supply Voltage

Nominal Threshold Voltage

Functionality

Family

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE AND ORDERING INFORMATION

PACKAGE INFORMATION(1)

TADEVICE NAME THRESHOLD VOLTAGE MARKING

TPS3813J25DBV 2.25 V PCDI

TPS3813L30DBV 2.64 V PEZI

–40°C to +85°C TPS3813K33DBV 2.93 V PFAI

TPS3813I50DBV 4.55 V PFBI

(1) For the most current package and ordering information see the Package Option Addendum at the end

of this document, or see the device product folder at www.ti.com.

Figure 1. ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted).(1)

UNIT

Supply voltage(2) 7 V

VDD RESET –0.3 V to VDD + 0.3 V

All other pins (2) –0.3 V to 7 V

IOL Maximum low output current 5 mA

IOH Maximum high output current –5 mA

IIK Input clamp current (VI< 0 or VI> VDD) ±20 mA

IOK Output clamp current (VO< 0 or VO> VDD) ±20 mA

Continuous total power dissipation See Dissipation Rating Table

TAOperating free-air temperature range –40°C to +85°C

Tstg Storage temperature range –65°C to +150°C

Soldering temperature +260°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND. For reliable operation the device should not be operated at 7 V for more than t = 1000h

continuously.

DISSIPATION RATING TABLE

TA< +25°C DERATING FACTOR TA= +70°C TA= +85°C

PACKAGE POWER RATING ABOVE TA= +25°C POWER RATING POWER RATING

DBV 437 mW 3.5 mW/°C 280 mW 227 mW

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

www.ti.com

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

RECOMMENDED OPERATING CONDITIONS

At specified temperature range. MIN MAX UNIT

VDD Supply voltage 2 6 V

VIInput voltage 0 VDD + 0.3 V

VIH High-level input voltage 0.7 × VDD V

VIL Low-level input voltage 0.3 × VDD V

Δt/ΔV Input transition rise and fall rate 100 ns/V

twPulse width of WDI trigger pulse 50 ns

TAOperating free-air temperature range –40 +85 °C

ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDD = 2 V to 6 V, IOL = 500 μA 0.2

VOL Low-level output voltage VDD = 3.3 V IOL = 2 mA 0.4 V

VDD = 6 V, IOL = 4 mA 0.4

Power up reset voltage (1) VDD ≥1.1 V, IOL = 50 μA 0.2 V

TPS3813J25 2.2 2.25 2.3

TPS3813L30 2.58 2.64 2.7

Negative-going input threshold

VIT TA= –40°C to +85°C V

voltage (2) TPS3813K33 2.87 2.93 3

TPS3813I50 4.45 4.55 4.65

TPS3813J25 30

TPS3813L30 35

Vhys Hysteresis mV

TPS3813K33 40

TPS3813I50 60

WDI, WDR WDI = VDD = 6 V, WDR = VDD = 6 V –25 25

IIH High-level input current WDT WDT = VDD = 6 V, VDD > VIT, RESET = High –100 100 nA

WDI, WDR WDI = 0 V, WDR = 0 V, VDD = 6 V –25 25

IIL Low-level input current WDT WDT = 0 V, VDD > VIT, RESET = High –100 100

IOH High-level output current VDD = VIT + 0.2 V, VOH = VDD 25 nA

VDD = 2 V output unconnected 9 13

IDD Supply current μA

VDD = 5 V output unconnected 20 25

CiInput capacitance VI= 0 V to VDD 5 pF

(1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥15 μs/V.

(2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near to the supply terminals.

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

www.ti.com

TIMING REQUIREMENTS

At RL= 1 MΩ, CL= 50 pF, and TA= –40°C to +85°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

twPulse width at VDD VDD = VIT– + 0.2 V, VDD = VIT– – 0.2 V 3 μs

SWITCHING CHARACTERISTICS

At RL= 1 MΩ, CL= 50 pF, and TA= -40°C to +85°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tdDelay time VDD ≥VIT + 0.2 V, See timing diagram 20 25 30 ms

WDT = 0 V 0.2 0.25 0.3 s

tt(out) Watchdog time-out Upper limit WDT = VDD 2 2.5 3

WDT = programmable (1) See (2) ms

WDR = 0 V, WDT = 0 V 1:31.8

WDR = 0 V, WDT = VDD 1:32

WDR = 0 V, WDT = programmable 1:25.8

Watchdog window ratio WDR = VDD, WDT = 0 V 1:124.9

WDR = VDD, WDT = VDD 1:127.7

WDR = VDD, WDT = programmable 1:64.5

Propagation (delay) time,

tPHL VDD to RESET delay VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 30 50 μs

high-to-low-level output

(1) 155 pF < C(ext) < 63 nF

(2) (C(ext) ÷ 15.55 pF + 1) × 6.25 ms

Table 1. TPS3813 FUNCTION/TRUTH TABLE

VDD > VIT RESET

0 L

1 H

VDD

tdtdtd

VIT

0.6 V

RESET

Output Condition

Undefined

WDI

1st Window

Without Lower

Boundary 2nd Window

With Lower

Boundary

3rd Window

With Lower

Boundary Trigger Pulse

Lower Window

Boundary 1st Window

Without Lower

Boundary

1st Window

Without Lower

Boundary 2nd Window

With Lower

Boundary

3rd Window

With Lower

Boundary

Output Condition

Undefined

RESET

WDT

Rising Edge

Detection

Watchdog

Ratio

Detection

Reset Logic

and Timer

Bandgap

Voltage

Reference

Oscillator

Detection

Circuit

WDI

WDR

GND

VDD Power to circuitry

GND

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

www.ti.com

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

The lower boundary of the watchdog window starts with the rising edge of the WDI trigger pulse. At the same

time, all internal timers will be reset. If an external capacitor is used, the lower boundary is impacted due to the

different oscillator frequency. This is described in more detail in the following section. The timing diagram and

especially the shaded boundary is prepared in a nonreal ratio scale to better visualize the description.

IOL − Low-Level Output Current − mA

1.25

0.75

0.50

0 1 2 3

1.50

1.75

4 5 7

0°C

85°C

−40°C

25°C

0.25

V− Low-Level Output Voltage − V

VDD = 2 V,

WDI = GND,

WDT = GND,

WDR = GND

VDD − Supply Voltage − V

0 1 2 3

4 6

ISupply Current − − Aµ

0°C

85°C

−40°C

25°C

WDI = GND,

WDT = GND,

WDR = GND

GND

WDT VDD

RESET

WDI

WDR

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

www.ti.com

PIN CONFIGURATIONS

DBV PACKAGE

SOT-6

(TOP VIEW)

Terminal Functions

TERMINAL

NAME NO. I/O DESCRIPTION

GND 2 I Ground

RESET 6 O Open-drain reset output

VDD 4 I Supply voltage and supervising input

WDI 1 I Watchdog timer input. This input must be driven at all times and not left floating.

WDR 5 I Selectable watchdog window ratio input. This input must be tied to VDD or GND and not left floating.

WDT 3 I Programmable watchdog delay input

space TYPICAL CHARACTERISTICS

SUPPLY CURRENT LOW-LEVEL OUTPUT VOLTAGE

vs vs

SUPPLY VOLTAGE LOW-LEVEL OUTPUT CURRENT

Figure 2. Figure 3.

VDD − Threshold Overdrive Voltage − V

0 0.2 0.4 0.6

0.8 1 1.4

tMinimum Pulse Duration at V− sµ

DD −

01.2

VI − Input Voltage at WDT − V

400

200

−200

0 1 2 3

600

800

1000

4 5 6

0°C

85°C

−40°C

25°C

−400

−600

−800

−1000

− Input Current − nA

VDD = 6 V,

WDI = GND,

WDR = GND

TA − Free-Air Temperature At VDD − °C

0.998

0.997

0.996

0.995

−40 −20 0 20

0.999

1.000

1.001

40 60 80

(25 C)VIT − Normalized Input Threshold Voltage − V °

WDI = Triggered,

WDR = GND,

WDT = GND

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

www.ti.com

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

TYPICAL CHARACTERISTICS (continued)

INPUT CURRENT NORMALIZED INPUT THRESHOLD VOLTAGE

vs vs

INPUT VOLTAGE AT WDT FREE-AIR TEMPERATURE AT VDD

Figure 4. Figure 5.

MINIMUM PULSE DURATION AT VDD

VDD THRESHOLD OVERDRIVE VOLTAGE

Figure 6.

ÎÎ

Window Frame to Reset the WDI

tboundary, min

tboundary, max tboundary, typ

Detection of

Rising Edge

WDI

twindow, min

twindow, typ

twindow, max

ÎÎ

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

www.ti.com

DETAILED DESCRIPTION

IMPLEMENTED WINDOW-WATCHDOG SETTINGS

There are two different ways to set up the watchdog window. The first way is to use the implemented timing

which is a default setting. Or, the default settings can be activated by wiring the WDT and WDR pin to VDD or

GND. There is a total of four different timings available with these settings. They are listed in the table below.

SELECTED OPERATION MODE WINDOW FRAME LOWER WINDOW FRAME

Max = 0.3 s Max = 9.46 ms

WDR = 0 V Typ = 0.25 s Typ = 7.86 ms

Min = 0.2 s Min = 6.27 ms

WDT = 0 V Max = 0.3 s Max = 2.43 ms

WDR = VDD Typ = 0.25 s Typ = 2 ms

Min = 0.2 s Min = 1.58 ms

Max = 3 s Max = 93.8 ms

WDR = 0 V Typ = 2.5 s Typ = 78.2 ms

Min = 2 s Min = 62.5 ms

WDT = VDD Max = 3 s Max = 23.5 ms

WDR = VDD Typ = 2.5 s Typ = 19.6 ms

Min = 2 s Min = 15.6 ms

To visualize the values named in the table, a timing diagram was prepared. It is used to describe the upper and

lower boundary settings. For an application, the important boundaries are the tboundary,max and twindow,min. Within

these values, the watchdog timer should be retriggered to avoid a timeout condition or a boundary violation in the

event of a trigger pulse in the lower boundary. The values in the table above are typical and worst case

conditions. They are valid over the whole temperature range of –40°C to +85°C.

In the shaded area of Figure 7, it cannot be predicted if the device will detect a violation or not and release a

reset. This is also the case between the boundary tolerance of tboundary,min and tboundary,max as well as between

twindow,min and twindow,max. It is important to set up the trigger pulses accordingly to avoid violations in these areas.

Figure 7. Upper and Lower Boundary Visualization

TIMING RULES OF WINDOW-WATCHDOG

After the reset of the supervisor is released, the lower boundary of the first WDI window is disabled. However,

after the first WDI pulse low-to-high transition is detected, the lower boundary function of the window is enabled.

All further WDI pulses will need to fit into the configured window frame.

twindow,typ +ǒC(ext)

15.55 pF )1Ǔ 6.25 ms

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

www.ti.com

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

PROGRAMMABLE WINDOW-WATCHDOG BY USING AN EXTERNAL CAPACITOR

The upper boundary of the watchdog timer can be set by an external capacitor connected between the WDT pin

and GND. Common consumer electronic capacitors can be used to implement this feature. They should have low

ESR and low tolerances since the tolerances have to be considered if the calculations are performed. The first

formula is used to calculate the upper window frame. After calculating the upper window frame, the lower

boundary can be calculated. As in the last example, the most important values are the tboundary,max and twindow,min.

The trigger pulse has to fit into this window frame.

The external capacitor should have a value between a minimum of 155 pF and a maximum of 63 nF.

SELECTED OPERATION MODE WINDOW FRAME

twindow,max = 1.25 × twindow,typ

WDT = external capacitor C(ext) WDR = 0 V and WDR = VDD twindow,min = 0.75 × twindow,typ

(1)

LOWER BOUNDARY CALCULATION

The lower boundary can be calculated based on the values given in the switching characteristics. Additionally,

facts have to be taken into account to verify that the lower boundary is where it is expected. Since the internal

oscillator of the window watchdog is running free, any rising edge at the WDI pin will be taken into account at the

next internal clock cycle. This happens regardless of the external source. Since the shift between internal and

external clock is not known, it is best to consider the worst case condition for calculating this value.

SELECTED OPERATION MODE LOWER BOUNDARY OF FRAME

tboundary,max = twindow,max / 23.5

WDR = 0 V tboundary,typ = twindow,typ / 25.8

tboundary,min = twindow,min / 28.7

WDT = external capacitor C(ext) tboundary,max = twindow,max / 51.6

WDR = VDD tboundary,typ = twindow,typ / 64.5

tboundary,min = twindow,min / 92.7

WATCHDOG SOFTWARE CONSIDERATIONS

To benefit from the window watchdog feature and help the watchdog timer monitor the software execution more

closely, it is recommended that the watchdog be set and reset at different points in the program rather than

pulsing the watchdog input periodically by using the prescaler of a microcontroller or DSP. Furthermore, the

watchdog trigger pulses should be set to different timings inside the window frame to release a defined reset, if

the program should hang in any subroutine. This allows the window watchdog to detect timeouts of the trigger

pulse as well as pulses that distort the lower boundary.

POWER-UP CONSIDERATIONS

Many microcontrollers use general-purpose input/output (GPIO) pins that can be programmed to be either inputs

or outputs. During power-up, these I/O pins are typically configured as inputs. If a GPIO pin is used to drive the

WDI input pin of the TPS3813, then a pull-down resistor (shown as R2 in Figure 8) should be added to keep the

WDI pin from floating during power-up.

In applications where the WDI input may experience a negative voltage while VDD is ramping between 0 V and

0.8 V, then the VDD slew rate in this range should be greater than 10 V/s. A negative voltage on the WDI input

along with a slew rate less than 10 V/s could result in a greatly reduced watchdog window time and reset output

delay time.

WDI

WDR

WDT

GND

TPS3813

I/O

GND

Position 1

Position 2

Position 3

Position 5

Position 4

R2(1)

C(ext)

VDD

0.1 Fm

VDD VDD

RESET RESET

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

www.ti.com

APPLICATION EXAMPLE

A typical application example (see Figure 8) is used to describe the function of the watchdog in more detail.

To configure the window watchdog function, two pins are provided by the TPS3813. These pins set the window

timeout and ratio.

The window watchdog ratio is a fixed ratio, which determines the lower boundary of the window frame. It can be

configured in two different frame sizes.

If the window watchdog ratio pin (WDR) is set to VDD, Position 1 in Figure 8, then the lower window frame is a

value based on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT)

connected to GND, it is a ratio of 1:124.9, for WDT connected to VDD, it is a ratio of 1:127.7, and for an external

capacitor connected to WDT, it is a ratio of 1:64.5.

If the window watchdog ratio pin (WDR) is set to GND, Position 2, the lower window frame will be a value based

on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT) connected to GND,

it will be a ratio of 1:31.8, for WDT connected to VDD it will be 1:32, and for an external capacitor connected to

WDT it will be 1:25.8.

The watchdog timeout can be set in two fixed timings of 0.25 seconds and 2.5 seconds for the window or can by

programmed by connecting a external capacitor with a low leakage current at WDT.

Example: If the watchdog timeout pin (WDT) is connected to VDD, the timeout will be 2.5 seconds. If the window

watchdog ratio pin (WDR) is set in this configuration to a ratio of 1:127.7 by connecting the pin to VDD, the lower

boundary is 19.6 ms.

(1) Use this pull-down resistor if a GPIO pin is used to drive the WDI input pin of the TPS3813 to keep the WDI pin from

floating during power-up.

Figure 8. Application Example

TPS3813J25, TPS3813L30

TPS3813K33, TPS3813I50

www.ti.com

SLVS331F –DECEMBER 2000–REVISED AUGUST 2012

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (April, 2008) to Revision D Page

• Updated table pin descriptions ............................................................................................................................................. 6

• Changed external capacitor value recommendations in paragraph 2 of Programmable Window-Watchdog section .......... 9

• Added Power-Up Considerations section ............................................................................................................................. 9

• Changed Figure 8 ............................................................................................................................................................... 10

Changes from Revision D (October 2010) to Revision E Page

• Added Pull-up resistor value to ROC table for RESET ........................................................................................................ 3

Changes from Revision E (October 2010) to Revision F Page

• Changed from Rev E to Rev F, August 2012 ....................................................................................................................... 1

• Deleted the Pull-up resistor value row in the ROC table ...................................................................................................... 3

PACKAGE OPTION ADDENDUM

www.ti.com 2-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS3813I50DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS