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_______________General Description
Maxim’s MX7575/MX7576 are high-speed (5µs/10µs),
microprocessor (µP) compatible, 8-bit analog-to-digital
converters (ADCs). The MX7575 provides an on-chip
track/hold function that allows full-scale signals up to
50kHz (386mV/µs slew rate) to be acquired and digi-
tized accurately. Both ADCs use a successive-approxi-
mation technique to achieve their fast conversions and
low power dissipation. The MX7575/MX7576 operate
with a +5V supply and a 1.23V external reference. They
accept input voltages ranging from 0V to 2VREF.
The MX7575/MX7576 are easily interfaced to all popu-
lar 8-bit µPs through standard CS and RD control sig-
nals. These signals control conversion start and data
access. A BUSY signal indicates the beginning and
end of a conversion. Since all the data outputs are
latched and three-state buffered, the MX7575/MX7576
can be directly tied to a µP data bus or system l/O port.
Maxim also makes the MAX165, a plug-in replacement
for the MX7575 with an internal 1.23V reference. For
applications that require a differential analog input and
an internal reference, the MAX166 is recommended.
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
Audio Systems
High-Speed Servo Loops
Low-Power Data Loggers
____________________________Features
♦Fast Conversion Time: 5µs (MX7575)
10µs (MX7576)
♦Built-In Track/Hold Function (MX7575)
♦Low Total Unadjusted Error (±1LSB max)
♦50kHz Full-Power Signal Bandwidth (MX7575)
♦Single +5V Supply Operation
♦8-Bit µP Interface
♦100ns Data-Access Time
♦Low Power: 15mW
♦Small-Footprint Packages
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
________________________________________________________________
Maxim Integrated Products
1
DAC
COMP
LATCH AND
THREE-STATE
OUTPUT DRIVERS
SAR
TRACK/
HOLD
CLOCK
OSCILLATOR
CONTROL
LOGIC
AIN
AGND
REF
CLK
CS
RD
VDD
BUSY DGND
TP
16
18
49
6
14
D7
.
.
D0
15
17
5
1
2
3
MX7575
Functional Diagrams continued at end of data sheet.
_______________Functional Diagrams
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
VDD
REF
AIN
AGND
D0 (LSB)
D1
D2
D3
D4
CS
RD
TP (MODE)
BUSY
CLK
D7 (MSB)
D6
D5
DGND
TOP VIEW
10
9
DIP/SO
MX7575
MX7576
( ) ARE FOR MX7576 ONLY.
Pin Configurations continued at end of data sheet.
_________________Pin Configurations
19-0876; Rev 1; 5/96
PART
MX7575JN
MX7575KN
MX7575JCWN 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
18 Plastic DIP
18 Plastic DIP
18 Wide SO
______________Ordering Information
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
** Contact factory for availability.
MX7575KCWN 0°C to +70°C 18 Wide SO
MX7575JP 0°C to +70°C 20 PLCC
MX7575KP 0°C to +70°C 20 PLCC
INL
(LSB)
±1
±1/2
±1
±1/2
±1
±1/2
MX7575J/D 0°C to +70°C Dice* ±1
MX7575AQ -25°C to +85°C 18 CERDIP**
MX7575BQ -25°C to +85°C 18 CERDIP** ±1
±1/2
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +5V; VREF = 1.23V; AGND = DGND = 0V; fCLK = 4MHz external for MX7575; fCLK = 2MHz external for MX7576;
TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND...............................................................-0.3V, +7V
VDD to DGND ..............................................................-0.3V, +7V
AGND to DGND...............................................-0.3V, VDD + 0.3V
Digital Input Voltage to DGND
(CS, RD, TP, MODE)......................................-0.3V, VDD + 0.3V
Digital Output Voltage to DGND
(BUSY, D0–D7)..............................................-0.3V, VDD + 0.3V
CLK Input Voltage to DGND............................-0.3V, VDD + 0.3V
REF to AGND...................................................-0.3V, VDD + 0.3V
AIN to AGND....................................................-0.3V, VDD + 0.3V
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C)...............889mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
CERDIP (derate 10.53mW/°C above +70°C).................842mW
PLCC (derate 10.00mW/°C above +70°C) ....................800mW
Operating Temperature Ranges
MX757_J/K............................................................0°C to +70°C
MX757_A/B........................................................-25°C to +85°C
MX757_JE/KE ....................................................-40°C to +85°C
MX757_S/T.......................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering,10sec)..............................+300°C
VIN = 0V or VDD ±10
IIN
Input Current µA
±1 V2.4VINH
Input High Voltage V0.8VINL
Input Low Voltage
µA500IREF
Reference Current V1.23VREF
Reference Voltage
dB45SNRSignal-to-Noise Ratio (Note 2) V/µs0.386Slew Rate, Tracking MΩ10DC Input Impedance V02V
REF
Voltage Range
±1 Bits8Resolution
ppm/°C±5Offset Tempco LSB±1/2Offset Error (Note 1) ppm/°C±5Full-Scale Tempco LSB±1Full-Scale Error
LSB
±2
TUETotal Unadjusted Error
±1/2 LSB
±1
INLRelative Accuracy
Bits8No-Missing-Codes Resolution
UNITSMIN TYP MAXSYMBOLPARAMETER
TA= TMIN to TMAX
TA= +25°C
MX757_K/B/T
±5% variation for specified performance
MX7575, VIN = 2.46Vp-p at 10kHz, Figure 13
MX7575
MX757_J/A/S
MX757_K/B/T
MX757_J/A/S
1LSB = 2VREF/256
CONDITIONS
pF10CIN
Input Capacitance (Note 2)
ACCURACY
ANALOG INPUT
REFERENCE INPUT
LOGIC INPUTS
CS
,
RD
, MODE
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________________________________________________________________________________ 3
Note 1: Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.
Note 2: Sample tested at +25°C to ensure compliance.
Note 3: Accuracy may degrade at conversion times other than those specified.
Note 4: Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:
For MX7575 CS = RD = BUSY = high;
For MX7576 CS = RD = BUSY = MODE = high.
Using recommended
clock components:
RCLK = 100kΩ,
CCLK = 100pF;
TA= +25°C
VOUT = 0V to VDD, D0–D7
VIN = 0V
VIN = VDD
4.75V < VDD < 5.25V LSB±1/4Power-Supply Rejection mW15Power Dissipation
mA
7
IDD
Supply Current 36V5V
DD
Supply Voltage
µs
10 30
Conversion Time with
Internal Clock
515
µs
10
Conversion Time with
External Clock 5
pF10
Floating State Output
Capacitance (Note 2)
µA
±10
Floating State Leakage Current
V2.4VINH
Input High Voltage V0.8VINL
Input Low Voltage
±1 V4.0VOH
Output High Voltage V0.4VOL
Output Low Voltage
700
IINL µA
800
Input Low Current
700
IINH µA
800
Input High Current
UNITSMIN TYP MAXSYMBOLPARAMETER
MX757_S/T
MX757_J/A/K/B
±5% for specified performance
MX7576
MX7575
MX7576: fCLK = 2MHz
TA= +25°C
ISOURCE = 40µA
MX7575: fCLK = 4MHz
ISINK = 1.6mA
MX757_J/A/K/B
MX757_S/T
MX757_J/A/K/B
D0–D7
MX757_S/T
TA= T MIN to TMAX
CONDITIONS
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V; VREF = 1.23V; AGND = DGND = 0V; fCLK = 4MHz external for MX7575; fCLK = 2MHz external for MX7576;
TA= TMIN to TMAX, unless otherwise noted.)
CLOCK
LOGIC OUTPUTS (D0–D7,
BUSY
)
CONVERSION TIME (Note 3)
POWER REQUIREMENTS (Note 4)
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
4 _______________________________________________________________________________________
______________________________________________________________Pin Description
DIP/SO NAME FUNCTION
1CS Chip Select Input. CS must be low for the device to be selected or to recognize the RD input.
PIN
2RD Read Input. RD must be low to access data. RD is also used to start conversions. See the
Microprocessor Interface
section.
TP
(MX7575) Test Point. Connect to VDD.
7, 8 D6, D5 Three-State Data Outputs, bits 6 and 5
6 D7 Three-State Data Output, bit 7 (MSB)
5 CLK External Clock Input/Internal Oscillator Pin for frequency setting RC components.
4BUSY BUSY Output. BUSY going low indicates the start of a conversion. BUSY going high indicates the
end of a conversion.
9 DGND Digital Ground
TA= +25°C TA= TMIN to TMAX
ALL J/K/A/B S/T
PARAMETER SYMBOL CONDITIONS
MIN MAX MIN MAX MIN MAX
UNITS
CS to RD Setup Time t10 0 0 ns
RD to BUSY Propagation Time t2100 100 120 ns
Data-Access Time after RD t3(Note 6) 100 100 120 ns
RD Pulse Width t4100 100 120 ns
CS to RD Hold Time t50 0 0 ns
Data-Access Time after BUSY t6(Note 6) 80 80 100 ns
Data-Hold Time t7(Note 7) 10 80 10 80 10 100 ns
BUSY to CS Delay t80 0 0 ns
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF = 1.23V, AGND = DGND = 0V.)
Note 5: Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with
tr= tf= 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V.
Note 6: t3and t6are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: t7is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
PLCC
2
3
4
8, 9
7
6
5
10
3MODE
(MX7576) Mode Input. MODE = low puts the ADC into its asynchronous conversion mode. MODE has to be
tied high for the synchronous conversion mode and the ROM interface mode.
14 D0 Three-State Data Output, bit 0 (LSB)
10–13 D4–D1 Three-State Data Outputs, bits 4–1
15 AGND Analog Ground
16
12–15
17
18 VDD Power-Supply Voltage. +5V nominal.
17 REF Reference Input. +1.23V nominal.
— N.C. No Connect
20
19
1, 11
16 AIN Analog Input. 0V to 2VREF input range.18
Figure 1. Load Circuits for Data-Access Time Test
_______________Detailed Description
Converter Operation
The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (see
Functional
Diagrams
). The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
eight times during the conversion (see
MX7575
Track/Hold
and
MX7576 Analog Input
sections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the BUSY sig-
nal goes high, and the data in the output latches is
ready for microprocessor (µP) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
Microprocessor Interface
The CS and RD logic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
are performed. In the slow-memory interface mode, CS
and RD are taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
µPs that can be forced into a wait state. In the ROM
interface mode, however, the µP is not forced into a wait
state. A conversion is started by taking CS and RD low,
and data from the previous conversion is read. At the
end of the most recent conversion, the µP executes a
read instruction and starts another conversion.
For the MX7575, TP should be hard-wired to VDD to
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from VDD if TP is left open or tied to a voltage other than
VDD.
Slow-Memory Mode
Figure 3 shows the timing diagram for slow-memory
interface mode. This is used with µPs that have a wait-
state capability of at least 10µs (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking CS and RD
low). The BUSY signal (which is connected to the µP
READY input) then goes low and forces the µP into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after RD goes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor decision). At the end of the conversion, BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the µP com-
pletes the memory read by acquiring this new data.
The fast conversion time of the MX7575/MX7576
ensures that the µP is not forced into a wait state for an
excessive amount of time. Faster versions of many µPs,
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________________________________________________________________________________ 5
D_ D_
100pF
DGND DGND
+5V
100pF3k
3k
a) HIGH-Z TO VOH
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
b) HIGH-Z TO VOL
D_ D_
10pF
DGND DGND
+5V
10pF3k
3k
a) VOH TO HIGH-Z b) VOL TO HIGH-Z
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
MX7575/MX7576
including the 8085A-2, test the status of the READY
input immediately after the start of an instruction cycle.
Therefore, if the MX7575/MX7576 are to be effective in
placing the µP in a wait state, their BUSY output should
go low very early in the cycle. When using the 8085A-2,
the earliest possible indication of an upcoming read
operation is provided by the S0 status signal. Thus, S0,
which is low for a read cycle, should be connected to
the RD input of the MX7575/MX7576. Figure 4 shows
the connection diagram for the 8085A-2 to the
MX7575/MX7576 in slow-memory interface mode.
ROM Interface Mode
Figure 5 shows the timing diagram for ROM interface
mode. In this mode, the µP does not need to be placed
in a wait state. A conversion is started with a read
instruction (RD and CS go low), and old data is
accessed. The BUSY signal then goes low to indicate
the start of a conversion. As before, the MX7575
track/hold acquires the signal on the third falling clock
edge after RD goes low, while the MX7576 samples it
eight times during a conversion. At the end of a conver-
sion (BUSY going high), another read instruction always
accesses the new data and normally starts a second
conversion. However, if RD and CS go low within one
external clock period of BUSY going high, then the sec-
ond conversion is not started. Furthermore, for correct
operation in this mode, RD and CS should not go low
before BUSY returns high.
Figures 6 and 7 show the connection diagrams for
interfacing the MX7575/MX7576 in the ROM interface
mode. Figure 6 shows the connection diagram for the
6502/6809 µPs, and Figure 7 shows the connections for
the Z-80.
Due to their fast interface timing, the MX7575/MX7576
will interface to the TMS32010 running at up to 18MHz.
Figure 8 shows the connection diagram for the
TMS32010. In this example, the MX7575/MX7576 are
mapped as a port address. A conversion is initiated by
using an IN A and a PA instruction, and the conversion
result is placed in the TMS32010 accumulator.
Asynchronous Conversion Mode (MX7576)
Tying the MODE pin low places the MX7576 into a con-
tinuous conversion mode. The RD and CS inputs are
only used for reading data from the converter. Figure 9
shows the timing diagram for this mode of operation,
and Figure 10 shows the connection diagram for the
8085A. In this mode, the MX7576 looks like a ROM to
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
6 _______________________________________________________________________________________
Figure 3. Slow-Memory Interface Timing Diagram
CS
RD
BUSY
DATA HIGH-
IMPEDANCE
BUS
HIGH-
IMPEDANCE
BUS
OLD DATA NEW
DATA
t1t5
tCONV
t2
t3t6t7
Figure 4. MX7575/MX7576 to 8085A-2 Slow-Memory Interface
ADDRESS
DECODE
ADDRESS BUS +5V
DATA BUS
ADDRESS
LATCH
8085A-2
A8–A15
S0 RD
CS
TP/MODE
BUSY
D0–D7
ALE
AD0–AD7
READY
MX7575*
MX7576
* SOME CIRCUITRY OMITTED FOR CLARITY
S0 IS LOW FOR READ CYCLES
Figure 5. ROM Interface Timing Diagram
CS
RD
BUSY
DATA HIGH-
IMPEDANCE
BUS
HIGH-
IMPEDANCE
BUS
OLD
DATA
t1t5
t4
t2
t3t7
HIGH-IMPEDANCE BUS NEW
DATA
t8
t3t7
Figure 6. MX7575/MX7576 to 6502/6809 ROM Interface
ADDRESS
DECODE
ADDRESS BUS +5V
DATA BUS
6502-6809
A0–A15
R/W
Φ2 OR E RD
CS
EN
TP/MODE
D0–D7
D0–D7
MX7575*
MX7576
* SOME CIRCUITRY OMITTED FOR CLARITY
the µP, in that data can be accessed independently of
the clock. The output latches are normally updated on
the rising edge of BUSY. But if CS and RD are low
when BUSY goes high, the data latches are not updat-
ed until one of these inputs returns high. Additionally,
the MX7576 stops converting and BUSY stays high until
RD or CS goes high. This mode of operation allows a
simple interface to the µP.
Processor Interface for Signal Acquisition (MX7575)
In many applications, it is necessary to sample the
input signal at exactly equal intervals to minimize errors
due to sampling uncertainty or jitter. In order to achieve
this objective with the previously discussed interfaces,
the user must match software delays or count the num-
ber of elapsed clock cycles. This becomes difficult in
interrupt-driven systems where the uncertainty in inter-
rupt servicing delays is another complicating factor.
The solution is to use a real-time clock to control the
start of a conversion. This should be synchronous with
the CLK input to the ADC (both should be derived from
the same source), because the sampling instants occur
three clock cycles after CS and RD go low. Therefore,
the sampling instants occur at exactly equal intervals if
the conversions are started at equal intervals. In this
scheme, the output data is fed into a FIFO latch, which
allows the µP to access data at its own rate. This guar-
antees that data is not read from the ADC in the middle
of a conversion. If data is read from the ADC during a
conversion, the conversion in progress may be dis-
turbed, but the accessed data that belonged to the pre-
vious conversion will be correct.
The track/hold starts holding the input on the third
falling edge of the clock after CS and RD go low. If CS
and RD go low within 20ns of a falling clock edge, the
ADC may or may not consider this falling edge as the
first of the three edges that determine the sampling
instant. Therefore, the CS and RD should not be
allowed to go low within this period when sampling
accuracy is required.
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________________________________________________________________________________ 7
Figure 7. MX7575/MX7576 to Z-80 ROM Interface
ADDRESS
DECODE
ADDRESS BUS +5V
DATA BUS
Z-80
MREQ
RD RD
CS
EN
TP/MODE
D7
D0
DB7
DB0
MX7575*
MX7576
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 8. MX7575/MX7576 to TMS32010 ROM Interface
ADDRESS
DECODE
ADDRESS BUS +5V
DATA BUS
PA2
PA0
MEN
DEN RD
CS
EN
TP/MODE
D7
D0
DB7
DB0
MX7575*
MX7576
TMS32010
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9. MX7576 Asynchronous Conversion Mode Timing
Diagram
CS
RD
BUSY
DATA HIGH-
IMPEDANCE
BUS
HIGH-
IMPEDANCE
BUS
VALID
DATA
t1t5
t4
t3t7
HIGH-IMPEDANCE BUS VALID
DATA
UPDATE
LATCH DEFER
UPDATING
ADDRESS
ENCODE
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
8085A
A0–A15
RD RD
CS
MODE
D0–D7
ALE
AD0–AD7
MX7576*
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 10. MX7576 to 8085A Asynchronous Conversion Mode
Interface
MX7575/MX7576
MX7575 Track/Hold
The track/hold consists of a sampling capacitor and a
switch to capture the input signal. The simplified dia-
gram of this block is shown in Figure 11. At the begin-
ning of the conversion, switch S1 is closed, and the
input signal is tracked. The input signal is held (switch
S1 opens) on the third falling edge of clock after CS
and RD go low (Figure 12). This allows a minimum of
two clock cycles for the input capacitor to be charged
to the input voltage through the switch resistance. The
time required for the hold capacitor to settle to ±1/4LSB
is typically 7ns. Therefore, the input signal is allowed
ample time to settle before it is acquired by the
track/hold. When a conversion ends, switch S1 closes,
and the input signal is tracked.
The track/hold is capable of acquiring signals with slew
rates of up to 386mV/µs (or equivalently a 50kHz sine
wave with 2.46Vp-p amplitude). Figure 13 shows the
signal-to-noise ratio (SNR) versus input frequency for
the ADC. The SNR plot is generated at a sampling rate
of 200kHz using sinusoidal inputs with a peak-to-peak
amplitude of 2.46V. The reconstructed sine wave is
passed through a 50kHz 8th-order Chebychev filter.
The improvement in SNR at high frequencies is due to
the filter cutoff.
The switching nature of the analog input results in tran-
sient currents that charge the input capacitance of the
track/hold. Keep the driving source impedance low
(below 2kΩ), so that the settling characteristics of the
track/hold are not degraded. A low driving impedance
also minimizes undesirable noise pickup and reduces
DC errors caused by transient currents at the analog
input. As with any ADC, it is important to keep external
sources of noise to a minimum during a conversion.
Therefore, keep the data bus as quiet as possible dur-
ing a conversion, especially when the track/hold is
making the transition to the hold mode.
For conversion times that are significantly longer than
5µs, the device’s accuracy may degrade slightly, as
shown in Figure 14. This degradation is due to the
charge that is lost from the hold capacitor in the pres-
ence of small on-chip leakage currents.
MX7576 Analog Input
The MX7576 analog input can also be modeled with the
switch and capacitor as shown in Figure 11. However,
unlike the MX7575, the MX7576 samples the input volt-
age eight times during a conversion (once before each
comparator decision). Therefore, the precautions that
apply to the MX7575 also apply to the MX7576. These
include minimizing the analog source impedance and
reducing noise coupling from the digital circuitry during
a conversion, especially near a sampling instant.
Reference Input
The high speed of this ADC can be partially attributed to
the “inverted voltage output” topology of the DAC that it
uses. This topology provides low offset and gain errors
and fast settling times. The input current to the DAC,
however, is not constant. During a conversion, as differ-
ent DAC codes are tried, the DC impedance of the DAC
can vary between 6kΩand 18kΩ. Furthermore, when
the DAC codes change, small amounts of transient cur-
rent are drawn from the reference input. These charac-
teristics require a low DC and AC driving impedance for
the reference circuitry to minimize conversion errors.
Figure 15 shows the reference circuitry recommended
to drive the reference input of the MX7575/MX7576.
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
8 _______________________________________________________________________________________
VIN CS
0.5pF CH
2pF
RON
500ΩS1
Figure 11. Equivalent Input Circuit
CS
RD
BUSY
INTERNAL
CLOCK
CS
RD
BUSY
EXTERNAL
CLOCK INPUT SIGNAL HELD HERE
a) WITH EXTERNAL CLOCK
b) WITH INTERNAL CLOCK
INPUT SIGNAL HELD HERE
Figure 12. MX7575 Track/Hold (Slow-Memory Interface)
Timing Diagrams
The decoupling capacitors are necessary to provide a
low AC source impedance.
Internal/External Clock
The MX7575/MX7576 can be run with either an exter-
nally applied clock or their internal clock. In either case,
the signal appearing at the clock pin is internally divid-
ed by two to provide an internal clock signal that is rela-
tively insensitive to the input clock duty cycle.
Therefore, a single conversion takes 20 input clock
cycles, which corresponds to 10 internal clock cycles.
Internal Clock
The internal oscillator frequency is set by an external
capacitor, CCLK, and an external resistor, RCLK, which
are connected as shown in Figure 16a. During a con-
version, a sawtooth waveform is generated on the CLK
pin by charging CCLK through RCLK and discharging it
through an internal switch. At the end of a conversion,
the internal oscillator is shut down by clamping the CLK
pin to VDD through an internal switch. The circuit for the
internal oscillator can easily be overdriven with an
external clock source.
The internal oscillator provides a convenient clock
source for the MX7575. Figure 17 shows typical conver-
sion times versus temperature for the recommended
RCLK and CCLK combination. Due to process varia-
tions, the oscillation frequency for this RCLK/CCLK com-
bination may vary by as much as ±50% from the
nominal value shown in Figure 17. Therefore, an exter-
nal clock should be used in the following situations:
1) Applications that require the conversion time to be
within 50% of the minimum conversion time for the
specified accuracy (5µs MX7575/10µs MX7576).
2) Applications in which time-related software con-
straints cannot accommodate conversion-time differ-
ences that may occur from unit to unit or over
temperature for a given device.
External Clock
The CLK input of the MX7575/MX7576 may be driven
directly by a 74HC or 4000B series buffer (e g., 4049),
or by an LS TTL output with a 5.6kΩpull-up resistor. At
the end of a conversion, the device ignores the clock
input and disables its internal clock signal. Therefore,
the external clock may continue to run between conver-
sions without being disabled. The duty cycle of the
external clock may vary from 30% to 70%. As dis-
cussed previously, in order to maintain accuracy, clock
rates significantly lower than the data sheet limits
(4MHz for MX7575 and 2MHz for MX7576) should not
be used.
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________________________________________________________________________________ 9
54
52
50
46
44
42
100 1k 100k
48
40
MX7575/6 FIG13
INPUT FREQUENCY (Hz)
SNR (dB)
10k
TA = +25°C
0
0.5
1.0
2.0
2.5
10 100 10000
1.5
MX7575/6 FIG14
CONVERSION TIME (µs)
RELATIVE ACCURACY (LSB)
1000
A B C
A: TA = +125°C
B: TA = +85°C
C: TA = +25°C
1.23V
0.1µF47µF
+5V
REF
3.3k
+
_
+
ICL8069
Figure 13. MX7575 SNR vs. Input Frequency
Figure 14. MX7575 Accuracy vs. Conversion Time
Figure 15. External Reference Circuit
MX7575/MX7576
______________ Typical Applications
Unipolar Operation
Figure 16a shows the analog circuit connections for
unipolar operation, and Figure 16b shows the nominal
transfer characteristic for unipolar operation. Since the
offset and full-scale errors of the MX7575/MX7576 are
very small, it is not necessary to null these errors in
most cases. If calibration is required, follow the steps in
the sections below.
Offset Adjust
The offset error can be adjusted by using the offset trim
capability of an op amp (when it is used as a voltage fol-
lower) to drive the analog input, AIN. The op amp should
have a common-mode input range that includes 0V. Set
its initial input to 4.8mV (1/2LSB), while varying its offset
until the ADC output code flickers between 0000 0000
and 0000 0001.
Full-Scale Adjustment
Make the full-scale adjustment by forcing the analog
input, AIN, to 2.445V (FS - 3/2LSB). Then vary the refer-
ence input voltage until the ADC output code flickers
between 1111 1110 and 1111 1111.
Bipolar Operation
Figure 18a shows an example of the circuit connection
for bipolar operation, and Figure 18b shows the nominal
transfer characteristic for bipolar operation. The output
code provided by the MX7575 is offset binary. The ana-
log input range for this circuit is ±2.46V (1LSB =
19.22mV), even though the voltage appearing at AIN is
in the 0V to 2.46V range. In most cases, the MX7575 is
accurate enough that calibration will not be necessary. If
calibration is not needed, resistors R1–R7 should have a
0.1% tolerance, with R4 and R5 replaced by one 10kΩ
resistor, and R2 and R3 with one 1kΩresistor. If calibra-
tion is required, follow the steps in the sections below.
Offset Adjust
Adjust the offset error by applying an analog input volt-
age of 2.43V (+FS - 3/2LSB). Then adjust resistor R5
until the output code flickers between 1111 1110 and
1111 1111.
Full-Scale Adjust
Null the full-scale error by applying an analog input
voltage of -2.45V (-FS + 1/2LSB). Then adjust resistor
R3 until the output code flickers between 0000 0000
and 0000 0001.
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
10 ______________________________________________________________________________________
16
17
15
5
4
1
2
3
9
18
+5V
+5V
47µF
47µF
0.1µF
3.3k
+1.23V
0.1µF
+5V
2.46V(max)
+
-D7–D0
DATA OUT
CONTROL INPUTS
CCLK
100pF, 1%
RCLK
100k, 2%
AIN
REF
AGND
CLK
BUSY
CS
RD
TP/
MODE
VDD
MX7575
MX7576
0000 0011
0000 0010
0000 0001
0000 0000
1111 1111
1111 1110
1111 1101
1LSB
2LSBs
3LSBs0
AIN, INPUT VOLTAGE (IN TERMS OF LSBs)
FS - 1LSB
FULL-SCALE
TRANSITION
(FS - 3/2LSB)
OUTPUT
CODE
FS = 2VREF
1LSB = –––
2FS
256
11
12
13
14
7-55 -25 25 75
8
10
AMBIENT TEMPERATURE (°C)
CONVERSION TIME (µs)
0 12510050
9
MX7576 MX7575
RCLK = 100kΩ
CCLK = 100pF
Figure 16a. Unipolar Configuration Figure 16b. Nominal Transfer Characteristic for Unipolar
Operation
Figure 17. Typical Conversion Times vs. Temperature Using
Internal Clock
__________Applications Information
Noise
To minimize noise coupling, keep both the input signal
lead to AIN and the signal return lead from AGND as
short as possible. If this is not possible, a shielded
cable or a twisted-pair transmission line is recommend-
ed. Additionally, potential differences between the ADC
ground and the signal-source ground should be mini-
mized, since these voltage differences appear as
errors superimposed on the input signal. To minimize
system noise pickup, keep the driving source resis-
tance below 2kΩ.
Proper Layout
For PC board layouts, take care to keep digital lines
well separated from any analog lines. Establish a sin-
gle-point, analog ground (separate from the digital sys-
tem ground) near the MX7575/MX7576. This analog
ground point should be connected to the digital system
ground through a single-track connection only. Any
supply or reference bypass capacitors, analog input fil-
ter capacitors, or input signal shielding should be
returned to the analog ground point.
__Functional Diagrams (continued)
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
______________________________________________________________________________________ 11
17
16
5
15
18
9
+5V
+5V
+5V
47µF
47µF
0.1µF
R6
3.3k
R7
10k
R1
1k
R2
820Ω
AGND DGND
R3
500Ω
INPUT VOLTAGE
R5
5k
R4
8.2k
0.1µFTLC271
+5V
+
D7–D0
DATA OUT
CL
100pF
2%
RCLK
REF
AIN
CLK
VDD
MX7575
ICL8069
1.2V
REFERENCE
111...111
111...110
100...010
100...001
100...000
011...111
011...110
000...001
000...000
OUTPUT
CODE
-FS
2 -1/2LSB
1/2LSB FS
2
2FS
256
-1LSB
FS = 2VREF
1LSB =
AIN
Figure 18a. MX7575 Bipolar Configuration Figure 18b. Nominal Transfer Characteristic for Bipolar
Operation
DAC
COMP
LATCH AND
THREE-STATE
OUTPUT DRIVERS
SAR
CLOCK
OSCILLATOR
CONTROL
LOGIC
AIN
AGND
REF
CLK
CS
RD
VDD
BUSY DGND
MODE
16
18
49
6
14
D7
D0
15
17
5
1
2
3
MX7576
.
.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_Ordering Information (continued)
__________________________________________________________Chip Topographies
____Pin Configurations (continued)
PART
MX7575JEWN
MX7575KEWN
MX7575JEQP -40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP. RANGE PIN-PACKAGE
18 Wide SO
18 Wide SO
20 PLCC
MX7575KEQP -40°C to +85°C 20 PLCC
MX7575SQ -55°C to +125°C 18 CERDIP**
MX7575TQ -55°C to +125°C 18 CERDIP**
INL
(LSB)
±1
±1/2
±1
±1/2
±1
±1/2
32 1 20 19
4
5
6
7
8
910 11 12 13
14
15
16
17
18
MX7575
MX7576
PLCC
TOP VIEW
AIN
AGND
D0 (LSB)
D1
D2
TP (MODE)
BUSY
CLK
D7 (MSB)
D6
D5
DGND
N.C.
D4
D3
RD
CS
N.C.
VDD
REF
( ) ARE FOR MX7576 ONLY.
MX7576JN
MX7576KN
MX7576JCWN 0°C to +70°C
0°C to +70°C
0°C to +70°C 18 Plastic DIP
18 Plastic DIP
18 Wide SO
MX7576KCWN 0°C to +70°C 18 Wide SO
MX7576JP 0°C to +70°C 20 PLCC
MX7576KP 0°C to +70°C 20 PLCC
±1
±1/2
±1
±1/2
±1
±1/2
MX7576J/D 0°C to +70°C Dice* ±1
MX7576AQ -25°C to +85°C 18 CERDIP**
MX7576BQ -25°C to +85°C 18 CERDIP** ±1
±1/2
MX7576JEWN
MX7576KEWN
MX7576JEQP -40°C to +85°C
-40°C to +85°C
-40°C to +85°C 18 Wide SO
18 Wide SO
20 PLCC
MX7576KEQP -40°C to +85°C 20 PLCC
MX7576SQ -55°C to +125°C 18 CERDIP**
MX7576TQ -55°C to +125°C 18 CERDIP**
±1
±1/2
±1
±1/2
±1
±1/2
* Contact factory for dice specifications.
** Contact factory for availability.
0.081"
(2.057mm)
0.130"
(3.302mm)
D2 D1
D6
*The two AGND pads must both be used (bonded together).
TRANSISTOR COUNT: 768
SUBSTRATE CONNECTED TO VDD
MX7575
D7
CLK
BUSY
N.C.
D0 AGND* AGND*
AIN
DGND
D5
TP
RD
CS
VDD
REF
D4
D3
0.081"
(2.057mm)
0.130"
(3.302mm)
D2 D1
D6
*The two AGND pads must both be used (bonded together).
TRANSISTOR COUNT: 768
SUBSTRATE CONNECTED TO VDD
MX7576
D7
(MSB)
CLK
BUSY
MODE
D0
(LSB) AGND* AGND*
AIN
DGND
D5
N.C.
RD
CS
VDD
REF
D4
D3
