74LVQ08SCX - Fairchild Semiconductor

Februa ry 199 2

Revised June 2001

74LVQ08 Low Voltage Quad 2-Input AND Gate

74LVQ08

Low Voltage Quad 2-Input AND Gate

General Description

The LVQ08 contains four, 2-input AND gates. Features

■Ideal for low power/low noise 3.3V applications

■Guaranteed simultaneous switching noise level and

dynamic thresh ol d per for man ce

■Guaranteed pin-to-pin skew AC performance

■Guaranteed incident wave switching into 75Ω

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let ter “X” to t he orderin g c ode.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number Package

Number Package Description

74LVQ08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LVQ08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Pin Names Description

An, BnInputs

OnOutputs

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74LVQ08

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Note 2: Unu s ed inputs m ust be he ld H I GH or LOW. They may not fl oat.

DC Elect ri cal Char act er ist ics

Note 3: All outputs loaded; th reshold s on input associate d w it h output un der test.

Note 4: Maximum test du ration 2.0 m s, one output loaded a t a t im e.

Note 5: Incident wa v e s witchin g on transmission lin es w it h im pedances as low as 75Ω for commercial temp erature range is guaranteed f or 74LVQ.

Note 6: Worst case package.

Note 7: Max num ber of outputs defined as (n). D at a inputs are driven 0V to 3.3V; one output at GN D .

Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switchin g 0V to 3.3V. Input-unde r-test sw itching: 3.3V to thresh old (VILD), 0V to threshold

(VIHD), f = 1 MHz.

Supply Voltage (VCC) −0.5V to +7.0V

DC Input Diode Current (IIK)

I = −0.5V −20 mA

I = VCC + 0.5V +20 mA

DC Input V oltage (VI) −0.5V to VCC + 0.5V

DC Output Diode Current (IOK)

O = −0.5V −20 mA

O = VCC + 0.5V +20 mA

DC Output Voltage (VO) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (IO) ±50 mA

DC VCC or Ground Curre nt

(ICC or IGND) ±200 mA

Storage Temperature (TSTG) −65°C to +150°C

DC Latch-Up Source or

Sink Current ±100 mA

Supply Voltage (VCC) 2.0V to 3.6V

Input Voltage (VI) 0V to VCC

Output Voltage (VO) 0V to VCC

Operating Temperature (TA) −40°C to +85°C

Minimum Input Edge Rate (∆V/∆t)

IN from 0.8V to 2.0V

CC @ 3.0V 125 mV/ns

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum High Level 3.0 1.5 2.0 2.0 V VOUT = 0.1V

Input V oltag e or VCC − 0.1V

VIL Maximum Low Level 3.0 1.5 0.8 0.8 V VOUT = 0.1V

Input V oltag e

VOH Minimum High Level 3.0 2.99 2.9 2.9 V IOUT = −50 µA

Output Voltage 3.0 2.58 2.48 V VIN = VIL or VIH (Note 3)

IOH = −12 mA

VOL Maximum Low Level 3.0 0.002 0.1 0.1 V IOUT = 50 µA

Output Voltage 3.0 0.36 0.44 V VIN = VIL or VIH (Note 3)

IOL = 12 mA

IIN Maximum Input 3.6 ±0.1 ±1.0 µAV

I = VCC, GND

Leakage Current

IOLD Minimum Dynamic 3.6 36 mA VOLD = 0.8V Max (Note 5)

IOHD Output Current (Note 4) 3.6 −25 mA VOHD = 2.0V Min (Note 5)

ICC Maximum Quiescent 3.6 2.0 20.0 µAVIN = VCC

Supply Current or GND

VOLP Quiet Output 3.3 0.4 0.8 V (Note 6)(Note 7)

Maximum Dynamic VOL

VOLV Quiet Output 3.3 −0.4 −0.8 V (Note 6)(Note 7)

Minimum Dynamic VOL

VIHD Maximum High Level 3.3 1.8 2.0 V (Note 6)(Note 8)

Dynamic Input Voltage

VILD Maximum Low Level 3.3 1.8 0.8 V (Note 6)(Note 8)

Dynamic Input Voltage

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74LVQ08

AC Electrical Characteristics

Note 9: Skew is def ined as t he absolute va lue of the difference between the actual propaga tio n delay f or any two separate o ut puts of t he same d evi ce. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Param eter gu aranteed by de s ign.

Capacitance

Note 10: CPD is meas ured at 10 M H z .

TA = +25°CT

A = −40°C to +85°C

Symbol Parameter VCC CL = 50 pF CL = 50 pF Units

(V) Min Typ Max Min Max

tPLH Propagation Delay 2.7 1.5 9.0 13.4 1.0 14.0 ns

3.3 ± 0.3 1.5 7.5 9. 5 1.0 10.0

tPHL Propagation Delay 2.7 1.5 8.4 12.0 1.0 13.0 ns

3.3 ± 0.3 1.5 7.0 8.5 1.0 9.0

tOSHL Output to Output Skew 2.7 1.0 1.5 1.5 ns

tOSLH (Note 9) 3.3 ± 0.3 1.0 1.5 1.5

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC = Open

CPD (Note 10) Power Dissipation Capacitance 17 pF VCC = 3.3V

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74LVQ08

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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74LVQ08 Low Voltage Quad 2-Input AND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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