ALC262-VD2-GR - REALTEK SEMICONDUCTOR

ALC262-GR

ALC262-VB Series

(ALC262-VB0-GR, ALC262SRS-GR, ALC262H-GR)

ALC262-VC Series (ALC262-VC1-GR, ALC262-VC2-GR)

ALC262-VD Series (ALC262-VD2-GR, ALC262W-VD2-GR)

4-CHANNEL DAC AND 6-CHANNEL ADC

HIGH DEFINITION AUDIO CODEC

DATASHEET

Rev. 1.9

15 April 2008

Track ID: JATR-1076-21

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com.tw

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code ii Track ID: JATR-1076-21 Rev. 1.9

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,

including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in

this document or in the product described in this document at any time. This document could include

technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document

are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek

ALC262 Series Audio Codecs.

Though every effort has been made to ensure that this document is current and accurate, more

information may have become available subsequent to the production of this guide. In that event, please

contact your Realtek representative for additional information that may help in the development process.

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code iii Track ID: JATR-1076-21 Rev. 1.9

REVISION HISTORY

Revision Release Date Summary

1.0 2005/05/02 First release.

1.1 2005/06/09 Update section 12 Ordering Information, page 78.

Revise analog output port information in section 1 General Description, page 1.

1.2 2005/08/25 Add ordering information note (see section 12 Ordering Information, page 78).

1.3 2005/10/17 Revise Figure 2, page 7.

Revise Table 84, page 72.

Update section 122 Ordering Information, page 78.

1.4 2005/11/25 Update section 12 Ordering Information, page 78.

1.5 2006/06/22 Release for ALC262 ‘C’ version.

Revise section 4 Block Diagram, page 6

Improve DAC/ADC filter characteristics, Table 79, page 68.

Support low voltage (1.5V~3.3V) IO for HAD link.

Add digital microphone input support (pins 2 and 46), see Figure 5, page 10.

Add digital microphone application note (section 10.4 Digital Microphone

Implementation, page 74).

Update section 12 Ordering Information, page 78.

1.6 2007/01/15 Update section 12 Ordering Information, page 78.

1.7 2007/01/22 Cosmetic changes to Figure 5, page 10.

1.8 2007/07/04 Release for ALC262 ‘D’ version.

This release was never checked/reviewed/approved

Supports 2nd SPDIF output:

Update section 8.2 Verb – Get Connection Select Control (Verb ID=F01h), page 40.

Update section 8.3 Verb – Set Connection Select (Verb ID=701h), page 41.

Meets Intel low power ECR compliant and power status control for all analog converter

and pin widgets. See section 7.5 Power Management, page 28.

1.9 2008/04/15 Added information for all ALC262 series (version A/B/C/D).

Added part number ALC262W-VD2-GR in section 12 Ordering Information, page 78.

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code iv Track ID: JATR-1076-21 Rev. 1.9

Table of Contents

1. GENERAL DESCRIPTION..............................................................................................................................................1

2. FEATURES.........................................................................................................................................................................3

2.1. HARDWARE FEATURES ................................................................................................................................................3

2.2. SOFTWARE FEATURES..................................................................................................................................................4

3. SYSTEM APPLICATIONS...............................................................................................................................................5

4. BLOCK DIAGRAM...........................................................................................................................................................6

4.1. ALC262 A/B VERSION ................................................................................................................................................6

4.2. ALC262 C VERSION ....................................................................................................................................................7

4.3. ALC262 D VERSION ....................................................................................................................................................8

4.4. ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................9

5. PIN ASSIGNMENTS .......................................................................................................................................................10

5.1. ALC262 A/B VERSION ..............................................................................................................................................10

5.2. GREEN PACKAGE AND VERSION IDENTIFICATION ......................................................................................................10

5.3. ALC262 C VERSION ..................................................................................................................................................11

5.4. GREEN PACKAGE AND VERSION IDENTIFICATION ......................................................................................................11

5.5. ALC262 D VERSION ..................................................................................................................................................12

5.6. GREEN PACKAGE AND VERSION IDENTIFICATION ......................................................................................................12

6. PIN DESCRIPTIONS.......................................................................................................................................................13

6.1. DIGITAL I/O PINS .......................................................................................................................................................13

6.2. ANALOG I/O PINS ......................................................................................................................................................13

6.3. FILTER/REFERENCE....................................................................................................................................................14

6.4. POWER/GROUND........................................................................................................................................................14

7. HIGH DEFINITION AUDIO LINK PROTOCOL .......................................................................................................15

7.1. LINK SIGNALS ............................................................................................................................................................15

7.1.1. Signal Definitions .................................................................................................................................................16

7.1.2. Signaling Topology...............................................................................................................................................17

7.2. FRAME COMPOSITION ................................................................................................................................................18

7.2.1. Outbound Frame – Single SDO............................................................................................................................18

7.2.2. Outbound Frame – Multiple SDO ........................................................................................................................19

7.2.3. Inbound Frame – Single SDI................................................................................................................................20

7.2.4. Inbound Frame – Multiple SDI ............................................................................................................................21

7.2.5. Variable Sample Rates .........................................................................................................................................21

7.3. RESET AND INITIALIZATION .......................................................................................................................................24

7.3.1. Link Reset .............................................................................................................................................................24

7.3.2. Codec Reset ..........................................................................................................................................................25

7.3.3. Codec Initialization Sequence ..............................................................................................................................26

7.4. VERB AND RESPONSE FORMAT ..................................................................................................................................27

7.4.1. Command Verb Format........................................................................................................................................27

7.4.2. Response Format..................................................................................................................................................27

7.5. POWER MANAGEMENT...............................................................................................................................................28

7.5.1. ALC262 A/B/C Versions .......................................................................................................................................28

7.5.2. ALC262 D Version ...............................................................................................................................................29

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code v Track ID: JATR-1076-21 Rev. 1.9

8. SUPPORTED VERBS AND PARAMETERS................................................................................................................31

8.1. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................31

8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)............................................................................31

8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................32

8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) .....................................................32

8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ..........................................................32

8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) ...............................................33

8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ..................................................33

8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ................................................34

8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) .................................................35

8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..................................................................35

8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) ..........................36

8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ........................36

8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) .......................................................37

8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 A/B/C Version) ........37

8.1.14. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version) ...............38

8.1.15. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)..................................................38

8.1.16. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)..........................................................39

8.1.17. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)..............................................39

8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................40

8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................41

8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................41

8.5. VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................44

8.6. VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................44

8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................45

8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................45

8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................45

8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................46

8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................46

8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................48

8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................49

8.14. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................50

8.15. VERB – GET POWER STATE (VERB ID=F05H) (ALC262 A/B/C VERSION)................................................................51

8.16. VERB – GET POWER STATE (VERB ID=F05H) (ALC262 D VERSION) .......................................................................52

8.17. VERB – SET POWER STATE (VERB ID=705H) ............................................................................................................53

8.18. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................53

8.19. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................54

8.20. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................54

8.21. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................55

8.22. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................55

8.23. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................56

8.24. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................56

8.25. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................57

8.26. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) .......................................................................................57

8.27. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 58

8.28. VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................58

8.29. VERB – SET BEEP GENERATOR (VERB ID=70AH)....................................................................................................59

8.30. VERB – GET GPIO DATA (VERB ID=F15H)...............................................................................................................59

8.31. VERB – SET GPIO DATA (VERB ID=715H)................................................................................................................60

8.32. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................60

8.33. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................61

8.34. VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................61

8.35. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................62

8.36. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................62

8.37. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................63

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code vi Track ID: JATR-1076-21 Rev. 1.9

8.38. VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................63

8.39. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH)...........................................64

8.40. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)............................................65

8.41. GET/SET VOLUME KNOB WIDGET (NID=21H) (VERB ID=F0FH/70FH) ....................................................................66

8.42. GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H/723H~720H TO SET BIT[31:0]).....................................................66

9. ELECTRICAL CHARACTERISTICS ..........................................................................................................................67

9.1. DC CHARACTERISTICS...............................................................................................................................................67

9.1.1. Absolute Maximum Ratings..................................................................................................................................67

9.1.2. Threshold Voltage ................................................................................................................................................67

9.1.3. Digital Filter Characteristics ...............................................................................................................................68

9.1.4. S/PDIF Input/Output Characteristics...................................................................................................................68

9.2. AC CHARACTERISTICS...............................................................................................................................................69

9.2.1. Link Reset and Initialization Timing.....................................................................................................................69

9.2.2. Link Timing Parameters at the Codec..................................................................................................................70

9.2.3. S/PDIF Output and Input Timing .........................................................................................................................71

9.2.4. Test Mode .............................................................................................................................................................71

9.3. ANALOG PERFORMANCE ............................................................................................................................................72

10. APPLICATION NOTES .............................................................................................................................................73

10.1. APPLICATION CIRCUIT ...............................................................................................................................................73

10.2. VOLUME CONTROL VIA EXTERNAL VARIABLE RESISTOR .........................................................................................73

10.3. VOLUME CONTROL VIA GPIO0/GPIO1.....................................................................................................................74

10.4. DIGITAL MICROPHONE IMPLEMENTATION .................................................................................................................74

11. MECHANICAL DIMENSIONS.................................................................................................................................76

11.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................77

12. ORDERING INFORMATION ...................................................................................................................................78

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code vii Track ID: JATR-1076-21 Rev. 1.9

List of Tables

TABLE 1. DIGITAL I/O PINS........................................................................................................................................................13

TABLE 2. ANALOG I/O PINS .......................................................................................................................................................13

TABLE 3. FILTER/REFERENCE ....................................................................................................................................................14

TABLE 4. POWER/GROUND.........................................................................................................................................................14

TABLE 5. LINK SIGNAL DEFINITIONS .........................................................................................................................................16

TABLE 6. HDA SIGNAL DEFINITIONS.........................................................................................................................................16

TABLE 7. DEFINED SAMPLE RATE AND TRANSMISSION RATE....................................................................................................22

TABLE 8. 48KHZ VARIABLE RATE OF DELIVERY TIMING ..........................................................................................................22

TABLE 9. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING .......................................................................................................23

TABLE 10. 40-BIT COMMANDS IN 4-BIT VERB FORMAT...............................................................................................................27

TABLE 11. 40-BIT COMMANDS IN 12-BIT VERB FORMAT.............................................................................................................27

TABLE 12. SOLICITED RESPONSE FORMAT ..................................................................................................................................27

TABLE 13. UNSOLICITED RESPONSE FORMAT .............................................................................................................................27

TABLE 14. SYSTEM POWER STATE DEFINITIONS .........................................................................................................................28

TABLE 15. POWER CONTROLS IN NID IS 01H, 02H~05H, 07H~09H.............................................................................................28

TABLE 16. ALC262 VERSION A/B/C POWERED DOWN CONDITIONS ..........................................................................................29

TABLE 17. ALC262-VD SUPPORTS POWER CONTROLS IN NID 01H, 02H~03H, 06H, 07H~0AH, 10H~12H, 14H~1FH................30

TABLE 18. ALC262 VERSION D POWERED DOWN CONDITIONS .................................................................................................31

TABLE 19. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................31

TABLE 20. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H)..........................................................................31

TABLE 21. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) ........................................................................32

TABLE 22. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H) ...............................................32

TABLE 23. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H) ......................................................32

TABLE 24. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H)..........................................33

TABLE 25. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H).............................................33

TABLE 26. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH) ...........................................34

TABLE 27. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)...........................................35

TABLE 28. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH) ...............................................................35

TABLE 29. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH).......................36

TABLE 30. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) ....................36

TABLE 31. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH) ......................................................37

TABLE 32. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) (ALC262 A/B/C VERSION).....37

TABLE 33. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) (ALC262 D VERSION) ............38

TABLE 34. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H)..................................................38

TABLE 35. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) ............................................................39

TABLE 36. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H) .............................................39

TABLE 37. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ................................................................................40

TABLE 38. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................41

TABLE 39. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................41

TABLE 40. VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................44

TABLE 41. VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................44

TABLE 42. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................45

TABLE 43. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................45

TABLE 44. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................45

TABLE 45. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................46

TABLE 46. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................46

TABLE 47. VERB – SET AMPLIFIER GAIN (VERB ID=3H).............................................................................................................48

TABLE 48. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................49

TABLE 49. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................50

TABLE 50. VERB – GET POWER STATE (VERB ID=F05H) (ALC262 A/B/C VERSION) ................................................................51

TABLE 51. VERB – GET POWER STATE (VERB ID=F05H) (ALC262 D VERSION)........................................................................52

TABLE 52. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................53

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code viii Track ID: JATR-1076-21 Rev. 1.9

TABLE 53. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................54

TABLE 54. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................54

TABLE 55. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................55

TABLE 56. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................55

TABLE 57. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................56

TABLE 58. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................56

TABLE 59. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................57

TABLE 60. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) .......................................................................................57

TABLE 61. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)58

TABLE 62. VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................58

TABLE 63. VERB – SET BEEP GENERATOR (VERB ID=70AH) ....................................................................................................59

TABLE 64. VERB – GET GPIO DATA (VERB ID=F15H)...............................................................................................................59

TABLE 65. VERB – SET GPIO DATA (VERB ID=715H)................................................................................................................60

TABLE 66. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................60

TABLE 67. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................61

TABLE 68. VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................61

TABLE 69. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................62

TABLE 70. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) .........................................................62

TABLE 71. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................63

TABLE 72. VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................63

TABLE 73. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH)...........................................64

TABLE 74. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)............................................65

TABLE 75. GET/SET VOLUME KNOB WIDGET (NID=21H) (VERB ID=F0FH/70FH) ....................................................................66

TABLE 76. GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H / 723H~720H TO SET BIT[31:0])....................................................66

TABLE 77. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................67

TABLE 78. THRESHOLD VOLTAGE ...............................................................................................................................................67

TABLE 79. DIGITAL FILTER CHARACTERISTICS ...........................................................................................................................68

TABLE 80. S/PDIF INPUT/OUTPUT CHARACTERISTICS ................................................................................................................68

TABLE 81. LINK RESET AND INITIALIZATION TIMING..................................................................................................................69

TABLE 82. LINK TIMING PARAMETERS AT THE CODEC ...............................................................................................................70

TABLE 83. S/PDIF OUTPUT AND INPUT TIMING ..........................................................................................................................71

TABLE 84. ANALOG PERFORMANCE ............................................................................................................................................72

TABLE 85. ORDERING INFORMATION ..........................................................................................................................................78

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code ix Track ID: JATR-1076-21 Rev. 1.9

List of Figures

FIGURE 1. BLOCK DIAGRAM – ALC262 A/B VERSION ................................................................................................................6

FIGURE 2. BLOCK DIAGRAM – ALC262 C VERSION ....................................................................................................................7

FIGURE 3. BLOCK DIAGRAM – ALC262 D VERSION ....................................................................................................................8

FIGURE 4. ANALOG INPUT/OUTPUT UNIT.....................................................................................................................................9

FIGURE 5. ALC262 A/B VERSION PIN ASSIGNMENTS................................................................................................................10

FIGURE 6. ALC262 C VERSION PIN ASSIGNMENTS....................................................................................................................11

FIGURE 7. ALC262 D VERSION PIN ASSIGNMENTS....................................................................................................................12

FIGURE 8. HDA LINK PROTOCOL...............................................................................................................................................15

FIGURE 9. BIT TIMING................................................................................................................................................................16

FIGURE 10. SIGNALING TOPOLOGY .............................................................................................................................................17

FIGURE 11. SDO OUTBOUND FRAME ..........................................................................................................................................18

FIGURE 12. SDO STREAM TAG IS INDICATED IN SYNC ..............................................................................................................18

FIGURE 13. STRIPED STREAM ON MULTIPLE SDOS.....................................................................................................................19

FIGURE 14. SDI INBOUND STREAM .............................................................................................................................................20

FIGURE 15. SDI STREAM TAG AND DATA ...................................................................................................................................20

FIGURE 16. CODEC TRANSMITS DATA OVER MULTIPLE SDIS....................................................................................................21

FIGURE 17. LINK RESET TIMING..................................................................................................................................................25

FIGURE 18. CODEC INITIALIZATION SEQUENCE...........................................................................................................................26

FIGURE 19. CODEC INITIALIZATION SEQUENCE...........................................................................................................................30

FIGURE 20. LINK RESET AND INITIALIZATION TIMING ................................................................................................................69

FIGURE 21. LINK SIGNALS TIMING ..............................................................................................................................................70

FIGURE 22. OUTPUT AND INPUT TIMING......................................................................................................................................71

FIGURE 23. VOLUME CONTROL BY EXTERNAL VARIABLE RESISTOR ..........................................................................................73

FIGURE 24. VOLUME CONTROL VIA GPIO0 AND GPIO1.............................................................................................................74

FIGURE 25. DIGITAL MICROPHONE IMPLEMENTATION-1.............................................................................................................74

FIGURE 26. DIGITAL MICROPHONE IMPLEMENTATION-2.............................................................................................................75

FIGURE 27. DIGITAL MICROPHONE TIMING .................................................................................................................................75

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 1 Track ID: JATR-1076-21 Rev. 1.9

1. General Description

The ALC262 series are 4-Channel DAC and 6-Channel ADC High Definition Audio Codecs with UAA

(Universal Audio Architecture). Featuring two 24-bit stereo DACs and three 24-bit stereo ADCs (the

ALC262, ALC262-VB and ALC262-VC support 20-bit ADC format, the ALC262-VD supports 24-bit

ADC format), they are designed for high-performance multimedia desktop and laptop systems. The

ALC262 series incorporates proprietary converter technology to achieve over 100dB Signal-to-Noise

ratio playback quality.

The ALC series meets the current WLP3.10 (Windows® Logo Program) requirements, and the

ALC262-VD (D version) meets future WLP requirements that become effective from 01 June 2008,

bringing PC sound quality closer to consumer electronic devices.

The ALC262 series provide 4 channels of DAC, supporting stereo sound playback on the rear panel and

independent stereo sound output on the front panel simultaneously (multiple streaming), along with

flexible mixing, mute, and fine gain control functions to provide a complete integrated audio solution.

The ALC262 series also integrates three stereo ADCs that can support a microphone array with Acoustic

Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously,

significantly improving sound quality for PC VoIP applications. With this unique feature (3 stereo ADCs),

the ALC262 can provide high-quality audio using S/PDIF to output analog data, or for multiple-source

recording applications.

All analog IO are input and output capable and can be re-tasked according to user’s definitions.

Headphone amplifiers are also integrated at analog output ports A, B, C, D, E, and F. The ALC262 series

supports 16/20/24 S/PDIF input and output to offer easy connection of PCs to high quality consumer

electronic products such as digital decoders and speakers.

The ALC262 series supports host/soft audio from the Intel ICH chipset, and also from any other HDA

compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent

software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional

audio, and optional Dolby®, SRS®, Fortemedia® and Waves® audio technology the ALC262 provides an

excellent entertainment package and game experience for PC users.

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 2 Track ID: JATR-1076-21 Rev. 1.9

Two functions are added in the ALC262 C version:

• Addition of a digital microphone interface. The ALC262 C version supports most digital microphones

currently available. With digital microphone implementation, a notebook computer can achieve better

voice input quality without noise interference caused by geometric PCB layout and radio frequency

devices

• The ALC262 C supports scalable I/O voltage (1.5V to 3.3V) on an HDA link, which will be a

requirement in future chipsets designed for low voltage operation.

The ALC262 D supports a secondary S/PDIF output converter and a dedicated output pin (S/PDIF-OUT2)

to a HDMI transmitter, and all ADCs support up to192K sample rate and 24-bit PCM format. The

ALC262 D version conforms to Intel’s Audio Codec low power state white paper and is ECR compliant,

with improved frequency response at a 44.1kHz sampling rate, and THD+N measured at -1dB full scale

in compliance with future WLP requirements that become effective from 01 June 2008.

Note: ALC262 version differences are listed in section 12 Ordering Information, page 78.

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 3 Track ID: JATR-1076-21 Rev. 1.9

2. Features

2.1.

Hardware Features

 High-performance DACs with 100dB SNR

 ADCs with 90dB SNR (A-weighting)

 Meets WLP (Windows Logo Program) 3.10 and future WLP requirements that become effective

from 01 June 2008

 Two stereo DACs support 16/20/24-bit PCM for stereo audio playback on the rear panel, plus 2

channels of independent stereo sound output (multiple streaming) through the Front-Out-Left and

Front-Out-Right channels

 Three stereo ADCs support 16/20-bit PCM for multiple input streaming (ALC262A/B/C versions)

 Three stereo ADCs support 16/20/24-bit PCM for multiple input streaming (ALC262D version)

 All DACs supports 44.1/48/96/192kHz sample rate

 All ADCs support 44.1/48/96kHz sample rate (ALC262 A/B/C version)

 All ADCs support 44.1/48/96/192kHz sample rate (ALC262 D version)

 16/20/24-bit S/PDIF-OUT supports 44.1/48/96/192kHz sample rate

 16/20/24-bit S/PDIF-IN supports 44.1/48/96/192kHz sample rate

 Up to four channels of microphone input are supported for AEC/BF applications

 Supports MONO line output with independent volume control

 High-quality analog differential CD input

 Supports external PCBEEP input and built-in digital BEEP generator

 Software selectable 2.5V/3.75V VREFOUT

 Two jack detection pins each designed to detect up to 4 jacks

 Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain

 All analog jacks are stereo input and output re-tasking for analog plug & play

 Built-in headphone amplifiers for port-A/D/E/F

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 4 Track ID: JATR-1076-21 Rev. 1.9

 Supports both analog DC volume control and GPI digital volume control (requires driver support)

 4 GPIOs (General Purpose Input/Output) for customized applications

 Optional EAPD (External Amplifier Power Down) is supported

 Power support: Digital: 3.3V; Analog: 3.3V/5.0V

 Power management and enhanced power saving features

 48-pin LQFP ‘Green’ package; pin compatible with the ALC260

 Supports low voltage (1.5V~3.3V) IO for HDA link (ALC262 C/D version)

 Supports stereo digital microphone input (ALC262 C/D version)

 Supports 2nd S/PDIF output. (ALC262 D version)

 Intel low power ECR compliant and power status control for all widgets (ALC262 D version)

2.2.

Software Features

 Meets Microsoft Windows Logo Program requirements

 EAX™ 1.0 & 2.0 compatible

 Direct Sound 3D™ compatible

 A3D™ compatible

 I3DL2 compatible

 HRTF 3D Positional Audio (Windows XP only)

 Emulation of 26 sound environments to enhance gaming experience

 Multi-band software equalizer and tools

 Voice Cancellation and Key Shifting in Karaoke mode

 Dynamic range control (expander, compressor and limiter) with adjustable parameters

 Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience

 Provides 10-foot GUI for Windows Media Center

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 5 Track ID: JATR-1076-21 Rev. 1.9

 Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)

technology for voice application

 Smart multiple streaming operation

 HDMI audio driver for AMD platform

 Dolby® PCEE program™ (optional software feature)

 SRS® TrueSurround HD (optional software feature)

 Fortemedia® SAM™ technology for voice processing (Beam Forming and Acoustic Echo

Cancellation) (optional software feature)

 MaxxAudio technologies from Waves (optional software feature, ALC262-VD2 only)

3. System Applications

 Multimedia desktop and laptop PCs

 Information appliances (IA)

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 6 Track ID: JATR-1076-21 Rev. 1.9

4. Block Diagram

4.1.

ALC262 A/B Version

Figure 1. Block Diagram – ALC262 A/B Version

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 7 Track ID: JATR-1076-21 Rev. 1.9

4.2.

ALC262 C Version

Note: The ALC262 C Version supports digital MIC (DMIC-CLK, DMIC-DATA).

Figure 2. Block Diagram – ALC262 C Version

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 8 Track ID: JATR-1076-21 Rev. 1.9

4.3.

ALC262 D Version

Note: The ALC262 D Version supports digital MIC (DMIC-CLK, DMIC-DATA) and S/DPIF-OUT2.

02h

03h

Digital

Interface

LOUT

MONO

LINE

1(Port-C)

LINE

2(Port-E)

BEEP-IN

18h

0Ah

0Ch

0Dh

19h

1Ah

1Bh

1Ch

1Dh

1Fh

MONO

-OUT

HP-OUT(Port-A)

MIC

2(Port-F)

CD-IN

BEEP Gen

Digital ConverterS/PDIF-IN

DAC

DACVOL

VOL

VOLM

A:Output w/ Amplifier

MONO

LOUT

I/O

Boost

PCM

-OUT

VOL

ADCM

VOL

ADCM

I/O

22h

23h

24h

0Bh

09h

08h

07h

PCM

-OUT

PCM

-IN

PCM

-IN

PCM

-IN

Volume

KnobMute

Up/Down

21h

VOLM

Digitaql MIC Input

VOL

ADCM

Verb Control

Parameters

0Eh

LOUT1

LOUT2

LOUT1

LOUT2

LOUT1

LOUT2

LOUT1

LOUT2

LOUT1

LOUT2

12h

06h

S/PDIF

-OUT

1Eh

Digital Converter

S/PDIF-OUT

10h

S/PDIF

-OUT2

11h

Digital Converter

16h

15h

14h

LINE-OUT(Port-D)

Boost

LOUT1

MIC

1(Port-B)

S/PDIF-OUT2

S/PDIF-IN

Figure 3. Block Diagram – ALC262 D Version

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 9 Track ID: JATR-1076-21 Rev. 1.9

4.4.

Analog Input/Output Unit

Pin Complex widgets NID=14h~16h, 18h~1Bh are re-tasking IO.

EN_AMP

RLeft

EN_IBUF

EN_OBUF

Input_Signal_Left

Output_Signal_Left Right

Output_Signal_Right

Input_Signal_Right

EN_OBUF

Figure 4. Analog Input/Output Unit

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 10 Track ID: JATR-1076-21 Rev. 1.9

5. Pin Assignments

5.1.

ALC262 A/B Version

Note: C and D versions (Figure 6, page 11, and Figure 7, page 12) support digital MIC (pin 2, 46) and

Scalable I/O Power (pin 9).

Figure 5. ALC262 A/B Version Pin Assignments

5.2.

Green Package and Version Identification

Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 5. The version number is shown

in the location marked ‘VV’. For example, ‘VV=B0’ indicates silicon version ‘B’ and stepping version

‘0’, which is the first stepping of the ALC262 version B.

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 11 Track ID: JATR-1076-21 Rev. 1.9

5.3.

ALC262 C Version

The C version supports digital MIC (pin 2, 46) and Scalable I/O Power (pin 9).

Figure 6. ALC262 C Version Pin Assignments

5.4.

Green Package and Version Identification

Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 6. The version number is shown

in the location marked ‘VV’. For example, ‘VV=C0’ indicates silicon version ‘C’ and stepping version

‘0’, which is the first stepping of the ALC262-VC.

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 12 Track ID: JATR-1076-21 Rev. 1.9

5.5.

ALC262 D Version

The D version supports digital MIC (pin 2, 46), Scalable I/O Power (pin 9), and S/PDIFO2 (pin45).

Figure 7. ALC262 D Version Pin Assignments

5.6.

Green Package and Version Identification

Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 7. The version number is shown

in the location marked ‘VV’. For example, ‘VV=D0’ indicates silicon version ‘D’ and stepping version

‘0’, which is the first stepping of the ALC262-VD.

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 13 Track ID: JATR-1076-21 Rev. 1.9

6. Pin Descriptions

6.1.

Digital I/O Pins

Table 1. Digital I/O Pins

Name Type Pin No. Description Characteristic Definition

RESET# I 11 H/W Reset Control Vt=0.5*DVDD

SYNC I 10 Sample Sync (48kHz) Schmitt trigger input, VIL=1.0V, VIH=2.0V

BITCLK I 6 24MHz Bit Clock Input Schmitt trigger input, VIL=1.0V, VIH=2.0V

SDATA-OUT I 5 Serial TDM Data Input Vt=0.5*DVDD

SDATA-IN O 8 Serial TDM Data Output VOH=0.9*DVDD, VOL=0.1*DVDD

SPDIFI /

EAPD

IO 47 S/PDIF Input /

Signal to Power Down Ext. Amp

Self bias to Vt=1.5V /

Output VOH=0.9*DVDD, VOL=0.1*DVDD

SPDIFO O 48 S/PDIF Output Output has 12mA@75Ω driving capability.

SPDIFO2 O 451 S/PDIF Output Output has 12mA@75Ω driving capability.

GPIO0 IO 43 General Purpose Input/Output 0 Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,

VOL=0.1*DVDD, internal pulled up by 50KΩ

GPIO1 IO 44 General Purpose Input/Output 1 Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,

VOL=0.1*DVDD, internal pulled up by 50KΩ

GPIO2 /

DMIC-DATA

IO 22 General Purpose Input/Output 2.

Data Input from Digital MIC

Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,

VOL=0.1*DVDD, internal pulled up by 50KΩ

GPIO3 IO 3 General Purpose Input/Output 3 Input Vt=(2/3)*DVDD, output VOH=0.9*DVDD,

VOL=0.1*DVDD, internal pulled up by 50KΩ

DMIC-CLK O 462 Clock Output for Digital MIC Default 2.048MHz clock output

Total: 13 Pins

Note 1: Only the D version supports SPDIFO2.

Note 2: Only the C version and D version support DMIC-DATA and DMIC-CLK.

6.2.

Analog I/O Pins

Table 2. Analog I/O Pins

Name Type Pin No. Description Characteristic Definition

LINE2-L IO 14 2nd Line Input Left Channel Analog input/output, default is input (PORT-E)

LINE2-R IO 15 2nd Line Input Right Channel Analog input/output, default is input (PORT-E)

MIC2-L IO 16

2nd Stereo Microphone Input Left

Channel

Analog input/output, default is input (PORT-F)

MIC2-R IO 17

2nd Stereo Microphone Input

Right Channel

Analog input/output, default is input (PORT-F)

CD-L I 18 CD Input Left Channel Analog input, 1.6Vrms of full scale input

CD-GND I 19 CD Input Reference Ground Analog input, 1.6Vrms of full scale input

CD-R I 20 CD Input Right Channel Analog input, 1.6Vrms of full scale input

MIC1-L IO 21

1st Stereo Microphone Input Left

Channel

Analog input/output, default is input (PORT-B)

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 14 Track ID: JATR-1076-21 Rev. 1.9

Name Type Pin No. Description Characteristic Definition

MIC1-R IO 22

1st Stereo Microphone Input Right

Channel

Analog input/output, default is input (PORT-B)

LINE1-L IO 23 1st Line Input Left Channel Analog input/output, default is input (PORT-C)

LINE1-R IO 24 1st Line Input Right Channel Analog input/output, default is input (PORT-C)

PCBEEP I 12 External PCBEEP Input Analog input, 1.6Vrms of full scale input

LINE-OUT-L IO 35 Line Output Left Channel Analog output (PORT-D)

LINE-OUT-R IO 36 Line Output Right Channel Analog output (PORT-D)

HP-OUT-L IO 39 Headphone Out Left Channel Analog output (PORT-A)

HP-OUT-R IO 41 Headphone Out Right Channel Analog output (PORT-A)

MONO-OUT O 37 MONO Output Analog mono output is summation of (L+R)/2

Sense A I 13 Jack Detect Pin l Jack resistor network input 1

Sense B I 34 Jack Detect Pin 2 Jack resistor network input 2

DCVOL I 33 DC Sense for Volume Control Analog DC input for external volume control

Total: 20 Pins

6.3.

Filter/Reference

Table 3. Filter/Reference

Name Type Pin No. Description Characteristic Definition

VREF - 27 2.5V Reference Voltage 1µF capacitor to analog ground

MIC1-VREFO-L O 28 Bias Voltage for MIC1 Jack 2.5V/3.75Vreference voltage

LINE1-VREFO O 29 Bias Voltage for LINE1 Jack 2.5V/3.75Vreference voltage

MIC2-VREFO O 30 Bias Voltage for MIC2 Jack 2.5V/3.75Vreference voltage

LINE2-VREFO O 31 Bias Voltage for LINE2 Jack 2.5V/3.75Vreference voltage

MIC1-VREFO-R O 32 Bias Voltage for MIC1 Jack 2.5V/3.75Vreference voltage

JDREF - 40 Ref. Resistor for Jack Detect 20K, 1% resistor to analog ground

NC - 45, 46 Not Connected -

Total: 7 Pins

6.4.

Power/Ground

Table 4. Power/Ground

Name Type Pin No Description Characteristic Definition

AVDD1 I 25 Analog VDD (5V or 3.3V) Analog power for mixer and amplifier

AVSS1 I 26 Analog GND Analog ground for mixer and amplifier

AVDD2 I 38 Analog VDD (5V or 3.3V) Analog power for DACs and ADCs

AVSS2 I 42 Analog GND Analog ground for DACs and ADCs

DVDD-CORE I 1 Digital VDD (3.3V) Digital power

DVSS I 4 Digital GND Digital ground

DVDD-CORE

DVDD-IO

I 9 Digital VDD (3.3V)

Digital VDD (1.5V~3.3V)

A/B version: Digital power for core and HDA link.

C/D version: Scalable digital power for HDA link.

DVSS I 7 Digital GND Digital ground

Total: 8 Pins

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 15 Track ID: JATR-1076-21 Rev. 1.9

7. High Definition Audio Link Protocol

7.1.

Link Signals

The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the

HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent

by the HDA controller. The input and output streams, including command and PCM data, are isochronous

with a 48kHz frame rate. Figure 8 shows the basic concept of the HDA link protocol.

Figure 8. HDA Link Protocol

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 16 Track ID: JATR-1076-21 Rev. 1.9

7.1.1. Signal Definitions

Table 5. Link Signal Definitions

Item Description

BCLK 24.0MHz of bit clock sourced from the HDA controller and connecting to all codecs.

SYNC 48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA

controller and connects to all codecs.

SDO Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are

carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec

samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at

least one SDO. To extend outbound bandwidth, multiple SDOs may be supported.

SDI Serial data input signal driven by the codec. It is point-to-point serial data from the codec to the HDA

controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be

supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each

rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID.

RST# Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the

HDA controller and connects to all codecs.

Table 6. HDA Signal Definitions

Signal Name Source Controller Type Description

BCLK Controller Output Global 24.0MHz Bit Clock.

SYNC Controller Output Global 48kHz Frame Sync and Outbound Tag Signal.

SDO Controller Output Serial Data Output from Controller.

SDI Codec/Controller Input/Output Serial Data Input from Codec.

Weakly pulled down by the controller.

RST# Controller Output Global Active Low Reset Signal.

SDO

SYNC

SDI

BCLK

Start of Frame

8-Bit Frame SYNC

7654 0123 999 998 997 996 995 994 993 992 991 990

3 2 1 0 499 498 497 496 495 494

Controller samples SDI at rising edge of BCLK

Codec samples SDO at both rising and falling edge of BCLK

Figure 9. Bit Timing

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 17 Track ID: JATR-1076-21 Rev. 1.9

7.1.2. Signaling Topology

The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.

RST#, BCLK, SYNC, SDO0, and SDO1 are driven by controller to codecs. Each codec drives its own

point-to-point SDI signal(s) to the controller.

Figure 10 shows the possible connections between the HDA controller and codecs:

• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission

• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate

• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate

• Codec N has two SDOs and multiple SDIs

The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and

codecs. Section 7.2 Frame Composition, page 18, describes the detailed outbound and inbound stream

compositions for single and multiple SDOs/SDIs.

The connections shown in Figure 10 can be implemented concurrently in an HDA system. The ALC262

is designed to receive a single SDO stream.

RST#

BCLK

SYNC

SDO0

SDI0

Codec 0

RST#

BCLK

SYNC

SDO0

SDO1

SDI0

Codec 1

RST#

BCLK

SYNC

SDO0

SDI1

Codec 2

HDA

Controller

RST#

BCLK

SYNC

SDO0

SDO1

SDI0

SDI2

SDI14

RST#

BCLK

SYNC

SDO0

SDO1

SDI1

Codec N

SDI0

SDI1

SDI13

. . .

Single SDO

Single SDI

Two SDOs

Single SDI

Single SDO

Two SDIs

SDI2

Two SDOs

Multiple SDIs

Figure 10. Signaling Topology

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 18 Track ID: JATR-1076-21 Rev. 1.9

7.2.

Frame Composition

7.2.1. Outbound Frame – Single SDO

An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one

or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA

controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the

sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry

96kHz samples (Figure 11).

For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started

at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 12).

To keep the cadence of converters bound to the same stream, samples for these converters must be placed

in the same block.

Command Stream

SDO

SYNC

A 48kHz Frame is composed of Command stream and multiple Data streams

Stream 'X' DataStream 'A' Data

Stream 'A' Tag Stream 'X' Tag

Frame SYNC

(Here 'A' = 5) (Here 'X' = 6)

Next FramePrevious Frame

Null Field

Sample Block(s)

Block 1 Block 2 ..

.Block Y

Sample 1 Sample 2 ..

.Sample Z

msb ... lsb

For 48kHz rate, only Block1 is included

One or multiple blocks in a stream

For 96kHz rate, Block1 includes (N)th time of samples, Block2

includes (N+1)th time of samples

Z channels of PCM Sample

msb first in a sample

Padded at the

end of Frame

Figure 11. SDO Outbound Frame

SDO

SYNC

BCLK

Data of Stream 10

7654 0123

Preamble Stream=10

110

msb lsb

msb

Previous Stream

Stream Tag

(4-Bit) (4-Bit)

Figure 12. SDO Stream Tag is Indicated in SYNC

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 19 Track ID: JATR-1076-21 Rev. 1.9

7.2.2. Outbound Frame – Multiple SDO

The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission

in less time to get more bandwidth. If software determines the target codec supports multiple SDO

capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate

a specific stream (Stream ‘A’ in Figure 13) to be transmitted on multiple SDOs. In this case, the MSB of

stream data is always carried on SDO0, the second bit on SDO1 and so forth.

SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to

SDO0.

To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It

is always transmitted on SDO0, and copied on SDO1.

Figure 13. Striped Stream on Multiple SDOs

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 20 Track ID: JATR-1076-21 Rev. 1.9

7.2.3. Inbound Frame – Single SDI

An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams.

Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each

rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 14).

The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream

includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the

total length of the contiguous sample blocks within a given stream is not of integral byte

length (Figure 15).

Response Stream

SDI

SYNC

A 48kHz Frame is Composed of a Response Stream and Multiple Data streams

Stream 'X'

Stream 'A'

Frame SYNC

Next FramePrevious Frame

Null Field

Sample 1 Sample 2 ... Sample Z

msb ... lsb

For 48kHz rate, only Block1 is included

For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples

Z channels of PCM Sample

msb first in a sample

Padded at the end of Frame

Sample Block(s)Stream Tag

Block 1 Block 2 ... Block Y Null Pad

Figure 14. SDI Inbound Stream

BCLK

SDI

Data Length in Bytes

Dn-1 00

Stream Tag

B0Dn-2

B9D0

(Data Length in Bytes *8)-Bit

Next Stream

Null Pad

n-Bit Sample Block

A Complete Stream

Figure 15. SDI Stream Tag and Data

ALC262 Series

Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 21 Track ID: JATR-1076-21 Rev. 1.9

7.2.4. Inbound Frame – Multiple SDI

A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound

stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI

signals, each of which operate independently, with different stream numbers at the same frame time. This

is similar to having multiple codecs connected to the controller. The controller samples the divided stream

into separate memory with multiple DMA descriptors, then software re-combines the divided data into a

meaningful stream.

Response Stream

SDI0

SYNC

Stream 'X'

Frame SYNC

SDI10s

Tag A

Stream A, B, X, and Y are independent and have separate IDs

Data A

Tag B Data B

Codec drives SDI0 and SDI1

Stream 'A'

Stream 'B'

Response Stream 0s

Stream 'Y'

Figure 16. Codec Transmits Data Over Multiple SDIs

7.2.5. Variable Sample Rates

The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or

sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample

block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate

of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own

sample rate, independent of any other stream.

The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 22, shows the recommended

sample rates based on multiples or sub-multiples of one of the two base rates.

Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in

multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 22, shows the delivery cadence

of variable rates based on 48kHz.

The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple

rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid

frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample

blocks are transmitted every 160 frames.

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Datasheet

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The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no

sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery

rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames.

Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame

and interleave an empty frame between non-empty frames (Table 9, page 23).

Table 7. Defined Sample Rate and Transmission Rate

(Sub) Multiple 48kHz Base 44.1kHz Base

1/6 8kHz (1 sample block every 6 frames) -

1/4 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames)

1/3 16kHz (1 sample block every 3 frames) -

1/2 - 22.05kHz (1 sample block every 2 frames)

2/3 32kHz (2 sample blocks every 3 frames) -

1 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame)

2 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame)

4 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)

Table 8. 48kHz Variable Rate of Delivery Timing

Rate Delivery Cadence Description

8kHz YNNNNN (repeat) One sample block is transmitted in every 6 frames

12kHz YNNN (repeat) One sample block is transmitted in every 4 frames

16kHz YNN (repeat) One sample block is transmitted in every 3 frames

32kHz Y2NN (repeat) One sample block is transmitted in every 6 frames

48kHz Y (repeat) One sample block is transmitted in every 6 frames

96kHz Y2 (repeat) Two sample blocks are transmitted in each frame

192kHz Y4 (repeat) Four sample blocks are transmitted in each frame

N: No sample block in a frame.

Y: One sample block in a frame.

Yx: X sample blocks in a frame.

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Table 9. 44.1kHz Variable Rate of Delivery Timing

Rate Delivery Cadence

11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}

(repeat)

22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}

(repeat)

44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)

88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)

174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)

11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN

{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN

{ - }=NNNN

22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN

{11}=YNYNYNYNYNYNYNYNYNYNYN

{ - }=NN

44.1kHz 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with

no sample block.

88.2kHz 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with

no sample block.

174.4kHz 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with

no sample block.

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Datasheet

4-Ch DAC and 6-Ch ADC High Definition Audio Code 24 Track ID: JATR-1076-21 Rev. 1.9

7.3.

Reset and Initialization

There are two types of reset within an HDA link:

• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state

• Codec Reset. Generated by software directing a command to reset a specific codec back to its default

state

An initialization sequence is requested after any of the following three events:

1. Link Reset

2. Codec Reset

3. Codec changes its power state (For example, hot docking a codec to an HDA system)

7.3.1. Link Reset

A link reset may be caused by 3 events:

1. The HDA controller asserts RST# for any reason (power up, or PCI reset)

2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA

controller

3. Software initiates power management sequences. Figure 17, page 25, shows the ‘Link Reset’ timing

including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)

Enter ‘Link Reset’:

n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a

link reset

o As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the

end of the frame

p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low

q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state

r All link signals driven by controller and codecs should be tri-state by internal pull low resistors

ALC262 Series

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Exit from ‘Link Reset’:

s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)

t Software is responsible for de-asserting RST# after a minimum of 100µsec BCLK running time (the

100µsec provides time for the codec PLL to stabilize)

u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC

v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the

last bit of frame SYNC, it means the codec requests an initialization sequence)

SDOs

SYNC

SDIs

BCLK

Normal Frame

SYNC is absent

RST#

4 BCLK 4 BCLK

Driven Low

Previous Frame

Normal Frame

SYNC

Link in Reset

4 53 6 7

Pulled Low

Driven Low Pulled Low

Pulled Low

>=100 usec >= 4 BCLK Initialization Sequence

Wake Event

Figure 17. Link Reset Timing

7.3.2. Codec Reset

A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being

reset to the default state. After the target codec completes its reset operation, an initialization sequence is

requested.

In ALC262 D version, the extend power state of conforming to Intel low power ECR the function reset

could not initialize the register setting. Host SW needs to send ‘two’ function reset consecutively to reset

all settings.

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7.3.3. Codec Initialization Sequence

n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the

controller.

o The codec will stop driving the SDI during this turnaround period.

pqrs The controller drives SDI to assign a CAD to the codec.

t The controller releases the SDI after the CAD has been assigned.

u Normal operation state

Figure 18. Codec Initialization Sequence

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7.4.

Verb and Response Format

7.4.1. Command Verb Format

There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with

12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command

stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and

controls parameters in the codec.

Table 10. 40-bit Commands in 4-bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:16] Bit [15:0]

Reserved Codec Address Node ID Verb ID Payload

Table 11. 40-bit Commands in 12-bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:8] Bit [7:0]

Reserved Codec Address Node ID Verb ID Payload

7.4.2. Response Format

There are two types of response from the codec to the controller. Solicited Responses are returned by the

codec in response to a current command verb. The codec will send Solicited Response data in the next

frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by

software, opaque to the controller.

Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI

status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in

Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.

Table 12. Solicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:0]

Valid Unsol=0 Reserved Response

Table 13. Unsolicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:28] Bit [27:0]

Valid Unsol=1 Reserved Tag Response

Note: The response stream in the link protocol is 36-bits wide. The response is placed in the lower 32-bit

field. Bit-35 is a ‘Valid’ bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that an unsolicited

response was sent.

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7.5.

Power Management

7.5.1. ALC262 A/B/C Versions

The ALC262 does not support Wake-Up events when in low power mode. All power management state

changes in widgets are driven by software. Table 14 shows the System Power State Definitions.

In the ALC262, all the widgets include output/input converters support power control. Software may have

various power states depending on system configuration. Table 15 indicates those nodes that support

power management. To simplify power control, software can configure whole codec power states through

the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no

individual power control to supply fine-grained power control.

7.5.1.1 System Power State Definitions

Table 14. System Power State Definitions

Power States Definitions

D0 All Power On. Individual DACs and ADCs can be powered up or down as required.

D1 All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog

reference stays up.

D2 All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog

reference off (D1 + analog reference off).

D3 (Hot) Power Still Supplied. The codec stops the internal clock. State is maintained.

D3 (Cold) All Power Removed. State lost.

7.5.1.2 Power Controls in NID is 01h, 02h~05h, 07h~09h

Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h

Description D0 D1 D2 D3 (Hot/Cold) Link Reset

LINK Response Normal Normal Normal PD PD

DAC Normal PD PD PD PD

LINE ADC Normal PD PD PD PD

MIX ADC Normal PD PD PD PD

All Headphone Drivers Normal Normal PD PD Normal

All Mixers Normal Normal PD PD Normal

Audio Function

(NID=01h)

All Reference Normal Normal PD PD Normal

Note: PD=Powered Down.

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7.5.1.3 ALC262 Version A/B/C Powered Down Conditions

Table 16. ALC262 Version A/B/C Powered Down Conditions

Condition Description

LINK Response powered down Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with pulled low

47K resistors internally. Detection of ‘Link Reset Entry’ and ‘Link Reset Exit’

sequences are supported. All states are maintained if DVDD is supplied.

LOUT DAC powered down Analog block and digital filter are powered down.

LINE ADC powered down Analog block and digital filter are powered down. The data on SDATA-IN is quiet.

MIX ADC powered down Analog block and digital filter are powered down. The data on SDATA-IN is quiet.

Headphone Driver powered down All headphone drivers are powered down.

Mixers powered down All internal mixer widgets are powered down. The DC reference and VREFOUTx at

individual pin complex are still alive.

Reference power down All internal references, DC reference, and VREFOUTx at individual pin complexes

are off.

7.5.2. ALC262 D Version

The ALC262 version D is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B

compliant. It meets the five attributes discussed in the white paper:

1. D3 state power < 30mW.

2. Exit latency (D3 to D0 transfer) < 10ms.

3. Audio pop/click suppression during D3 and D0 transition < -65dBV.

4. Supports Jack detection in D3 state.

5. D3 functions with or without the BITCLK

The ALC262-VD minimizes D3 state idle mode power consumption and increases overall battery life in

mobile systems.

In D3 mode, only a power on reset or a ‘double function reset’ resets all ALC262-VD settings, cutting

software configuration time spent entering/leaving D3 state, and reducing latency time for D3 to D0

transitions.

The ALC262-VD supports Wake-Up events in D3 mode, including jack detection and GPIO status

changes. If the HDA-Link was alive (with BCLK), the ALC262-VD Wake-Up response is as normal. If

no BITCLK is present, the ALC262-VD drives the SDI high in order to wake up the system.

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Figure 19. Codec Initialization Sequence

All power management state changes in widgets are driven by software. Table 17 indicates the definitions

of power states.

In the ALC262-VD, the Audio Function (NID=01h), input converter, output converter, and each pin

widget supports power control. Software may have various power states dependent on system

configuration. Table 17 indicates those Nodes that support power management. To simplify power

control, software can configure whole codec power states using only the Audio Function (NID=01h).

Output converters (DACs) and input converters (ADCs) have no individual power control to supply

fine-Grained power control.

7.5.2.1 ALC262-VD Supports Power Controls in NID 01h, 02h~03h, 06h,

07h~0Ah, 10h~12h, 14h~1Fh

Table 17. ALC262-VD Supports Power Controls in NID 01h, 02h~03h, 06h, 07h~0Ah, 10h~12h, 14h~1Fh

Description D0 D1 D2 D3 D3 (No BCLK) Link Reset

LINK Response Normal Normal Normal PD PD PD

DAC Normal PD PD PD PD PD

LINE ADC Normal PD PD PD PD PD

MIX ADC Normal PD PD PD PD PD

All Headphone Drivers Normal Normal PD PD PD Normal

All Mixers Normal Normal PD PD PD Normal

Audio Function

(NID=01h)

All Reference Normal Normal PD PD PD Normal

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7.5.2.2 ALC262 Version D Powered Down Conditions

Table 18. ALC262 Version D Powered Down Conditions