Rev: 2.01 3/2003 1/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
18Mb Σ2x2B2
SigmaQuad SRAM
100 MHz–200 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
SigmaRAM™ Family Overview
GS8180Q18/36 are built in compliance with the SigmaQuad SRAM
pinout standard for Separate I/O synchronous SRAMs. They are
18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide,
very low voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance networking
systems.
SigmaQuad SRAMs are offered in a number of configurations. Some
emulate and enhance other synchronous separate I/O SRAMs. A
higher performance SDR (Single Data Rate) Burst of 2 version is also
offered. The logical differences between the protocols employed by
these RAMs hinge mainly on various combinations of address
bursting, output data registering, and write cueing. Along with the
Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs
allows a user to implement the interface protocol best suited to the
task at hand.
Clocking and Addressing Schemes
A Σ2x2B2 SigmaQuad SRAM is a synchronous device. It employs
two input register clock inputs, K and K. K and K are independent
single-ended clock inputs, not differential inputs to a single differential
clock input buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and C
clock inputs. C and C are also independent single-ended clock inputs,
not differential inputs. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead.
Because Separate I/O Σ2x2B2 RAMs always transfer data in two
packets, A0 is internally set to 0 for the first read or write transfer, and
automatically incremented by 1 for the next transfer. Because the LSB
is tied off internally, the address field of a Σ2x2B2 RAM is always one
address pin less than the advertised index depth (e.g., the 1M x 18
has a 512K addressable index).
-200 -150 -133 -100
tKHKH 5.0 ns 6.7 ns 7.5 ns 10.0 ns
tKHQV 2.3 ns 2.7 ns 3.0 ns 3.0 ns
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
JEDEC Std. MO-216, Variation CAB-1
Rev: 2.01 3/2003 2/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
1M x 18 SigmaQuad SRAM — Top View
1234567891011
A NC MCL/SA
(144Mb)
NC/SA
(36Mb) WBW1 KNC R SA MCL/SA
(72Mb) NC
B NC Q9 D9 SA NC K BW0 SA NC NC Q8
C NC NC D10 VSS SA SA SA VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS SA SA SA VSS NC NC D1
P NC NC Q17 SA SA C SA SA NC D0 Q0
R TDO TCK SA SA SA C SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. MCL = Must Connect Low
4. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 2.01 3/2003 3/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
512K x 36 SigmaQuad SRAM — Top View
1234567891011
A NC MCL/SA
(288Mb)
NC/SA
(72Mb) WBW2 KBW1 RNC/SA
(36Mb)
MCL/SA
(144Mb) NC
B Q27 Q18 D18 SA BW3 KBW0SA D17 Q17 Q8
C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1
P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0
R TDO TCK SA SA SA C SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A9 for 36Mb, A3 for 72Mb, A10 for 144Mb, A2 for 288Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.
4. MCL = Must Connect Low
5. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 2.01 3/2003 4/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Note: NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.
Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in
applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the
RAM’s bandwidth in half.
A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that
shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer
protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which
a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs
Pin Description Table
Symbol Description Type Comments
SA Synchronous Address Inputs Input —
NC No Connect — —
RSynchronous Read Input Active Low
WSynchronous Write Input Active Low
BW0–BW1 Synchronous Byte Writes Input Active Low
x18 Version
BW0–BW3 Synchronous Byte Writes Input Active Low
x36 Version
K Input Clock Input Active High
KInput Clock Input Active Low
C Output Clock Input Active High
COutput Clock Input Active Low
TMS Test Mode Select Input —
TDI Test Data Input Input —
TCK Test Clock Input Input —
TDO Test Data Output Output —
VREF HSTL Input Reference Voltage Input —
ZQ Output Impedance Matching Input Input —
MCL Must Connect Low — —
Q0–Q35 Synchronous Data Outputs Output x36 Version
D0–D17 Synchronous Data Inputs Input x18 Version
Q0–Q17 Synchronous Data Outputs Output x18 Version
VDD Power Supply Supply 2.5 V Nominal
VDDQ Isolated Output Buffer Supply Supply 1.5 V Nominal
VSS Power Supply: Ground Supply —
Rev: 2.01 3/2003 5/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the
same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from
differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application
at hand.
Alternating Read-Write Operations
SigmaQuad SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.
Rev: 2.01 3/2003 6/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Σ2x2B2 SigmaQuad SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read
cycle. Data can be clocked out one cycle later and again one half cycle after that. A high on the Read Enable-bar pin, R, begins a read port
deselect cycle.
Σ2x2B2 Double Data Rate SigmaQuad SRAM Read First
Dwg Rev. G
DC0 DC1 DE0 DE1 DG0 DG1
QB0 QB1
E
No Op Read Write Read Write
XX
K
/K
Address XX B C D
No Op
C
/C
D
Q
/R
/W
/BWx
WriteRead
GF
Rev: 2.01 3/2003 7/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Σ2x2B2 SigmaQuad SRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A low on the
Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising
edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write
address. A high on W causes a write port deselect cycle.
Σ2x2B2 Double Data Rate SigmaQuad SRAM Write First
Dwg Rev. G
DB0 DB1 DD0 DD1 DF0 DF1 DH0 DH1
/C
K
/K
D
Q
Read Write
AddressXXBCDE F
No Op Write Read Write
C
/R
/W
/BWx
WriteRead
H
QC0 QC1
G
Rev: 2.01 3/2003 8/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular
byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address
at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write
sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the
RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Resulting Write Operation
Output Register Control
SigmaQuad SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock
inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing
the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs
are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.
Data In Sample
Time BW0 BW1 D0–D8 D9–D17
Beat 1 0 1 Data In Don’t Care
Beat 2 1 0 Don’t Care Data In
Byte 1
D0–D8
Byte 2
D9–D17
Byte 3
D0–D8
Byte 4
D9–D17
Written Unchanged Unchanged Written
Rev: 2.01 3/2003 9/29 © 2002, Giga Semiconductor, Inc.
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Preliminary
GS8180Q18/36D-200/150/133/100
Example Four Bank Depth Expansion Schematic
A
K
R
W
A0–An
K
W0
D1–Dn
Bank 0 Bank 1 Bank 2 Bank 3
R0
D
A
K
W
D
A
K
W
D
A
K
W
D
RRR
QQQ Q
CC CC
Q1–Qn
C
W1
R1
W2
R2
W3
R3
Note: For simplicity BWn, K, and C are not shown.
Rev: 2.01 3/2003 10/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Σ2x2B2 SigmaQuad SRAM Depth Expansion
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external
resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between
150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may
move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary
Dwg Rev. G
DG0 DG1
DC0 DC1 DE0 DE1
/R2
/W1
CD HEFAddress XX B
K
/K
G
/R1
Q Bank 1 +
Q Bank 2
/C
Q
Bank 1
Write Read Write
- Bank 2 Bank 2 Bank 1 Bank 2 Bank 1 Bank 1
No Op Read Write Read
/W2
D
Bank 1
D
Bank 2
C
QD0
Q
Bank 2 QB0 QB1
QB0 QB1 QD0
Rev: 2.01 3/2003 11/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
weighted impedance steps. Impedance updates for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or
the SRAM is in HI-Z. The SRAM requires 32K start-up cycles, selected or deselected, after VDD reaches its operating range to reach its
programmed output driver impedance.
Σ2x2B2 Coherency and Pass Through Functions
Because the Σ2x2B2 read and write commands are loaded at the same time, there may be some confusion over what constitutes “coherent”
operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately after a write. This is true of the
Σ2x2B2 except in one case, as is illustrated in the following diagram. If the user holds the same address value in a given K clock cycle, loading
the same address as a read address and then as a matching write address, the Σ2x2B2 will read or “Pass-thru” the latest data input, rather than
the data from the previously completed write operation.
Σ2x2B2 Coherency and Pass Through Functions
Dwg Rev. G
DB0 DB1 DD0 DD1 DF0 DF1 DH0 DH1 DI0
QA0 QA1 QC0 QC1 QE0 QE1
71
WriteRead
OOIO
56
OI
3
Write Read Write
C
/R
/W
/BWx
Read Write
Address OO OI OI OO OO OO
Read
K
/K
D
Q??
5
/C
4682719
HIABCDEFG
COHERENT PASS- THRU
Rev: 2.01 3/2003 12/29 © 2002, Giga Semiconductor, Inc.
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Preliminary
GS8180Q18/36D-200/150/133/100
Separate I/O Σ2x2B2 SigmaQuad SRAM Read Truth Table
Separate I/O Σ2x2B2 SigmaQuad SRAM Write Truth Table
AR Output Next State Q Q
K ↑
(tn)
K ↑
(tn)
K ↑
(tn)
K ↑
(tn+1)
K ↑
(tn+1½)
X 1 Deselect Hi-Z Hi-Z
V 0 Read Q0 Q1
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
AWBWn BWn Input Next State D D
K ↑
(tn + ½)
K ↑
(tn)
K ↑
(tn)
K ↑
(tn + ½)
K ↑, K ↑
(tn), (tn + ½)
K ↑
(tn)
K ↑
(tn + ½)
V 0 0 0 Write Byte Dx0, Write Byte Dx1 D0 D1
V 0 0 1 Write Byte Dx0, Write Abort Byte Dx1 D0 X
V 0 1 0 Write Abort Byte Dx0, Write Byte Dx1 X D1
X 0 1 1 Write Abort Byte Dx0, Write Abort Byte Dx1 X X
X1XX Deselect X X
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
Rev: 2.01 3/2003 13/29 © 2002, Giga Semiconductor, Inc.
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Preliminary
GS8180Q18/36D-200/150/133/100
x36 Byte Write Enable (BWn) Truth Table
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35
1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care
0 1 1 1 Data In Don’t Care Don’t Care Don’t Care
1 0 1 1 Don’t Care Data In Don’t Care Don’t Care
0 0 1 1 Data In Data In Don’t Care Don’t Care
1 1 0 1 Don’t Care Don’t Care Data In Don’t Care
0 1 0 1 Data In Don’t Care Data In Don’t Care
1 0 0 1 Don’t Care Data In Data In Don’t Care
0 0 0 1 Data In Data In Data In Don’t Care
1 1 1 0 Don’t Care Don’t Care Don’t Care Data In
0 1 1 0 Data In Don’t Care Don’t Care Data In
1 0 1 0 Don’t Care Data In Don’t Care Data In
0 0 1 0 Data In Data In Don’t Care Data In
1 1 0 0 Don’t Care Don’t Care Data In Data In
0 1 0 0 Data In Don’t Care Data In Data In
1 0 0 0 Don’t Care Data In Data In Data In
0 0 0 0 Data In Data In Data In Data In
BW0 BW1 D0–D8 D9–D17
1 1 Don’t Care Don’t Care
0 1 Data In Don’t Care
1 0 Don’t Care Data In
0 0 Data In Data In
Rev: 2.01 3/2003 14/29 © 2002, Giga Semiconductor, Inc.
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Preliminary
GS8180Q18/36D-200/150/133/100
State Diagram
Power-Up
Read NOP
Load New
Read Address
DDR Read
Write NOP
Load New
Write Address
DDR Write
WRITE
READ
READ WRITE
READ WRITE
Always
(Fixed)
Always
(Fixed)
READ WRITE
Notes:
1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.
2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is true for “WRITE” and
“WRITE”.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
Rev: 2.01 3/2003 15/29 © 2002, Giga Semiconductor, Inc.
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Preliminary
GS8180Q18/36D-200/150/133/100
Recommended Operating Conditions
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 2.9 V
VDDQ Voltage in VDDQ Pins –0.5 to VDD V
VREF Voltage in VREF Pins –0.5 to VDDQ V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V
IIN Input Current on Any Pin +/–100 mA dc
IOUT Output Current on Any I/O Pin +/–100 mA dc
TJMaximum Junction Temperature 125 oC
TSTG Storage Temperature –55 to 125 oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Power Supplies
Parameter Symbol Min. Typ. Max. Unit Notes
Supply Voltage VDD 1.7 1.8 1.9 V
1.8 V I/O Supply Voltage VDDQ 1.7 1.8 1.95 V 1
1.5 V I/O Supply Voltage VDDQ 1.4 1.5 1.6 V 1
Ambient Temperature
(Commercial Range Versions) TA02570°C2
Ambient Temperature
(Industrial Range Versions) TA–40 25 85 °C2
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O)
and 1.7 V ≤ VDDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The
power down sequence must be the reverse. VDDQ must not exceed VDD.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number
of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
Rev: 2.01 3/2003 16/29 © 2002, Giga Semiconductor, Inc.
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Preliminary
GS8180Q18/36D-200/150/133/100
HSTL I/O AC Input Definitions
HSTL I/O DC Input Characteristics
Parameter Symbol Min Max Units Notes
DC Input Logic High VIH (dc) VREF + 200 mV 1
DC Input Logic Low VIL (dc) VREF – 200 mV 1
VREF DC Voltage VREF (dc) VDDQ (min)/2 VDDQ (max)/2 V1
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers
HSTL I/O AC Input Characteristics
Parameter Symbol Min Max Units Notes
AC Input Logic High VIH (ac) VREF + 400 mV 3,4
AC Input Logic Low VIL (ac) VREF – 400 mV 3,4
VREF Peak to Peak AC Voltage VREF (ac) 5% VREF (DC) mV 1
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
4. See AC Input Definition drawing below.
VIH (ac)
VREF
VIL (ac)
Rev: 2.01 3/2003 17/29 © 2002, Giga Semiconductor, Inc.
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Preliminary
GS8180Q18/36D-200/150/133/100
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 45pF
Output Capacitance COUT VOUT = 0 V 67pF
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single RΘJA TBD °C/W 1,2
Junction to Ambient (at 200 lfm) four RΘJA TBD °C/W 1,2
Junction to Case (TOP) — RΘJC TBD °C/W 3
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature,
ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
AC Test Conditions
Parameter Conditions
Input high level VDDQ
Input low level 0 V
Max. input slew rate 2 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
Notes: Test conditions as specified with output loading as shown unless otherwise noted.
20% tKHKH
V
SS – 1.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKHKH
VDD + 1.0 V
50%
VDD
VIL
Rev: 2.01 3/2003 18/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
AC Test Load Diagram
Input and Output Leakage Characteristics
Parameter Symbol Test Conditions Min. Max Notes
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA
Mode Pin Input Current IINM
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–2 uA
2 uA
2 uA
Output Leakage Current IOL
Output Disable,
VOUT = 0 to VDDQ –2 uA 2 uA
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter Symbol Min. Max. Units Notes
Output High Voltage VOH1 V
DDQ/2 VDDQ V 1, 3
Output Low Voltage VOL1 Vss VDDQ/2 V 2, 3
Output High Voltage VOH2 V
DDQ – 0.2 VDDQ V 4, 5
Output Low Voltage VOL2 Vss 0.2 V 4, 6
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. Minimum Impedance mode, ZQ = VSS
5. IOH = –1.0 mA
6. IOL = 1.0 mA
DQ
VT = VDDQ/2
50Ω
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
Rev: 2.01 3/2003 19/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Operating Currents
Parameter Org Symbol
-200 -150 -133 -100
Test Conditions
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
Operating
Current x18
IDD 460 mA TBD 400 mA TBD 340 mA TBD 280 mA TBD R and W ≤ VIL Max.
tKHKH ≥ tKHKH Min.
All other inputs
VIN ≤ VIL Max. or VIN ≥ VIH Min.
IDDQ 55 mA TBD 45 mA TBD 40 mA TBD 35 mA TBD
Operating
Current x36
IDD 525 mA TBD 440 mA TBD 380 mA TBD 320 mA TBD R and W ≤ VIL Max.
tKHKH ≥ tKHKH Min.
All other inputs
VIN ≤ VIL Max. or VIN ≥ VIH Min.
IDDQ 110 mA TBD 95 mA TBD 75 mA TBD 65 mA TBD
Chip
Disable
Current
x18
ISB1 130 mA TBD 120 mA TBD 115 mA TBD 110 mA TBD R and W ≥ VIH Min.
tKHKH ≥ tKHKH Min.
All other inputs
VIN ≤ VIL Max. or VIN ≥ VIH Min.
ISBQ1 5 mA TBD 5 mA TBD 5 mA TBD 5 mA TBD
Chip
Disable
Current
x36
ISB1 155 mA TBD 145 mA TBD 140 mA TBD 135 mA TBD R and W ≥ VIH Min.
tKHKH ≥ tKHKH Min.
All other inputs
VIN ≤ VIL Max. or VIN ≥ VIH Min.
ISBQ1 5 mA TBD 5 mA TBD 5 mA TBD 5 mA TBD
Note: Power measured with output pins floating.
Rev: 2.01 3/2003 20/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
AC Electrical Characteristics
Parameter Symbol -200 -150 -133 -100 Units Notes
Min Max Min Max Min Max Min Max
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
5.0 — 6.7 — 7.5 — 10 — ns
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
2.0 — 2.7 — 3.0 — 3.5 — ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
2.0 — 2.7 — 3.0 — 3.5 — ns
K Clock High to K Clock High
C Clock High to C Clock High
tKHKH
tCHCH
2.2 — 3.0 — 3.4 — 4.5 — ns 4
K Clock High to K Clock High
C Clock High to C Clock High
tKHKH
tCHCH
2.2 — 3.0 — 3.4 — 4.6 — ns
K, K Clock High to C, C Clock High tKHCH 0 1.7 0 2.2 0 2.5 0 3.0 ns
Address Input Setup Time tAVKH 0.6 — 0.7 — 0.8 — 1.0 — ns
Address Input Hold Time tKHAX 0.6 — 0.7 — 0.8 — 1.0 — ns
Control Input Setup Time tBVKH 0.6 — 0.7 — 0.8 — 1.0 — ns 1
Control Input Hold Time tKHBX 0.6 — 0.7 — 0.8 — 1.0 — ns 1
Data and Byte Write Input Setup Time tDVKH 0.6 — 0.7 — 0.8 — 1.0 — ns
Data and Byte Write Input Hold Time tKHDX 0.6 — 0.7 — 0.8 — 1.0 — ns
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
— 2.2 — 2.7 — 3.0 — 3.0 ns
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
1.0 — 1.2 — 1.2 — 1.2 — ns 2
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
1.0 — 1.2 — 1.2 — 1.2 — ns 2,3
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
— 2.2 — 2.7 — 3.0 — 3.0 ns 2,3
Notes:
1. These parameters apply to control inputs R and W.
2. These parameters are guaranteed by design and characterization. Not 100% tested.
3. These parameters are measured at ±50mV from steady state voltage.
4. tKHKH Max is specified by tKHKH Min. tCHCH Max is specified by tCHCH Min.
Rev: 2.01 3/2003 21/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
K and K Controlled Read-Write-Read Timing Diagram
A4 A5 A6
K
K
A
R
Q
tKHAX
tAVKH
tKHBX
tBVKH
tKHKH tKHKL tKLKH
Read Write Read Deselect Read Write Deselect Write Read Write Deselect
A2 A3
W
A7
D
tKHDX
tDVKH
D21 D50 D60
D51 D61 D80
A8A1
tKHQX1
tKHQZ
tKHQV
tKHQX
Q10 Q11 Q30 Q31 Q40 Q41
BWn
D20 D81
tKHQV
tKHQX
tKHAX
tAVKH
tKHBX
tBVKH
tKHDX
tDVKH
tKHKHtKHKH
Rev: 2.01 3/2003 22/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
C and C Controlled Read-Write-Read Timing Diagram
A4 A5 A6
K
K
A
R
Read Write Read Deselect Read Write Deselect Write Read Write Deselect
A2 A3
W
A7
D
A8A1
BWn
D21 D50 D60D51 D61 D80D20 D81
Q
tCHQX1
tCHQZ
tCHQV
tCHQX
Q10 Q11 Q30 Q31 Q40 Q41
tCHQV
tCHQX
C
C
tKHCH
tCHCH tCHCL tCLCH
tKHCH
tCHCHtCHCH
Rev: 2.01 3/2003 23/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard
(commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI,
and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may
be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Port Registers
Overview
The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s
applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK
and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various
data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The
Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset
state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s
JTAG Port to another device in the scan chain with as little delay as possible.
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS Test Mode Select In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI Test Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO Test Data Out Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
Rev: 2.01 3/2003 24/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are
then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also
includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan
Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the
contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is
moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with
the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the
register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31302928272625242322212019181716151413121110987654321 0
x36 XXXX0000100100001000000110110011
x18 XXXX0000100100001010000110110011
Instruction Register
ID Code Register
Boundary Scan Register
012
012
····
31 30 29
012
···
······
n
0
Bypass Register
TDI TDO
TMS
TCK Test Access Port (TAP) Controller
Rev: 2.01 3/2003 25/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed
ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the
RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the
controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially
loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
110
0
0
1
11
1
Rev: 2.01 3/2003 26/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 2.01 3/2003 27/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z. 1
RFU 011 Do not use this instruction; Reserved for Future Use. 1
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1
RFU 101 Do not use this instruction; Reserved for Future Use. 1
RFU 110 Do not use this instruction; Reserved for Future Use. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
Test Port Input High Voltage VIHJ 0.6 * VDD VDD +0.3 V1
Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V1
TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2
TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3
TDO Output Leakage Current IOLJ –11uA4
Test Port Output High Voltage VOHJ VDD – 400 mV —V5, 6
Test Port Output Low Voltage VOLJ —0.4 V 5, 7
Test Port Output CMOS High VOHJC VDD – 100 mV —V5, 8
Test Port Output CMOS Low VOLJC —100 mV V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V not to exceed 2.6 V maximum, with a pulse width not to
exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDD
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDD
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
Rev: 2.01 3/2003 28/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
JTAG Port Timing Diagram
JTAG Port AC Electrical Characteristics
Parameter Symbol Min. Max Unit
TCK Cycle Time tTKC 50 — ns
TCK Low to TDO Valid tTKQ — 20 ns
TCK High Pulse Width tTKH 20 — ns
TCK Low Pulse Width tTKL 20 — ns
TDI & TMS Set Up Time tTS 10 — ns
TDI & TMS Hold Time tTH 10 — ns
Notes:
1. Distributed scope and test jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level VDD
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDD/2
DQ
VT = VDD/2
50Ω30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
tTKQ
tTS tTH
tTKH tTKL
TCK
TMS
TDI
TDO
tTKC
Rev: 2.01 3/2003 29/29 © 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180Q18/36D-200/150/133/100
Ordering Information—GSI SigmaQuad SRAM
Org Part Number1Type Package Speed
(MHz) TA3
512Kx 36 GS8180Q36D-200 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 200 C
512Kx 36 GS8180Q36D-150 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 150 C
512Kx 36 GS8180Q36D-133 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 133 C
512Kx 36 GS8180Q36D-100 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 100 C
512Kx 36 GS8180Q36D-200I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 200 I
512Kx 36 GS8180Q36D-150I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 150 I
512Kx 36 GS8180Q36D-133I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 133 I
512Kx 36 GS8180Q36D-100I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 100 I
1M x 18 GS8180Q18D-200 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 200 C
1M x 18 GS8180Q18D-150 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 150 C
1M x 18 GS8180Q18D-133 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 133 C
1M x 18 GS8180Q18D-100 SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 100 C
1M x 18 GS8180Q18D-200I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 200 I
1M x 18 GS8180Q18D-150I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 150 I
1M x 18 GS8180Q18D-133I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 133 I
1M x 18 GS8180Q18D-100I SigmaQuad SRAM 1 mm Pitch, 165-Pin BGA 100 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example:
GS818x36D-200T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
