RX5500 - RFM - Datasheet.Directory

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• Designed for Short-Range Wireless Control Applications

• 3 V, Low Current Operation plus Sleep Mode

• Characterized for Automotive Applications

• High EMI Rejection Capability

• Complies with Directive 2002/95/EC (RoHS)

The RX5500 hybrid receiver is ideal for short-range wireless control applications where robust operation,

small size, low power consumption and low cost are required. The RX5500 employs RFM’s amplifier-

sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions

are contained in the hybrid, simplifying and speeding design-in. The RX5500 is sensitive and stable. A wide

dynamic range log detector provides robust performance in the presence of on-channel interference or noise.

Two stages of SA W filtering provide excellent receiver out-of-band rejection. The RX5500 generates virtually

no RF emissions, facilitating compliance with ETSI I-ETS 300 220 and similar regulations.

Absolute Maximum Ratings

Rating Value Units

Power Supply and All Input/Output Pins -0.3 to +4.0 V

Non-Operating Case Temperature -50 to +100 °C

Soldering Temperature (10 seconds / 5 cycles max.) 260 °C

433.92 MHz

Hybrid

Receiver

RX5500

SM-20L Case

Electrical Characteristics

Characteristic Sym Notes Minimum Typical Maximum Units

Operating Frequency fo433.72 434.12 MHz

Modulation Types OOK & ASK

Data Rate 19.2 kbps

Receiver Performance, High Sensitivity Mode

Sensitivity, 1.2 kbps, 10-3 BER, AM Tes t Method 1 - 110.5 dBm

Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Meth od 1 -104.5 dBm

Current, 1.2 kbps (RPR = 330 K) 22.9mA

Sensitivity, 2.4 kbps, 10-3 BER, AM Tes t Method 1 -109 dBm

Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Meth od 1 -103 dBm

Current, 2.4 kbps (RPR = 330 K) 23.0mA

Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method 1 -105 dB m

Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method 1 -99 dBm

Current, 19.2 kbps 3.1 mA

Receiver Performance, Low Current Mode

Sensitivity, 1.2 kbps, 10-3 BER, AM Tes t Method 1 -104 dBm

Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Meth od 1 -98 dBm

Current, 1.2 kbps (RPR = 2000 K) 21.65mA

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Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 °C)

Characteristic Sym Notes Minimum Typical Maximum Units

Receiver Out-of-Band Rejection, ± 5% fo R±5% 380dB

Receiver Ultimate Rejection RULT 3 100 dB

Sleep Mode Current IS0.7 µA

Power Supply Volt age Range VCC 2.2 3.7 Vdc

Power Supply Voltage Ripple 10 mVP-P

Ambient Operating Temperature TA-40 85 °C

1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are t wo tes t methods commonly used to measure OOK/ASK

receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both te st methods. See Appendix 3.8 in the ASH

Transceiver Designer’s Guide for the details of each test method, and for sensit ivity curves for a 2.2 to 3.7 V supply voltage range at five operating

temperatures. The app lication/tes t c i rcuit and component values are sho w n on the next pa ge and in the Designer’s Guide.

2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivit y for lower operating current. Sensit ivity data and receiver

current are given at 1.2 kbps for both high sensitivity operation (RPR = 330 K) and low current operation (RPR = 2000 K).

3. Data is gi ven with the ASH radio matched to a 50 ohm load. Matching component value s are given on the next page.

4. See Table 1 on Page 8 f or additional information on ASH radio event timing.

Dimension mm Inches

Min Nom Max Min Nom Max

A 10.795 10.922 11.049 .425 .430 .435

B 9.525 9.652 9.779 .375 .380 .385

C 1.778 1.905 2.032 .070 .075 .080

D 3.048 3.175 3.302 .120 .125 .130

E 0.381 0.508 0.635 .015 .020 .025

F 0.889 1.016 1.143 .035 .040 .045

G 3.175 3.302 3.429 .125 .130 .135

H 1.778 1.905 2.032 .070 .075 0.80

ASH Transcei ver Pin Out

RFIO

201

LPFADJ

RREF

THLD2

AGCCAP

PKDET

BBOUT

CMPIN

RXDATA

TXMOD THLD1

PRATE

PWIDTH

GND1

VCC1

GND2

VCC2

GND3

CNTRL0

CNTRL1

SM-20L Package Drawing

CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.

Notes:

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Data Output

TOP VIEW

GND

3CNT

RL0 CNT

RL1 P

WIDTH P

RATE THLD

1NC

RREF

GND2

DATA LPF

ADJ

CMP

OUT

DET

VCC

RFIO

GND1

+ 3

VDC

ASH Receiver Application Circuit

OOK Configuration

23456789

1213141516171819

+ 3

VDC

RPW RPR

RTH1

RREF

RLPF

CBBO

CDCB

LAT

LESD

CRFB1

R/S

CLPF

RBBO

Receiver Set-Up, 3.0 Vdc, -40 to +85 °C

Item Symbol OOK OOK ASK Units Notes

Nominal NRZ Data Rate DRNOM 1.2 2.4 19.2 kbps see page 1& 2

Minimum Signal Pulse SPMIN 833.33 416.67 52. 08 µs single bit

Maximum Signal Pulse SPMAX 3333.33 1666.68 208.32 µs 4 bits of same value

BBOUT Capacitor CBBO 0.2 0.1 0.015 µF ±10% ceramic

BBOUT Resistor RBBO 12 12 0 K ±5%

LPFAUX Capacitor CLPF 0.01 0.0047 - µF ±5%

LP FADJ Resistor RLPF 330 300 100 K ±5%

RREF Resistor RREF 100 100 100 K ±1%

TH LD1 Re sistor RTH1 0 0 0 K ±1%, typical values

PRATE Resistor RPR 330 330 330 K ±5%

PWIDTH Resi stor RPW 270 to GND 270 to GND 270 to GND K ±5%

DC Bypass Capacitor CDCB 4.7 4.7 4.7 µF tantalum

RF Bypass Capacitor 1 CRFB1 100 100 100 pF ±5% NPO

Antenna T uning Inductor LAT 56 56 56 nH 50 ohm antenna

Shunt T uning/ESD Inductor LESD 220 220 220 nH 50 ohm antenna

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ASH Receiv er Block Diagr am & Timing Cycle

Antenna

Pulse

Generator

SAW

Delay Line

SAW Filter RFA1 RFA2 Data

Out

Detector &

Low-Pass

Filter

RF Data Pulse

P1 P2

RFA1 Out

RF Input

Delay Line

Out

tPW2

tPW1 tPRI

tPRC

Figure 1

ASH Receiver Theory of Operation

Introduction

RFM’s RX5500 series amplifier-sequenced hybrid (ASH) receivers

are speci fical ly d esigned for s hor t-range wirele ss c ontrol and data

communication applications. The receivers provide robust

operation, very small size, low power consumption and low

implementation cost. All critical RF functions are contained in the

hybrid, simplifying and speeding design-in. The ASH receiver can

be readil y configured to support a wide range of data rates and

protocol requirements. The receiver features virtually no RF

emissions, making it easy to certify to short-range (unlicensed)

radio regulations.

Amplifier-Sequenced Receiver Operation

The ASH receiver’s unique feature set is made possible by its

system architecture. The heart of the receiver is the amplifier-

sequenced receiver section, which provides more than 100 dB of

stable RF and detector gain without any special shielding or

decoupl ing provisi ons. Stability is achieved by distributi ng the total

RF gain over time. This is in contrast to a superheterodyne

receive r, which ach ieves sta bility by dis tributing to tal RF gain ov er

multiple frequencies.

Figure 1 shows the basic block diagram and timing cycle for an

amplifier-sequenced receiver. Note that the bias to RF amplifiers

RFA1 and RFA2 are independently controlled by a pulse

generator, and that the two amplifiers are coupled by a surface

acoustic wave (SAW) delay line, which has a typical delay of

0.5 µs.

An incom ing RF sig nal is first fi ltered by a narrow-ba nd SAW filte r,

and is then app lied to RFA1. The pu lse g ene rato r tu rns R FA1 O N

for 0.5 µs. Th e amplified signal from RFA1 emerges from the SAW

delay line at the input to RFA2. RFA1 is now switched OFF and

RFA2 is switc hed ON for 0.5 5 µs, amplifying th e RF signal f urther.

The ON time for RFA2 is usually set at 1.1 times the ON time for

RFA1, as the filtering effect of the SAW delay line stretches the

signal pulse from RFA1 somewhat. As shown in the timing

diagr am, RFA1 and RF A2 are never on a t the same time, assu ring

excellent receiver stability. Note that the narrow-band SAW filter

eliminates sampling sideband responses outside of the receiver

passband, and the SAW filter a nd delay line act together to provide

very high receiver ultimate rejection.

Amplifier-sequenced receiver operation has several interesting

characteristics that can be exploited in system design. The RF

amplifiers in an amplifier-sequenced receiver can be turned on and

off almost instantly, allowing for very quick power-down (sleep)

and wake-up times. Also, both RF amplifiers can be off between

ON seque nces to trade- off rece iver no ise fi gure for l ower averag e

current consumption. The effect on noise figure can be modeled as

if RFA1 is on continuously, with an attenuator placed in front of it

with a loss equivalent to 10*log10(RFA1 duty factor), where the

duty f actor is the aver age amount of t ime RFA1 is ON (up to 50%).

Since an ampli fie r-sequenced rec eiv er is inh erently a samp lin g

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Figure 2

receive r, the ov erall cycl e time betwe en the start of one R FA1 ON

sequenc e an d the sta rt o f th e next RF A1 O N sequen ce s hou ld be

set to sample the narrowest RF data pulse at least 10 times.

Otherwise, significant edge jitter will be added to the de tected data

pulse.

RX5500 Series ASH Receiver Block Diagram

Figure 2 is the general block diagram of the RX5500 series ASH

receiver. Please refer to Figure 2 for the following discussions.

Antenna Port

The only ex ternal R F compo nents neede d for the rece ive r are the

antenna and its matching components. Antennas presenting an

impedance in the range of 35 to 72 ohms resistive can be

satisfactorily matched to the RFIO pin with a series matching coil

and a shunt matching/ESD protection coil. Other antenna

impedances can be matched using two or three components. For

some im pedances , two ind uctors and a capaci tor wil l be requir ed.

A DC path from RFIO to ground is required for ESD protection.

Receiver Chain

The output of the SAW filter drives amplifier RFA1. The output of

RFA1 dri ves the S AW dela y line, whi ch has a nominal delay o f 0.5

µs.

The second amplifier, RFA2, provides 51 dB of gain below

saturati on. The o utput of R FA2 drives a full-w ave detector with 19

dB of threshold gain. The onset of saturation in each section of

RFA2 is detec ted and summed t o pro vide a lo garit hmic res ponse .

This is added to the output of the full-wave detector to produce an

overall detector response that is square law for low signal levels,

and transitions into a log response for high signal levels. This

combination provides excellent threshold sensitivity and more than

70 dB of dete ctor dynam ic range. In combin ation with the 30 dB of

AGC range in RFA1, more tha n 100 dB of rece iver dynamic range

is achieved.

The detector output drives a gyrator filter. The filter provides a

three-pole, 0.05 degree equiripple low-pass response with

excellent group delay flatness and minimal pulse ringing. The 3 dB

bandwi dth of the fil ter c an b e se t from 4.5 kH z to 1.8 MHz w ith a n

external resistor.

The filter is followed by a base-band amplifier which boosts the

detected signal to the BBOUT pin. When the receiver RF amplifiers

are operating at a 50%-50% duty cycle, the BBOUT signal

changes about 10 mV/dB, w ith a peak-to-pe ak signal le vel of up to

685 mV. Fo r lower duty cy cles, the mV/dB slope and pe ak-to-peak

signal level are proportionately less. The detected signal is riding

on a 1.1 Vdc level that varies somewhat with supply voltage,

temperature, etc. BBOUT is coupled to the CMPIN pin or to an

external data recovery process (DSP, etc.) by a series capacitor.

The correct value of the series capacitor depends on data rate,

data run length, and other factors as discussed in the ASH

Transceiver Designer’s Guide .

When the rec eiv er i s pl ace d in the po w er-do wn (sl ee p) mode, the

output impedance of BBOUT becomes very high. This feature

helps preserve the charge on the coupling capacitor to minimize

data slic er stabil izati on time when the receiv er swi tches out of the

sleep mode.

Data Slicers

The CMPIN pin drives data slicer DS1, which convert the analog

signal from BBOUT b ack into a digital st ream. Da ta slicer DS1 is a

capaci tiv ely -c oup led co mparator with provi si ons for an adjustable

threshold. The threshold, or squelch, offsets the comparator’s

slicin g level from 0 to 90 mV, and is se t with a resistor b etween the

RX5500 Series ASH Receiver Block Diagram

RFA1 RFA2

SAW

Delay Line

SAW

CR Filter

Log

Antenna

RFIO

ESD

Choke

Detector Low-Pass

Filter BB

Pulse Generator

& RF Amp Bias

LPFADJ

PRATE PWIDTH

RXDATA

CNTRL1 CNTRL0

RREF

THLD1

Bias Control

Power

Down

Control

Threshold

Control

BBOUT

DS1

Ref Thld

CBBO

RLPF

RPR RPW

RTH1

17 18

14 15

VCC1: Pin 2

VCC2: Pin 16

GND1: Pin 1

GND2: Pin 10

GND3: Pin 19

NC: Pin 8

RREF: Pin 11

CMPIN: Pin 6

NC: Pin 4

NC: Pin 12

RFA1

11 RREF

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RREF and THLD1 pins . This thresh old a llows a trade-o ff betw een

receiver sensitivity and output noise density in the no-signal

condition. For be st sensitivity, the thre shold is set to 0. In this case,

noise is output continuously when no signal is present. This, in

turn, requires the circuit being driven by the RXDATA pin to be able

to process noise (and signals) conti nuously.

This can be a problem if RXDATA is driving a circuit that must

“sleep” whe n da ta is no t pres en t to c ons erv e po wer, o r wh en i t its

necess ary to minim ize false inte rrupts to a multi tasking proc essor.

In this case, noise can be greatly reduced by increasing the

threshold level, but at the expense of sensitivity. The best 3 dB

bandwidth for the low-pass filter is also affected by the threshold

level setting of DS1. The bandwidth must be increased as the

threshol d is increa sed to min imize data pu lse-width variations wi th

signal amplitude.

Receiver Pulse Generator and RF Amplifier Bias

The receiver amplifier-sequence operation is controlled by the

Pulse Generator & RF Amplifier Bias module, which in turn is

controlled by the PRATE and PWIDTH input pins, and the Power

Dow n (sleep) C ontrol Signal from the B ias Co ntro l function.

In the low da ta rate mode, t he interval be tween the fallin g edge of

one RFA1 ON puls e to the rising edge of the ne xt RFA1 ON pulse

tPRI is set by a res istor between th e PRATE pi n an d gro und . The

interval can be adjusted between 0.1 and 5 µs. In the high data rate

mode (selected at the PWIDTH pin) the receiver RF amplifiers

operate at a nominal 50%-50% duty cycle. In this case, the start-

to-start period tPRC for ON pulses to RFA1 are controlled by the

PRATE resistor over a range of 0.1 to 1.1 µs.

In the low data rate mode, the PWIDTH pin sets the width of the

ON pulse tPW1 to RFA1 with a resistor to ground (the ON pulse

width tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in

the low data rate mode). The O N pulse w idth tPW1 can be adjusted

between 0.55 and 1 µs. However, when the PWIDTH pin is

connected to Vcc through a 1 M resistor, the RF amplifie rs operate

at a nominal 50%-50% duty cycle, facilitating high data rate

operation. In this case, the RF amplifiers are controlled by the

PRATE resistor as described above.

Both receiver RF amplifiers are turned off by the Power Down

Control Signal, which is invoked in the sleep mode.

Receiver Mode Control

The rec eiv er op erating mod es – re cei ve a nd po w er-d own (sleep),

are controlled by the Bias Control function, and are selected with

the CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and

CNTRL0 both high place the unit in the receive mode. Setting

CNTRL1 and CNTRL0 both low place the unit in the power-down

(sleep) mode. CNTRL1 and CNTRL0 are CMOS compatible

inputs. These inputs must be held at a logic level; they cannot be

left unconnected.

Receiver Ev ent Ti ming

Receiver event timing is summarized in Table 1. Please refer to

this table for the following discussions.

Turn-On Timing

The maximum time tPR required for the receive function to become

operational at turn on is influe nced by tw o facto rs. All receiv er

circuitry will be operational 5 ms after the supply voltage reaches

2.2 Vdc. The BBOUT -CMPIN cou pl ing -ca pac ito r is then DC

stab ilized in 3 time co nstants (3*tBBC). The to tal turn-on time to

stable receiver operation for a 10 ms power supply rise time is:

tPR = 15 ms + 3*tBBC

Sleep and Wake-Up Timing

The maximum transitio n time from the receive mo de to the power-

down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0 are

both low (1 µs fall time).

The maximum transition time tSR from the sleep mode to the

receive mode is 3*tBBC, where tBBC is the BBOUT-CMPIN

coupling-capacitor time constant. When the operating temperature

is limited to 60 °C, the time required to switch from sleep to receive

is dramatically less for short sleep times, as less charge leaks

away from the BBOUT- CMPIN coupling capacitor.

Pulse Generator Timing

In the low data rate mode, the interval tPRI between the falling edge

of an ON pulse to the first RF amplifier and the rising edge of the

next ON pulse to the first RF amplifier is set by a resistor RPR

between the PRATE pin a nd ground. Th e interval can be adju sted

between 0.1 and 5 µs with a resistor in the range of 51 K to 2000

K. The value of the RPR is given by:

RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms

In the high data rate mode (selected at the PWIDTH pin) the

receiver RF amplifiers operate at a nominal 50%-50% duty cycle.

In this case, the period tPRC from the start of an ON pulse to the

first RF amplifier to the start of the next ON pulse to the first RF

amplifie r is cont rolled by the PRATE resi stor over a range of 0.1 to

1.1 µs using a resistor of 11 K to 220 K. In this case RPR is given

by:

RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms

In the low data rate mode, the PWIDTH pin sets the width of the

ON pulse to the first RF amplifier tPW1 with a resistor RPW to

ground (t he ON pul se width to the se cond R F amp lifier tPW2 is set

at 1.1 tim es t he pul se w idth to the first RF amp lifier in th e low d ata

rate mode). The ON pulse width tPW1 can be adjusted between

0.55 and 1 µs with a re sis tor value in the range of 200 K to 390 K.

The value of RPW is given by:

RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms

However, when the PWIDTH pin is connected to Vcc through a 1

M resistor, the RF amplifiers operate at a nominal 50%-50% duty

cycle, facilitating high data rate operation. In this case, the RF

amplifiers are controlled by the PRATE resistor as described

above.

LPF Group Delay

The low-pass filter group delay is a function of the filter 3 dB

bandwidth, which is set by a resistor RLPF to ground at the LPFADJ

pin. The m inimum 3 dB bandwid th fLPF = 1445/RLPF, where fLPF is

in kHz, and RLPF is in kilohm s.

The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where

tFGD is in µs, fLPF in kHz, and RLPF in kiloh ms .

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Receiver Event Timing, 3.0 Vdc, -40 to +85 °C

Event Symbol Time Min/

Max Test Conditions Notes

Turn On to Receive tPR 3*tBBC + 15 ms max 10 ms supply voltage rise time time until receiver operational

Sleep to RX tSR 3*tBBC max 1 µs CNTRL0/CNTROL 1 rise

times time until receiver operational

RX to Sleep tRS 10 µs max 1 µs CNTRL0/CNTROL 1 fall times time until receiver is in power-down mode

PRATE Interval tPRI 0.1 to 5 µs range low data rate mode user selected mode

PWIDT H R FA1 tPW1 0.55 to 1 µs range low data rate mode user selected mode

PWIDT H R FA2 tPW2 1.1*tPW1 range low data rate mode user selected mode

PRATE Cycle tPRC 0.1 to 1.1 µs range high data rate mode user selected mode

PWIDTH Hi gh (RFA1 & RFA2) tPWH 0.05 to 0.55 µs rang e high data rate mode user selected mode

LPF Group Delay tFGD 1750/fLPF max tFGD i n µs, fLPF in kHz user selected

LPF 3 dB Bandwidth fLPF 1445/RLPF min fLPF in kHz, RLPF in kilohms user selected

BBOUT-CMPIN Time Constant tBBC 0.064*CBBO min tBBC i n µ s, CBBO in pF user selected

Table 1

Pin Descriptions

Pin Name Description

1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.

2 VCC1 VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF capacitor,

which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.

3RFA1

4 NC This pin should be left unconnected.

5BBOUT

BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for internal

data slicer operation. The time constant tBBC for this connect ion is:

tBBC = 0.064*CBBO , where tBBC is in µs and CBBO is in pF

A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC and

1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend

on the data rate, data run length, and other factors as discussed in the ASH T ransceiver Designer’s Guide. A common criteria

is to set the time constant for no more than a 20% voltage droop during SPMAX. For this case:

CBBO = 70*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in pF

The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output imped-

ance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes

about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak

signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply volt-

age and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in

parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must

be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function

is driven by the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin

becomes very high, preserving the charge on the coupling capacitor.

6CMPIN

This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of

this pin is 70 K to 100 K.

7RXDATA

RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this

pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin becomes high

impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin is

high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than Vcc +

200 mV.

8 NC This pin may be left unconnected or may be grounded.

9LPFADJ

This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this pin and

ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from 4. 5 kHz to 1.8 MHz.

The resistor value is determined by:

RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz

A ± 5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF and 1.3* fLPF

with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response.

The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting.

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Pin Name Description

10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

11 RREF

RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%

resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less

than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less

that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.

12 NC This pin should be left unconnected.

13 THLD1

The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is

increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The acceptable

range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:

RTH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV

A ±1% resistor tolerance is recommended for the THLD1 resistor.

14 PRATE

The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the

first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be adjusted between 0.1 and

5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by:

RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms

A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers

operate at a nominal 50%-50% duty cycle, facilitating high dat a rate operation. In t his case, the period tPRC from start-to-start

of ON pulses to t he f irst RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K

to 220 K. In this case the value of RPR is given by:

RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms

A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional

amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5

pF to maintain stability.

15 PWIDTH

The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON pulse

width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width tPW1

can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of RPW is given by:

RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms

A ± 5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at

a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by

the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to

less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor

between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.

16 VCC2 VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which

may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor.

17 CNTRL1

CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode.

CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS

compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is inter-

preted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a

maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic

level; it cannot be left unconnected.

18 CNTRL0

CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An

input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic

high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source

current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left

unconnected.

19 GND3 GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

20 RFIO

RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presentin g an imped-

ance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt

matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some imped-

ances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection.

www.RFM.com E-mail: info@rfm.com Page 9 of 9

0.000

.140

.270

.410

.0775

.1025

.1175

.1575

.1975

.2375

.2775

.3175

.3575

.3825

.4600

.1975

.1725

.2125

.2375

Dimensions in inches

SM-20L PCB Pad Layout

Note: Specifications subject to change without notice.