PRELIMINARY MX98206EC 8-Port Dual-Speed Ethernet Switch Controller FEATURES * Support IEEE802.3x compliant flow control for FDX and back-pressure flow control for HDX. * Support up to 2MB SSRAM (pipeline type, or flow through type) as data buffer. * Serial EEPROM interface for auto-configuration. * Broadcast storm control. * LED interface for utilization indication of each port. * Cascade 2 switch controllers to construct 16 10/ 100MBps switched Ethernet ports in a box easily without extra logic. * 3.3V COMS technology, package in 208-pin PQFP. * Single-chip 8-port 10/100Mbps wire-speed switched Ethernet controller. * Integration of 8 dual-speed, full/half duplex capable Media Access Controllers (MACs) with RMII interfaces. * Support Store-and-Forward switching scheme. * Support 2.1Gbps (@66MHz) expansion (inter-switch) bus interface. * Support source/destination MAC address lookup, learning, and aging within built-in storage of 1K MAC address. * Optional MII port in replacement of the cascading interface. GENERAL DESCRIPTION is over the warning threshold, flow control mechanism is triggered to deter the underlying host(s) to transmit frames for some time. For half-duplex operation port(s), jam pattern is issued to the attached host. For full-duplex operation port(s), specific "pause" frame of IEEE Std. 802.3x is issued to host. Moreover, user can program the threshold of broadcast frame storage to discard over-loaded ones to prevent potential of broadcast storming from occurring. After buffer fullness drops in the safe margin, controller releases flow control state to allow physical ports to work in normal condition. The MX98206EC is a 8-port 10/100Mbps single-chip shared-memory Ethernet switch controller. A desktop or departmental switched Ethernet solution can be achieved by combining MX98206EC, the necessary physical devices and low-cost memory. All 8 ports are full-duplex capable to provide private 20/200Mbps bandwidth connection to power users or servers through external physical (PHY) layers. System manufacturers can cascade 2 MX98206EC switch controllers to build a 16-port 10/ 100Mbps switched Ethernet box easily. MX98206EC supports store-and-forward switching scheme with built-in storage of 1K MAC addresses. The function modules integrated in controller include 8 fullduplex compatible media access controller with RMII interface to PHYs, address resolution logic (ARL) for MAC address learning and recognition, queue manager, and expansion bus interface for 2 MX98206ECs cascading. It fully complies with IEEE Std. 802.3/802.3u specification, and supports MDC/MDIO interface for physical layer management with industrial standard physical devices. Per port utilization information can be retrieved through serial LED interface. User can program the control register for "all-port" display mode or "select-port" display mode with 8-bit indication or 5-bit indication. System manufactures' design flexibility is our concern too. MX98206EC provides expansion bus interface for 2 MX98206ECs cascading. Simple bus protocol is utilized to control traffic transaction on expansion bus. MX98206EC also provides an optional MII port for general connection in case no expansion bus is used. In 16port Fast Ethernet switch paradigm, only one EEPROM is required for auto-configuration. Figure 1 and Figure 2 illustrate the functional block diagrams of MX98206EC, and Figure 3 depicts the pin assignment of MX98206EC. The flow control mechanism is provided to prevent buffer overflow that would force controller to lose packets. Controller will monitor the traffic through receive terminal of each physical port, and frame queuing status on the data buffer. Some watermarks are set. As soon as data buffer P/N:PM0661 REV. 0.2, JUN. 09, 2000 1 MX98206EC MMODE MTYPE/ MDC MDIO MDC/MDIO I/F MSIZE[1:0] MD[63:0] Queue/SRAM Manager MA[17:0] MA16X GW# CE# PxCRSDV * PxRXD[1:0] PxTXEN PxTXD[1:0] REFCLK 10/100M MAC Address Resolution Logic LED Controller LEDOUT# EEPROM ECS EEPROM I/F OSCIN LEDPS LEDCLK EXPDI15:0] ESK EDI EDO CMDI EXPDO[15:0] CMDO FCIN FCOUT Expansion L2 Address Table Control Registers Bus * Note: On RMII interface, "Px" stands for P0 ~P7 separately. Figure 1. MX98206EC Functional Block Diagram ( with Expansion Bus ) P/N:PM0661 REV. 0.2, JUN. 09, 2000 2 MX98206EC MMODE MSIZE[1:0] MTYPE/ MDC MDIO MDC/MDIO I/F MD[63:0] MA[17:0] MA16X Queue/SRAM Manager GW# CE# PxCRSDV * PxRXD[1:0] PxTXEN PxTXD[1:0] REFCLK 10/100M MAC Address Resolution Logic LED Controller EEPROM ECS EEPROM I/F OSCIN MII_PORT MII_RXD[3:0] MII_RXDV MII_CRS MII_TXD[3:0] MII_TXC MII_TXEN MII_COL LEDPS LEDCLK LEDOUT# ESK EDI EDO L2 Address Table Control Registers * Note: On RMII interface, "Px" stands for P0 ~P7 separately. Figure 2. MX98206EC Functional Block Diagram ( with Extra MII Port ) P/N:PM0661 REV. 0.2, JUN. 09, 2000 3 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 MD[15] MD[16] MD[17] MD[18] MD[19] MD[20] MD[21] MD[22] MD[23] MD[24] MD[25] VDD GND MD[26] MD[27] MD[28] MD[29] MD[30] MD[31] MD[32] MD[33] MD[34] MD[35] MD[36] MD[37] VDD GND MD[38] MD[39] MD[40] MD[41] MD[42] MD[43] MD[44] MD[45] MD[46] MD[47] MD[48] MD[49] GND VDD MD[50] MD[51] MD[52] MD[53] MD[54] MD[55] MD[56] MD[57] MD[58] MD[59] MD[60] MX98206EC 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 MX98206EC 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 MD[61] MD[62] MD[63] MA[7] MA[6] MA[5] MA[4] MA[3] MA[2] MA[1] MA[0] GND MA[8] MA[9] MA[10] MA[11] MA[12] MA[13] MA[14] MA[15] LEDOUT LEDCLK LEDPS VDD GND VDD P7RXD[1] P7RXD[0] P7CRSDV P7TXD[1] P7TXD[0] P7TXEN GND P6RXD[1] P6RXD[0] P6CRSDV P6TXD[1] P6TXD[0] P6TXEN GND P5RXD[1] P5RXD[0] P5CRSDV P5TXD[1] P5TXD[0] P5TXEN P4RXD[1] P4RXD[0] P4CRSDV P4TXD[1] P4TXD[0] P4TXEN EXPDO[15] EXPDO[14] EXPDO[13] EXPDO[12] EXPDO[11] EXPDO[10] EXPDO[9] EXPDO[8] EXPDO[7] EXPDO[6] EXPDO[5] EXPDO[4] EXPDO[3] EXPDO[2] EXPDO[1] EXPDO[0] CMDO FCOUT RESET VDD REFCLK GND VDD GND VDD MDC MDIO P0TXEN P0TXD[0] P0TXD[1] P0CRSDV P0RXD[0] P0RDX[1] GND P1TXEN P1TXD[0] P1TXD[1] P1CRSDV P1RXD[0] P1RXD[1] P2TXEN P2TXD[0] P2TXD[1] P2CRSDV P2RXD[0] P2RXD[1] P3TXEN P3TXD[0] P3TXD[1] P3CRSDV P3RXD[0] P3RXD[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 MD[14] MD[13] MD[12] MD[11] MD[10] MD[9] MD[8] MD[7] MD[6] MD[5] MD[4] MD[3] MD[2] MD[1] MD[0] GND MA[17] MA16X MA[16] GW# CE# MMODE MSIZE[1] MSIZE[0] OSCIN GND VDD VDD EDO EDI ESK ECS EEPROM GND FCIN CMDIN EXPDI[0] EXPDI[1] EXPDI[2] EXPDI[3] EXPDI[4] EXPDI[5] EXPDI[6] EXPDI[7] EXPDI[8] EXPDI[9] EXPDI[10] EXPDI[11] EXPDI[12] EXPDI[13] EXPDI[14] EXPDI[15] Figure 3. MX98206EC Pin Diagram Top View P/N:PM0661 REV. 0.2, JUN. 09, 2000 4 MX98206EC PIN DESCRIPTION 10/100Mbps RMII Interface PIN # 31 38 44 50 56 62 69 76 33-32 40-39 46-45 52-51 58-57 64-63 71-70 78-77 28 35 41 47 53 59 66 73 30-29 37-36 43-42 49-48 55-54 61-60 68-67 75-74 21 Subtotal PIN NAME P0CRSDV P1CRSDV P2CRSDV P3CRSDV P4CRSDV P5CRSDV P6CRSDV P7CRSDV P0RXD[1:0] P1RXD[1:0] P2RXD[1:0] P3RXD[1:0] P4RXD[1:0] P5RXD[1:0] P6RXD[1:0] P7RXD[1:0] P0TXEN P1TXEN P2TXEN P3TXEN P4TXEN P5TXEN P6TXEN P7TXEN P0TXD[1:0] P1TXD[1:0] P2TXD[1:0] P3TXD[1:0] P4TXD[1:0] P5TXD[1:0] P6TXD[1:0] P7TXD[1:0] REFCLK I/O I DESCRIPTION Carrier sense/Receive data valid. Active high, indicates receive medium is non-idle. CRSDV is asserted asynchronously with respect to REFCLK. I Receive data. for Port 0 ~ Port 7, synchronous to REFCLK and RXD[1] is MSB. When CRSDV is deasserted, RXD[1:0] is "00". O Transmit enable. Active high, assertion indicates the MAC is presenting di-bits on TXD[1:0] for transmission. TXEN is asserted synchronously with first nibble of preamble and remained asserted while all di-bits transmitted are presented on RMII. TXEN is negated prior to 1st REFCLK rising edge following the final di-bit of frame. O Transmit data. for Port 0 ~ Port 7, synchronous to REFCLK and TXD[1] is MSB. When TXEN is asserted, TXD[1:0] is accepted for transmission. TXD[1:0] is "00" when TXEN is deasserted. I Reference Clock for RMII interface. 50MHz. 49 P/N:PM0661 REV. 0.2, JUN. 09, 2000 5 MX98206EC EXPANSION (inter-switch) BUS INTERFACE/OPTIONAL 10/100M MII INTERFACE PIN # 1-4 5 6 7 8 9-16 PIN NAME EXPDO[15:12]/MII_TXD[0:3] EXPDO[11]/MII_TXC EXPDO[10]/MII_TXEN EXPDO[9]/MII_COL EXPDO[8]/MII_CRS EXPDO[7:0] I/O O 193-202 203 204-207 208 EXPDI[0:9] EXPDI[10]/MII_PORT EXPDI[11:14]/MII_RXD[0:3] EXPDI[15]/MII_RXDV I 17 CMDO O 192 CMDI I 18 FCOUT O 191 FCIN I DESCRIPTION Expansion data Out, EXPDO[15] is MSB. Frame data or command is output to the adjacent cascaded switch con troller on the bus. A bus transaction consists of a com mand phase followed by one or more data phases. Data or command is generated on the rising edge of OSCIN. When CMDO is asserted, the command is on the bus. Particular "start of Frame" command notifies start of frame transmission to the adjacent cascaded switch controller; and "End of Frame" indicates end of transmission. If MII-PORT is tied to "1" during reset, the multiplexed pins (pin 1-8) are configured as the output of the 10/100M MII interface. Expansion data in. When CMDI is active, command mes sage is sampled on the rising edge of OSCIN. While "Start of Frame" command is detected, switch controller starts to receive frame data. Till "End of Frame" presents, switch controller stops data reception. If MII_PORT is tied to "1" during reset, the multiplexed pins (pin203-208) are configured as the input of the 10/ 100M MII interface. Command enable out. Active high, assertion assertion indicates available command is on the EXPDO[15:0]. Command enable in. Active high, indicates command is ready on the EXPDI[15:0]. Flow control out. Active high, assertion will force the ad jacent cascaded switch controller to suspend current frame transmission on expansion interface. Flow control in. Active high, assertion indicates the adja cent cascaded controller could not accept any frame data due to FIFO full. 36 Subtotal P/N:PM0661 REV. 0.2, JUN. 09, 2000 6 MX98206EC BUFFER MEMORY INTERFACE PIN # 102-115 118-129 132-143 146-164 165-171 174 173 175 85-92 101-94 PIN NAME MD[63:50] MD[49:38] MD[37:26] MD[25:7] MD[6:0] MA16X MA[17] MA[16] MA[15:8] MA[7:0] I/O I/O DESCRIPTION Memory data bus.64-bit and bi-directional. O Memory address bus. Where MA[16], MA16X, and MA[17] could be used for chip enabling. 176 GW# O 177 178 CE# MMODE O I 179-180 MSIZE[1:0] I Global write. The signal is low for memory write cycle and is high for memory read cycle. Chip enable. Active low, enables memory read or write. Memory mode. High is for pipelined SSRAM, low for flowthrough SSRAM. An external resistor should be connected. Memory size. Controller supports 3 different buffer memory configurations, where to this pin in all cases. MSIZE[1:0] = "00" reserved; "01" 512KB; "10" 1MB; "11" 2MB. External resistors should be connected to the pins in all cases. 88 Subtotal P/N:PM0661 REV. 0.2, JUN. 09, 2000 7 MX98206EC EEPROM INTERFACE PIN # 189 PIN NAME EEPROM I/O I 188 ECS I/O 187 ESK I/O 186 EDI I/O 185 EDO I Subtotal DESCRIPTION EEPROM enable. Active high. Indicates configuration data is autoloaded from EEPROM after reset. In 2-controller cascade structure only one EEPROM is required. The configuration data of upper half is for master controller (device=0)*, and that of lower half one is for slave controller (device=1). Tying this pin to ground disables EEPROM interface and prevents auto-configuration. An external resister should be connected to this pin in all cases. EEPROM chip select. Active high. In 1-controller application it is an output pin to enable auto-loading from EEPROM. In 2-controller cascade structure the master controller (device=0)* utilizes the pin as an output pin to trigger slave controller (device=1, on which ECS is an input pin) and EEPROM. The pin should be pulled down with external resistor in operating. EEPROM clock. 515KHz derived from system clock by internal PLL. For 1-controller application or master controller (device=0)*, it is used as an output pin to drive EEPROM and slave controller. For slave controller (device=1), it is used as an input pin to receive clocking information from master controller. The pin should be pulled down with external resistor in operating. EEPROM data input. The pin is connected to the corresponding EDI pin on EEPROM part. In 2-controller cascade structure, the pin of MX98206EC with device = 0 is used as an output pin. In MX98206EC with device = 1, it is an input pin. The pin should be pulled down with external resistor in operating. EEPROM data output. The pin is connected to the corresponding EDO pin on EEPROM part. 5 * Note: The "device" is designated by pin LEDOUT# during reset. P/N:PM0661 REV. 0.2, JUN. 09, 2000 8 MX98206EC MISCELLANEOUS PIN # 181 PIN NAME OSCIN I/O I 19 26 RESET# MTYPE/MDC I I/O 27 MDIO I/O 83 LEDCLK I/O 84 LEDOUT# I/O 82 LEDPS I (PD) DESCRIPTION System clock input. 66MHz. Single 66MHz clock source is used to drive controller and external data buffer (SSRAM). Reset. Active low, be held low for some time after power-on. Memory type/Management data clock. During reset, the multiplexed pin is used as input to identify whether SSRAM is of 1 chip_enable pin, (where MTYPE pulls high) or 3 chip_enable pins, (where MTYPE pulls low). After reset, the multiplexed pin works as output pin (MDC) to provide 2.5MHz clock reference for MDIO. Management data. Bi-directional RMII management port data pin. MDIO is synchronous with respect to MDC, and is sampled on the rising edge of MDC. Cascade/LED shift clock. During reset, the multiplexed pin is used as input to identify application structure, where Pull high, 2-controller cascade structure; Pull low, 1-controller application. After reset, the multiplexed pin works as an output pin (LEDCLK) to provide 1.1MHz clock reference for serial LED data out. Device/LED data out. During reset, the multiplexed pin is used as an input pin to designate controller I.D. where Pull high, device = 1 (slave); Pull low, device = 0 (master). After reset, the multiplexed pin works as a serial data out pin. The data indicates the switch port s ' utilization ratio. LEDOUT# is active-low serial data, of which "1" (high) bits turn off LED and "0" (low) bits turn on LED. LEDOUT# is latched by external latch device on the rising edge of LEDCLK. LED display mode selector. During reset, pull-high makes "all-port" display mode be selected, while pull-low makes "select-port" display mode be chosen. On "select-port" display mode, LEDOUT# stream contains the selected port number and its utilization data. Where port selection is through high pulse trigger caused by external switch button. Power-on port 0 is selected, then the pulse will let controller select next port's utilization indication. P/N:PM0661 REV. 0.2, JUN. 09, 2000 9 MX98206EC 20, 23, 25, VDD 79, 81, 116, 131, 145, 183, 184 22, 24, 34, GND 65, 72, 80, 93, 117, 130, 144, 172, 182, 190 Subtotal 3.3V 30 Control Registers Offset 0x00H 0x01H 0x02H 0x03H 0x04H 0x05H 0x06H 0x07H 0x08H 0x09H Register Configuration 0 Configuration 1 Aging Timer Time Base 802.3x Pause Timer MAC Address 0 MAC Address 1 MAC Address 2 Port 0/1 RX_Buf Threshold Port 2/3 RX_Buf Threshold Offset 0x0AH 0x0BH 0x0CH 0x0DH 0x0EH 0x0FH 0x10H 0x11H 0x12H P/N:PM0661 Register Port 4/5 RX_Buf Threshold Port 6/7 RX_Buf Threshold Expansion Port Rx_Buf Threshold Broadcast Storming Control. Forcd 100/F Force 802.3x Flow Control Reserved Reserved B/TX_Buf Threshold REV. 0.2, JUN. 09, 2000 10 MX98206EC Configuration 0 (Reg00H), default = 0xC072H Bit 0.0 0.1 0.2 0.3 0.5-4 0.6 0.15-7 Description Col16#, 1: packet that runs into 16 consecutive collision will NOT be dropped; 0: packet that runs into 16 consecutive collision will be dropped. LED_8, 1: 8-bit value used for per port utilization indication; 0: 5-bit value used for per port utilization indication. MF, management frame preamble suppression 1: controller will send management frames with preamble being suppressed on MDIO interface; 0: controller will send management frames without preamble suppression. Timeout#, 1: packet will NOT be dropped in despite of packet being queued over 1 second. 0: packet will be dropped if packet has been queued over 1 second. HashSel, 48-bit DA (SA)_MAC address, is translated separately to 8-bit pointer of address table for address learning and recognition. The translation is by aid of CRC generator within the controller. The selector helps to fine-tune the hashing resolution. 00: bits [7:0] of CRC [DA or SA] are selected; 01: bits [15:8] of CRC [DA or SA] are selected; 10: bits [23:16] of CRC[DA or SA] are selected; 11: bits [31:24] of CRC[DA or SA] are selected. RGNT_ext, read cycle extension. The setting assures the accuracy of last data read in read cycle for different SSRAM models used. 0: pipeline SSRAM with 2T/2T character, or flowthrough SSRAM is used; 1: pipeline SSRAM with 2T/1T character is used. Reserved P/N:PM0661 Type R/W Default 0 R/W 1 R/W 0 R/W 0 R/W 11 R/W 1 0xC00H REV. 0.2, JUN. 09, 2000 11 MX98206EC Configuration 1 (Reg01H), default = 0x001EH Bit 1.1-0 1.3-2 1.5-4 1.6 1.7 1.8 1.9 1.10 1.11 1.15-12 Description Type AbortCnt, When a port is on flow control state, the setting will allow some extra R/W packet reception from attached host, on which the NIC card could not recognize 802.3x "pause" frame or operates at half-duplex mode. If fullness of buffer memory reaches global reception threshold, some packets are still dropped. 00: 8 packets; 01: 16 packets; 10: 32 packets; 11: all packets. BPCnt. The setting limits times of jam pattern sending on some half-duplex R/W port that runs into flow control state. 00: back-pressure 8 times then stop; 01: back-pressure 16 times then stop; 10: back-pressure 32 times then stop; 11: back-pressure all the time till the amount of used pages drops into safe margin. BoffOp, Backoff operation mode. In normal backoff algorithm same packet R/W transmission delays {2n -1} (max.) slot time when collision occurs. Modification of backoff algorithm is utilized to improve switched Ethernet performance on half-duplex connection. 00: standard algorithm; 01: for first 2 collision follows standard backoff. More than 2 collision in transmission, packet re-send delays only 0, 1,2,or 3 slot times. 10: packet re-send delays 0 slot time all the time; 11: reserved. BPEn#, enable back-pressure flow control on half-duplex connection. R/W 1: disable; 0: enable. BP64, jam pattern packet length. R/W 1: 64 bytes; 0: 1024 bytes. Reserved Selmux, R/W 1: to reverse port numbering, namely ports 0~7 mapped to ports 7~0 and 8~11 mapped to 11~8; 0: none MII-port speed 1:100M ; 0:10M R/W MII-port duplex 1: Full duplex ; 0: Half duplex R/W Reserved P/N:PM0661 Default 11 00 00 0 0 0 0 0 REV. 0.2, JUN. 09, 2000 12 MX98206EC Aging Timer (Reg02H), default = 0x012CH Bit 2.15-0 Description The time period is defined to age out the least used entries on address table. Default is 300 (0x012CH) seconds. Type R/W Default 0x12CH Type R/0 Default x1F78H Type Default R/W 0x00FH Type R/W Default 0x00H Type R/W Default 0x00H Type R/W Default 0x00H Type R/W R/W Default ** ** Time Base Register (Reg03H), default = 0x1F78H Bit 3.15-0 Description The setting determines count of system clock cycles for 125us. At 66MHz operation frequency, the count is 0x1F78. Controller utilizes 125us as internal timing base for control logic. 802.3x Pause Timer (Reg04H), default = 0x01FFH Bit 4.4-0 4.15-5 Description Reserved. TxFCCnt, the timer determines the period, namely pause_time, to inhibit packet transmission from attached host for flow control. The variable pause_time of "pause" frame is equal to TxFCCnt x 32 + 31. MAC Address 0 (Reg05H), default = 0x00H Bit 5.15-0 Description Controller MAC address bits [15:0]. MAC Address 1 (Reg06H), default = 0x00H Bit 6.15-0 Description Controller MAC address bits [31:16]. The MAC address is used in "pause" frame MAC Address 2 (Reg07H), default = 0x00H Bit 7.15-0 Description Controller MAC address bits [47:32]. Port 0/1 Rx_Buf Threshold (Reg08H), default = ** Bit 8.7-0 8.15-8 Description Port 0 Rx_Buf Threshold *. Port 1 Rx_Buf Threshold *. P/N:PM0661 REV. 0.2, JUN. 09, 2000 13 MX98206EC Port 2/3 Rx_Buf Threshold (Reg09H), default = ** Bit 9.7-0 9.15-8 Description Port 2 Rx_Buf Threshold *. Port 3 Rx_Buf Threshold *. Type R/W R/W Default ** ** Type R/W R/W Default ** ** Type R/W R/W Default ** ** Description Type Expansion Port Rx_Buf Threshold. When the amount of pages used by expansion R/W port's receive terminal is over the threshold defined, controller will inform the adjacent cascaded partner to deter new frame transmission. Reserved. Default *** Port 4/5 Rx_Buf Threshold (Reg0AH), default = ** Bit A.7-0 A.15-8 Description Port 4 Rx_Buf Threshold *. Port 5 Rx_Buf Threshold *. Port 6/7 Rx_Buf Threshold (Reg0BH), default = ** Bit B.7-0 B.15-8 Description Port 6 Rx_Buf Threshold *. Port 7 Rx_Buf Threshold *. Expansion Port Rx_Buf Threshold (Reg0CH), default = *** Bit C.7-0 C.15-8 Broadcast Storming Control (Reg0DH), default = 0x2000H Bit D.12-0 D.13 Description Reserved 1: enable broadcast packet buffer control; 0: disable. If the amount of pages used by queued broadcast packets is over the threshold defined in Reg12H, the next broadcast packet received is discarded. D.15-14 Reserved. P/N:PM0661 Type Default R/W 1 REV. 0.2, JUN. 09, 2000 14 MX98206EC Force 100Mbps Full-Duplex Mode, Port Map (Reg0EH), default =0x00H Bit E. 7-0 E.15-8 Description 1: Force the corresponding MAC to operate on Fast Ehternet Full-duplex mode, where bit E.7 is used for port_7 and bit E.0 is used for port_0 Reserved Type R/W Default 0x000H Type R/W Default 0x000H Type Default Type Default Type Default R/W !! Force 802.3x Flow Control, Port Map (Reg 0FH), default = 0x00H Bit F.7-0 F.15-8 Description 1: Force the corresponding MAC to be capable of IEEE Std, 802.3x frame-base flow control where bit F.7 is used for port_7, and bit F.0 is used for port_0. Reserved Reserved (Reg10H) Bit Description 10.15-0 Reserved Reserved (Reg11H) Bit Description 11.15-0 Reserved B/Tx_Buf Threshold (Reg12H), default = !! Bit 12.7-0 12.15-8 Description Reserved Broadcast Packet Tx_Buf Threshold. P/N:PM0661 REV. 0.2, JUN. 09, 2000 15 MX98206EC (Notes for above registers' definition. Reg08H ~ Reg0CH) * Note: The amount of used pages (not released) by physical port's receive terminal is counted. If the amount is over the threshold defined, controller will issue flow control frame on this port. ** Note: The default threshold on each port depends on buffer memory configuration. The setting is Size: 512KB 1MB 2MB Default: 0x8H 0x10H 0x20H The threshold is register setting multiplied by 32. *** Note: The default threshold on expansion port's receive terminal depends on buffer memory configuration. The setting is Size: 512KB 1MB 2MB Default: 0x20H 0x40H 0x80H The threshold is register setting multiplied by 32. !! Note: The default threshold on total pages occupied by queued frames in expansion port's output buffer or by queued broadcast frames depends on buffer memory configuration. The setting is Size: 512KB 1MB 2MB Default: 0x30H 0x60H 0xC0H The threshold is register setting multiplied by 32. P/N:PM0661 REV. 0.2, JUN. 09, 2000 16 MX98206EC Functional Description Clocks MX98206EC requires a single 66MHz clock signal at OSCIN input pin as system clock and 50MHz at REFCLK as timing reference on RMII interfaces. Internal logic derives clock references for other interfaces, namely 2.5MHz clock applied on MDC/MDIO interface, 1.1Mhz clock on LED serial data interface, and 515KHz clock on EEPROM interface. Same on-board 66MHz clock source also drives SSRAM parts directly. Reset A power-on, or hard reset is initiated by an active-low pulse on RESET# pin. In reset MX98206EC can identify its "device" number and application structure (1-controller or 2-controller cascade) by pull-up/down the pins of LEDOUT# and LEDCLK. The initialization process then loads all ports configurable parameters, resets internal state machines to idle state, initializes embedded layer 2 address table, and frees data buffers. At the completion of reset sequence, all ports are enabled for packet transmission and reception. In 2-controller cascade structure, only one external EEPROM is required for auto-configuration. If pin of EEPROM is low, MX98206EC runs under default configuration. Figure 4 below shows auto-configuration diagram in 2-controller cascade structure. VDD LEDCLK LEDCLK EEPROM MX98206EC ECS ESK EDI EDO MX98206EC LEDOUT LEDOUT " device = 0 " " device = 1 " ECS ESK EDI EDO GND EEPROM Figure 4. Auto-Configuration Diagram in 2-Controller Cascade Structure P/N:PM0661 REV. 0.2, JUN. 09, 2000 17 MX98206EC PHY Management Via auto-negotiation procedure between PHYs on both end of connection link, the transmission mode on the link is determined. The link operation is classified as 10Mbps-HDX, 10Mbps-FDX, 100Mbps-HDX, and 100Mbps-FDX, where HDX means half-duplex and FDX means full-duplex. Moreover, under full-duplex mode, it is identified whether either side supports frame-based flow control or not. MX98206EC through serial MDIO interface continuously monitors the negotiation result in PHY registers, and MAC of each physical port will operate accordingly. MX98206EC also provides force-mode configuring capability to force individual port to run on Fast Ethernet, fullduplex mode. <Programmable Register> Reg00H.2, MF bit. Following standard PHY management through MDIO/MDC interface, a pattern of 32 consecutive "1" is used as preamble in each read-write cycle. Set this bit to support preamble suppressed on management frame driven by MX98207. The standard PHY management READ frame format is Preamble ST OP PHYAD REGAD TA DATA IDLE (32 bits) (2 bits) (2 bits) (5 bits) (5 bits) (2 bits) (16 bits) 1.......1 01 10 AAAAA RRRRR Z0 D....D Z Reg01H.9, selmux bit. Quad PHYs in the market today have two port ordering in the chip pinout, clockwise and counter clockwise. The setting enables system engineers to implement board layout with any PHY easily. With default setting (selmux = 0), the PHY of AH104 from Altima Technologies is recommended. Reg0EH.7-0 When the bit(s) of 8-bit map is set to 1, the corresponding port is forced to run on 100Mbps full-duplx mode, Frame Reception The frame received on 2-bit wide receive channel of RMII interface is queued in receive FIFO, and then stored in external buffer memory. Several error conditions will be identified during data reception, 1.Runt frame error, if the frame size is less than 64 bytes; 2.CRC error, if FCS is not matched to the result of CRC calculation; 3.Long frame error, if frame size is larger than 1522 bytes; 4.Alignment error, if frame length is of non-integral number of octets; The bad frames will be discarded. If no errors are detected , the frame is stored and forwarded to egress port at wire speed. Several pages of buffer memory could be occupied for frame storage, on each page 256-byte free memory is allocated. The data link management frames, namely IEEE 802.3x "pause" frame is recognized and no frame storage occurs. Frame Transmission Frame transmission begins while the output queue of physical port is not empty. The frame data is moved to output FIFO from external buffer memory, and converted to 2-bit stream through transmit channel of RMII interface. MX98207 transmits frames in accordance to IEEE 802.3 standard. The egress port is responsible for preamble insertion, collision back-off, and inter packet gap keeping. While late collision happens on half-duplex port, the transmitted frame is aborted. Several control bits are defined on half-duplex mode (see below). In full-duplex mode, the egress port ignores the signaling of carrier activity and collision detection on channel media. P/N:PM0661 REV. 0.2, JUN. 09, 2000 18 MX98206EC <Programmable Register> Reg00H.0, Col16#. Set this bit to drop the transmitted packet which runs into 16 consecutive collisions. Reg00H.3, Timeout#. Set this bit to drop frames which have been queued in buffer over 1 second. Reg01H.5-4, BoffOP. Set these bits to determine back-off operation mode on half-duplex ports. Broadcast Storm Control To prevent network melted down due to broadcast storm, MX98207 can be programmed to restrict storage amount of broadcast frame inside. While the storage of broadcast frame gets over the threshold, the next coming broadcast frame(s) is dropped. Three type of frame are viewed as broadcast frame. 1.Received frame with DL_DA as FF-FF-FF-FF-FF-FF; 2.Received frame with DL_DA as 1x-xx-xx-xx-xx-xx; 3.Received frame with unknown destination (unicast) address. <Programmable Register> Reg0DH.13, enable_key of broadcast storm control. Reg12H.15-8, broadcast frame storage watermark. The setting of this byte indicates the maximum amount of pages could be used for broadcast frame storage. Each page allocates 256-byte space in buffer memory. Flow Control Flow control mechanism is implemented to avoid abnormal packet drop due to traffic congestion on egress ports. The input traffic on each physical port and global frame queuing is monitored and counted in pages, where each page allocates 256-byte in buffer memory. Two kinds of thresholds are defined for flow control, namely global reception threshold per chip, and reception threshold per port. While the total pages occupied by queued frames are over the output queuing threshold on certain egress port, the forthcoming frame destined to this port is dropped. While the output queue is in safety margin again, frame relay to this port is back to normal operation. While the amount of pages used (not released yet) by certain ingress port is over reception threshold, MX98206EC will identify this port as heavy buffer memory consumer and force this port on flow control state. The port is back to normal operation when several occupied pages are released to free pool. While the fullness of buffer memory is over global reception threshold, all ports are forced on flow control state. Only multiple occupied pages are released to free pool, each port will be back to normal operation. The global reception threshold depends on external buffer memory configuration and is set by controller itself. While physical port(s) is under flow control state, MX98206EC will issue specific "pause" frame on full-duplex port, or "jam" the half-duplex connection bus to deter further frame transmission from attached host (or device). On full duplex connection, the attached host will delay for period of pause_time defined, and then re-start frame transmission. On half-duplex connection, the attached host will back-off till jam pattern disappearing, and then re-start frame transmission. After the delay, if the global reception or reception per port still runs over threshold, the flow control procedure repeats. P/N:PM0661 REV. 0.2, JUN. 09, 2000 19 MX98206EC Similar idea is applied to expansion port, except that MX98207 will send out proprietary "stop" command to adjacent cascaded partner for inhibition of frame transmission, and then send out proprietary "continue" command as soon as occupied pages being released to free pool. <Programmable Register> Reg01H.6, BPEn#, enable_key of flow controlling on half-duplex ports. Reg01H.7, BP64 The bit determines the length of jam pattern used in back-pressure operation. Reg04H.15-8, TxFCCnt. Determine the pause_time to be filled in pause frame. Reg08H, 09H, 0AH, 0BH, 13H, and 14H. Set reception threshold of each ingress port. The 1-byte variable indicates total pages can be used. Each page allocates 256-byte space in buffer memory. Reg0CH. Set reception threshold of expansion bus. The 1-byte variable indicates total pages can be used. Each page allocates 256-byte space in buffer memory. Reg0DH, enable_keys of flow controlling on egress ports. Reg0EH, 0FH, 10H, 11H, 15H, and 16H. Set output queuing threshold of each egress port. The 1-byte variable indicates total pages can be used. Each page allocates 256-byte space in buffer memory. Reg12H.7-0. Set output queuing threshold on expansion bus. The 1-byte variable indicates total pages can be used. Each page allocates 256-byte space in buffer memory. Reg0FH. 7-0. When the pyhsical port runs on "forced" 100Mbps full-duplex mode, the corresponding bit on Reg0F. 7-0 can be set to 1 to indicate the MAC supports frame-based flow control mechanism. Address Learning and Recognition After a good packet is received, address resolution logic begins address lookup. The destination MAC address and source MAC address associated are retrieved. The source MAC address is used to build up an address table. By searching the address table, the unicast destination MAC address will be recognized, and stored frame is forwarded to destined port. In both of address learning and recognition, the 48-bit MAC address is converted to a 8-bit search index via hash transformation. In learning, the entry designated by search index is checked to be valid or not. If non-valid, a new entry is generated with putting the information of source MAC address and ingress port I.D.. A 4-layer structure is provided in learning mechanism. If valid, the 4-layer mechanism can keep 4 different MAC addresses in one certain entry to increase hashing resolution. In recognition, the MAC address in table entry designated by search index is used to compare with destination MAC address. If both are matched, the associated port I.D. in entry is the destination port. Otherwise, the received frame will be classified as a broadcast frame, and be flooded through every port (except source port). P/N:PM0661 REV. 0.2, JUN. 09, 2000 20 MX98206EC The memory space within MX98206EC can keep 1K MAC addresses. Aging mechanism is supported, namely the address information is aged out if not be referred in 300sec (default, the parameter is programmable). The newly learnt MACs will be kept in table. Through expansion bus, two address tables used in 2-controller cascade structure are synchronized. <Programmable Register> Reg02H. Aging timer defined to age out the least used entries in address table. Default value is for 300 seconds. Queue Management The buffer memory is partitioned into pages, each page allocates 256-byte memory space. Buffer management will dispatch free pages for each received frame. After frame reception complete, the descriptor information is passed to buffer controller of the egress port. For unicast frame, the occupied pages will be released for reuse after transmission complete. For broadcast frame, switch controller does not make copies of frame, but count the times of transmission of broadcast frame that should be performed. Till all ports (except source port) complete (broadcast) frame transmission, the occupied pages are released to free buffer pool. External (up to 2MB) SSRAM is used for frame buffer. MX98206EC supports Store-and-Forward switching scheme. Each frame reception and frame transmission needs to access the external buffer memory. Queue manager grants those access requests to provide fair access to the memory, and to meet different traffic throughput on each port (10M-HDX, 10M-FDX, 100M-HDX, or 100M-FDX). MX98206EC can support up to 4.2Gbps (64b @66MHz) memory access bandwidth for the operation of 12 200Mbps per port (at full-duplex mode) plus traffic flow on expansion bus. Pins of MTYPE/MDC, MSIZE, and MMODE are provided for flexibility of selection of SSRAMs in system design. Figure 5 below shows the SSRAM chip_enable diagram with different MTYPE value. MX98206EC CE# MA16X MA[17] MA[16] SSRAM # 0 CE1# CE2 CE3# MTYPE " MTYPE = 0" GND VDD MX98206EC CE# MA[16] MA[17] MA16X MTYPE SSRAM # 1 CE1# CE2 CE3# SSRAM # 0 CE# SSRAM # 1 CE# " MTYPE = 1" SSRAM # 2 CE1# CE2 CE3# SSRAM # 2 CE# SSRAM # 3 CE# SSRAM # 3 CE1# CE2 CE3# Figure 5. SSRAMs Chip_Enable Diagram with Different MTYPE Value P/N:PM0661 REV. 0.2, JUN. 09, 2000 21 MX98206EC <Programmable Register> Reg00H.6, RGNT_ext. The setting depends on SSRAM used. Expansion Bus Interface 2 MX98206ECs can be cascaded back-to-back through expansion bus interface. The bus interface provides data receive channel, data transmit channel (both are 16-bit wide, running at up to 66MHz), and control signaling. The stream on the expansion bus includes pure frame data, address table updating information, and control message. The operation on expansion bus is command-based. The active signal present on CMD_I (or CMD_O) pin indicates command message on data channel, otherwise frame or address updating information is on data channel. "Start of Frame" command associates with beginning of frame data transmission on data channel, then "End of Frame" terminates data transmission. During frame transmission, controller asserts FCOUT to request cascaded partner to suspend frame transmission. The address updating information is used to synchronize both address tables in cascade architecture, whenever new entry generation. When the amount of un-relayed frames runs over threshold defined, MX98206EC will issue proprietary "stop" command to notify the cascaded partner no further frame reception allowed on data receive channel. Figure 6 below shows 2-controller cascade structure diagram. VDD LEDCLK LEDCLK 16 EXPDO EXPDI CMDI FCIN CMDO FCOUT MX98206EC MX98206EC 16 EXPDI CMDO FCOUT CMDI FCIN LEDOUT EXPDO 66MHz OSCIN " device = 0 " LEDOUT " device = 1 " GND Figure 6. 2-Controller Cascade Structure Diagram P/N:PM0661 REV. 0.2, JUN. 09, 2000 22 MX98206EC MII Port Selection and Application In addition to the cascaded back-to-back connection, MX98206EC offers another way to be further integrated into the internet world. With the MII_Port pin tied to pull-up, MX98206EC can be configured as a 9-port switch with 8 RMII + 1 MII ports, and the extra MII port will act like a general interface to the G-MAC environment, which serves perfectly in the home gateway architecture. The ideal system diagram of putting MX98206EC and MX98726EC together is shown in Figure.7. Users can build their broadband internet system and share the uplink bandwidth into local area network via the G-MAC + Switch combination. Internet ADSL or cable modem MII uP G-MAC MX98726/8 Routip Engine G-MAC MX98726/8 Flash / DRAM HPNA Phone Line 802.11b wireless LAN RF Bluetooth RF MII 8 Port Switch MX98206EC Ethernet Figure 7. MX98206EC (Switch) + MX98726/8EC (G-MAC) System Block Diagram P/N:PM0661 REV. 0.2, JUN. 09, 2000 23 MX98206EC LED Interface Through LED interface, MX98206EC provides visibility of per port utilization (other information of link activity, data rate, and duplex operation mode to be retrieved from the attached PHYs). The utilization information is measured as the ratio of frame data reception over 10Mbps or 100Mbps receive channel. A serial active-low data_out pin is supplied to drive on-board latch buffer circuit for LED monitor. 8-bit utilization per port is provided for physical port performance indication. 8-Bit Value [7:0] 1111_1110 1111_1100 1111_1000 1111_0000 1110_0000 1100_0000 1000_0000 0000_0000 Utilization ~2% ~ 10 % ~ 20 % ~ 35 % ~ 50 % ~ 65 % ~ 80 % ~ 95 % 5-bit utilization indication is also provided. The mapping is depicted below. 5-Bit Value[4:0] 1_1110 1_1100 1_1000 1_0000 0_0000 Utilization ~2% ~ 10 % ~ 35 % ~ 65 % ~ 95 % The LEDCLK provides 1.1MHz timing reference. The serial data is generated on the rising edge of LEDCLK. In the periodic interval of 60 ms the utilization indication is updated once. MX98206EC can provides "all-port" display and "select-port" display as well. An external push-button part is added for implementation of "select-port" display mode. When power-on, port 0 is selected. Once the button is pushed, a high pulse triggers LEDPS pin to make next port be selected to output utilization information. n "all-port" display mode, LEDOUT# sequence is a consecutive stream of 8-bit (or 5-bit) utilization words for port 0 till to port 11. In "select-port" display mode, LEDOUT# sequence contains 8-bit (or 5-bit) utilization word plus 12-bit port I.D., namely '(MSB)0111_1111_1111(LSB)' for port 0, '(MSB)1011_1111_1111(LSB)' for port 1, etc.. The MSB is shifted out first. <Program Register> Reg00H.1, LED_8. User can select 8-bit or 5-bit display mode by defining this bit. P/N:PM0661 REV. 0.2, JUN. 09, 2000 24 MX98206EC Timing Diagram Reset and Clock Timing t03 t01 OSCIN t02 RESET# T# .t01 .t02 .t04 Description System clock period. System clock high time. RESET# low pulse duration. MIN 15 6.7 1 P/N:PM0661 TYP 15.15 7.5 MAX 8.3 UNIT ns ns ms REV. 0.2, JUN. 09, 2000 25 MX98206EC PHY Management (MDIO) Read Timing MDC t11 t15 t12 t13 MDIO T# .t11 .t12 .t13 .t14 .t15 .t16 t16 t14 Register Address TA Q15 Description MDC high time. MDC clock period. MDC falling edge to MDIO delay. MDC falling edge to MDIO Hi-Z. MDIO setup time. MDIO hold time. MIN 3 3 2 2 P/N:PM0661 Q0 TYP 200 400 MAX 8 8 UNIT ns ns ns ns ns ns REV. 0.2, JUN. 09, 2000 26 MX98206EC RMII Interface Timing REFCLK t21 t22 TXEN t23 t24 TXD t25 t26 CRSDV t27 t28 RXD T# .t21 .t22 .t23 .t24 .t25 .t26 .t27 .t28 Description REFCLK high time. REFCLK clock period. REFCLK to TXEN delay. REFCLK to TXD delay. CRSDV setup time. CRSDV hold time. RXD setup time. RXD hold time. MIN 9 3.5 3.5 0 1.5 0 1.5 P/N:PM0661 TYP 10 20 MAX 11 10.5 11.5 UNIT ns ns ns ns ns ns ns ns REV. 0.2, JUN. 09, 2000 27 MX98206EC SSRAM Interface Timing Pipeline, SSRAM Read/Write Cycle OSCIN CE# t31 MA A1 A2 A3 A4 A5 A6 A7 A8 D2 D3 D4 t32 GW# t34 t35 t33 MD Q1 Q2 READ T# .t31 .t32 .t33 .t34 .t35 TA Q3 Q4 D1 TA WRITE Description OSCIN to CE# and GW# delay. OSCIN to MA[17:0] delay. OSCIN to MD[63:0] delay. MD[63:0] setup time. MD[63:0] hold time. Turn around time. MIN 4 4 3.5 1 0.5 2 cycle P/N:PM0661 TYP MAX 10 9.5 11.5 UNIT ns ns ns ns ns REV. 0.2, JUN. 09, 2000 28 MX98206EC Flowthrough, SSRAM Read/Write Cycle OSCIN CE# t31 MA A2 A1 A3 A4 A5 A6 A7 A8 D2 D3 D4 t32 GW# t34 t35 t33 MD Q1 Q2 READ T# TA Q3 Q4 D1 TA Description Turn around time. WRITE MIN P/N:PM0661 TYP 2 cycle MAX UNIT REV. 0.2, JUN. 09, 2000 29 MX98206EC LED Driver Interface Timing t40 LEDCLK t41 t42 t43 t44 LEDOUT# T# .t40 .t41 .t42 .t43 .t44 Description LED update clock period. LEDCLK period. LEDCLK high pulse width. LEDCLK low pulse width. LEDCLK falling edge to LEDOUT# delay. MIN 2 P/N:PM0661 TYP 60 880 440 440 MAX UNIT ms ns ns ns 8 REV. 0.2, JUN. 09, 2000 30 MX98206EC LED Driver Interface Timing OSCIN t51 t50 CMDO t52 EXPDO Data SOF t53 EOF t54 FCOUT t55 t56 CMDI T# .t50 .t51 .t52 .t53 .t54 .t55 .t56 Description CMDO pulse width. OSCIN to COMO delay. OSCIN to EXPDO[15:0] delay. OSCIN to FCOUT delay. FCOUT pulse width. CMDI, EXPDI[15:0], and FCIN setup time CMDI, EXPDI[15:0], and FCIN hold time. MIN 3 3 3 1 cycle 0 2 P/N:PM0661 TYP 1 cycle MAX UNIT 7.5 7.5 7.5 ns ns ns ns ns REV. 0.2, JUN. 09, 2000 31 MX98206EC Expansion Bus Interface Timing OSCIN t50 CMDO EXPDO SOF Data EOF t51 FCOUT T# .t50 .t51 Description CMDO pulse width. FCOUT pulse width. MIN TYP 1 cycle MAX UNIT 1 cycle P/N:PM0661 REV. 0.2, JUN. 09, 2000 32 MX98206EC MII Interface Timing t62 t61 MII_TXC t63 t64 MII_TXEN MII_TXD[3:0] MII_COL MII_CRS t65 MII_RXDV MII_RXD[3:0] t66 T# .t61 .t62 .t63 .t64 .t65 .t66 .t67 Description MII_TXC high time. MII_TXC clock period. MII_TXC rise time. MII_TXC fall time MII_TXC to MII_signal output delay time MII_signal input setup time MII_signal input hold time t67 MIN 16 TYP 20 40 4 4 11.5 3.5 10 10 P/N:PM0661 MAX 24 UNIT ns ns ns ns ns ns ns REV. 0.2, JUN. 09, 2000 33 MX98206EC Electrical Specification Absolute Maximum Ratings Parameter VDD , Supply Voltage. VI , Input Voltage. VO , Output Voltage. II , Input Current. TSTG , Storage Temperature. VESD , Electrostatic Discharge. Value -0.3V ~ +3.6V -0.3V ~ VDD + 0.3V -0.3V ~ VDD + 0.3V +/- 10 mA Recommended Operating Conditions Supply Voltage Operating Temperature Power Dissipation 3.3V +/- 10 % 0o C ~ 70o C DC Characteristics Parameter VOh , Output voltage-high, IOh = VOl , Output voltage-low, IOh = IOZ , High impedance state output current. Iih , Input current-high. Iil , Input current-low. Vih , Input voltage-high. Vil , Input voltage-low. ICC , Supply current. MIN P/N:PM0661 TYP MAX Unit V V uA uA uA V V mA REV. 0.2, JUN. 09, 2000 34 MX98206EC PACKAGE INFORMATION 208-PIN PLASTIC QUAD FLAT PACK A B ITEM MILLIMETERS INCHES A 31.20 .30 1.228 .12 B 28.00 .10 1.102 .004 C 28.00 .10 1.102 .004 D 31.20 .30 1.228 .012 E 25.35 .999 F 1.33 [REF.] .052 [REF.] G 1.33 [REF.] .052 [REF.] H .30 [Typ.] .012 [Typ.] I .65 [Typ.] .026 [Typ.] J 1.60 [REF.] .063 [REF.] K .80 .20 .031 .008 L .15 [Typ.] .006 [Typ.] M .10 max. .004 max. N 3.35 max. .132 max. O .10 min. .004 min. 3.68 max. .145 max. P NOTE: 120 121 81 80 E F Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. 160 1 C D 41 40 G H I J N P L M P/N:PM0661 K O REV. 0.2, JUN. 09, 2000 35 MX98206EC REVISION HISTORY Revision 0.0 0.1 0.2 Destription Preliminary data created. 1. Update eneral Description 2. Modify ontrol Registers 3.Update definition of bit 8 Reg01H 4.Update definition of Reg0DH 5.Modify definition of Reg0EH, 0FH, 10H, and 11H 6.Reserve bit 7-0 Reg12H 7.Delete statement of "! Note" 8.Modify statement of section "PHY Management" 9.Add statement of Ref0EH. 11-0 10.Modify statement of section "Flow Control" 11.Delete statement of Reg01H.8 12.Add statement of Reg0FH.11-0 13.Redefine registers "default value". 1.Update part number and Rev. Info 2.Update general description 3.Add Fig.2 Functional Block Diagram for optional MII port 4.Modify definition of EXPANSION pins 5.Add bits 10-11 and their statement of Reg01H 6.Add Fig.7 for Switch + GMAC configuration 7.Add MII interface Timing 8.Add TOP SIDE MARKING descriptioin P/N:PM0661 Page P1 P08 P10 P12 P13 P13 P14 P16 P16 P17 P18 P18 all pages P01 P03 P06 P12 P23 P33 P37 Date NOV/08/1999 FEB/10/2000 JUN/09/2000 REV. 0.2, JUN. 09, 2000 36 MX98206EC TOP SIDE MARKING MX98206EC line 1 : MX98206EC is MXIC parts No. "E" :PQFP "C" : commercial grade line 2 : Assembly Date Code. line 3 : Wafer Lot No. line 4 : "36C" : revision code, "A" : bonding option "X" : not used line 5 : State C0013 F4044937B1 36CAX TAIWAN MACRONIX INTERNATIONAL CO., LTD. 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