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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
8-Port Dual-Speed Ethernet Switch Controller
FEATURES
• Single-chip 8-por t 10/100Mbps wire-speed switched
Ethernet controller.
• Integration of 8 dual-speed, full/half duplex capable
Media Access Controllers (MACs) with RMII interfaces.
• Support Store-and-Forward switching scheme.
• Support 2.1Gbps (@66MHz) expansion (inter-switch)
bus interface.
• Support source/destination MAC address lookup, learn-
ing, and aging within built-in storage of 1K MAC ad-
dress.
• Optional MII port in replacement of the cascading in-
terface.
GENERAL DESCRIPTION
The MX98206EC is a 8-port 10/100Mbps single-chip
shared-memory Ethernet switch controller . A desktop or
departmental switched Ethernet solution can be achieved
by combining MX98206EC, the necessary physical de-
vices and low-cost memory. All 8 por ts are full-duplex
capable to provide private 20/200Mbps bandwidth con-
nection to power users or servers through external physi-
cal (PHY) layers. System manufacturers can cascade 2
MX98206EC switch controllers to build a 16-port 10/
100Mbps switched Ethernet box easily.
MX98206EC supports store-and-forward switching
scheme with built-in storage of 1K MAC addresses. The
function modules integrated in controller include 8 full-
duplex compatible media access controller with RMII
interface to PHYs, address resolution logic (ARL) for MAC
address learning and recognition, queue manager , and
expansion bus interface for 2 MX98206ECs cascading.
It fully complies with IEEE Std. 802.3/802.3u specifica-
tion, and supports MDC/MDIO interface for physical layer
management with industrial standard physical devices.
The flow control mechanism is provided to prevent buffer
overflow that would force controller to lose packets. Con-
troller will monitor the traffic through receive terminal of
each physical port, and frame queuing status on the data
buff er. Some watermarks are set. As soon as data buffer
PRELIMINARY
• Support IEEE802.3x compliant flow control for FDX
and back-pressure flow control for HDX.
• Support up to 2MB SSRAM (pipeline type, or flow
through type) as data buff er .
• Serial EEPROM interface for auto-configuration.
• Broadcast storm control.
• LED interface f or utilization indication of each port.
• Cascade 2 switch controllers to construct 16 10/
100MBps switched Ethernet ports in a box easily with-
out extra logic.
• 3.3V COMS technology, package in 208-pin PQFP.
is over the warning threshold, flow control mechanism is
triggered to deter the underlying host(s) to transmit frames
for some time. For half-duplex operation port(s), jam pat-
tern is issued to the attached host. For full-duplex opera-
tion port(s), specific "pause" frame of IEEE Std. 802.3x
is issued to host. Moreover, user can program the thresh-
old of broadcast frame storage to discard over-loaded
ones to prevent potential of broadcast storming from
occurring. After buffer fullness drops in the safe margin,
controller releases flow control state to allow physical
ports to work in normal condition.
P er port utilization inf ormation can be retrie v ed through
serial LED interface. User can program the control regis-
ter for "all-port" display mode or "select-port" display mode
with 8-bit indication or 5-bit indication.
System manufactures’ design flexibility is our concern
too. MX98206EC provides expansion bus interface for 2
MX98206ECs cascading. Simple bus protocol is utilized
to control traffic transaction on expansion bus.
MX98206EC also provides an optional MII port f or gen-
eral connection in case no expansion bus is used. In 16-
port Fast Ethernet switch paradigm, only one EEPROM
is required for auto-configuration. Figure 1 and Figure 2
illustrate the functional block diagrams of MX98206EC,
and Figure 3 depicts the pin assignment of MX98206EC.
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
Figure 1. MX98206EC Functional Block Diagram
( with Expansion Bus )
10/100M
MAC
MDC/MDIO
I/F
Expansion
Bus
L2 Address
Table
Address
Resolution
Logic
Queue/SRAM
Manager
MDIO
MTYPE/
MDC
PxCRSDV
PxRXD[1:0]
PxTXEN
PxTXD[1:0]
REFCLK
OSCIN
EXPDI15:0]
CMDI
EXPDO[15:0]
CMDO
FCIN
FCOUT
*
* Note: On RM II i n terfac e, “Px” stan ds for P0 ~P 7 separately.
MSIZE[1:0]
LED
Controller
EEPROM
I/F
Control
Registers
MMODE
MD[63:0]
MA[17:0]
MA16X
GW#
CE#
EEPROM
ECS
ESK
EDI
EDO
LEDPS
LEDCLK
LEDOUT#
MSIZE[1:0]
MMODE
MD[63:0]
MA[17:0]
MA16X
GW#
CE#
EEPROM
ECS
ESK
EDI
EDO
LEDPS
LEDCLK
LEDOUT#
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
Figure 2. MX98206EC Functional Block Diagram
( with Extra MII Port )
MSIZE[1:0]
10/100M
MAC
MDC/MDIO
I/F
L2 Address
Table
Address
Resolution
Logic
Queue/SRAM
Manager
LED
Controller
EEPROM
I/F
Control
Registers
MDIO
MTYPE/
MDC
PxCRSDV
PxRXD[1:0]
PxTXEN
PxTXD[1:0]
REFCLK
OSCIN
MMODE
MD[63:0]
MA[17:0]
MA16X
GW#
CE#
EEPROM
ECS
ESK
EDI
EDO
LEDPS
LEDCLK
LEDOUT#
*
* Note: On RMII i nterface, “Px” stands for P0 ~P7 separat el y.
MII_PORT
MII_RXD[3:0]
MII_RXDV
MII_CRS
MII_TXEN
MII_TXD[3:0]
MII_TXC
MII_COL
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
Figure 3. MX98206EC Pin Diagram Top View
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
MD[14]
MD[13]
MD[12]
MD[11]
MD[10]
MD[9]
MD[8]
MD[7]
MD[6]
MD[5]
MD[4]
MD[3]
MD[2]
MD[1]
MD[0]
GND
MA[17]
MA16X
MA[16]
GW#
CE#
MMODE
MSIZE[1]
MSIZE[0]
OSCIN
GND
VDD
VDD
EDO
EDI
ESK
ECS
EEPROM
GND
FCIN
CMDIN
EXPDI[0]
EXPDI[1]
EXPDI[2]
EXPDI[3]
EXPDI[4]
EXPDI[5]
EXPDI[6]
EXPDI[7]
EXPDI[8]
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
MD[61]
MD[62]
MD[63]
MA[7]
MA[6]
MA[5]
MA[4]
MA[3]
MA[2]
MA[1]
MA[0]
GND
MA[8]
MA[9]
MA[10]
MA[11]
MA[12]
MA[13]
MA[14]
MA[15]
LEDOUT
LEDCLK
LEDPS
VDD
GND
VDD
P7RXD[1]
P7RXD[0]
P7CRSDV
P7TXD[1]
P7TXD[0]
P7TXEN
GND
P6RXD[1]
P6RXD[0]
P6CRSDV
P6TXD[1]
P6TXD[0]
P6TXEN
GND
P5RXD[1]
P5RXD[0]
P5CRSDV
P5TXD[1]
P5TXD[0]
P5TXEN
P4RXD[1]
P4RXD[0]
P4CRSDV
P4TXD[1]
P4TXD[0]
P4TXEN
EXPDO[15]
EXPDO[14]
EXPDO[13]
EXPDO[12]
EXPDO[11]
EXPDO[10]
EXPDO[9]
EXPDO[8]
EXPDO[7]
EXPDO[6]
EXPDO[5]
EXPDO[4]
EXPDO[3]
EXPDO[2]
EXPDO[1]
EXPDO[0]
CMDO
FCOUT
RESET
VDD
REFCLK
GND
VDD
GND
VDD
MDC
MDIO
P0TXEN
P0TXD[0]
P0TXD[1]
P0CRSDV
P0RXD[0]
P0RDX[1]
GND
P1TXEN
P1TXD[0]
P1TXD[1]
P1CRSDV
P1RXD[0]
P1RXD[1]
P2TXEN
P2TXD[0]
P2TXD[1]
P2CRSDV
P2RXD[0]
P2RXD[1]
P3TXEN
P3TXD[0]
P3TXD[1]
P3CRSDV
P3RXD[0]
P3RXD[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
MD[15]
MD[16]
MD[17]
MD[18]
MD[19]
MD[20]
MD[21]
MD[22]
MD[23]
MD[24]
MD[25]
VDD
GND
MD[26]
MD[27]
MD[28]
MD[29]
MD[30]
MD[31]
MD[32]
MD[33]
MD[34]
MD[35]
MD[36]
MD[37]
VDD
GND
MD[38]
MD[39]
MD[40]
MD[41]
MD[42]
MD[43]
MD[44]
MD[45]
MD[46]
MD[47]
MD[48]
MD[49]
GND
VDD
MD[50]
MD[51]
MD[52]
MX98206EC
EXPDI[9]
EXPDI[10]
EXPDI[11]
EXPDI[12]
EXPDI[13]
EXPDI[14]
EXPDI[15]
MD[53]
MD[54]
MD[55]
MD[56]
MD[57]
MD[58]
MD[59]
MD[60]
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
PIN DESCRIPTION
10/100Mbps RMII Interface
PIN # PIN NAME I/O DESCRIPTION
31 P0CRSDV I Carrier sense/Receive data valid. Active high, indicates receive
38 P1CRSDV medium is non-idle. CRSD V is asserted asynchronously with respect
44 P2CRSDV to REFCLK.
50 P3CRSDV
56 P4CRSDV
62 P5CRSDV
69 P6CRSDV
76 P7CRSDV
33-32 P0RXD[1:0] I Receive data. for Port 0 ~ Port 7, synchronous to REFCLK and RXD[1]
40-39 P1RXD[1:0] is MSB. When CRSDV is deasserted, RXD[1:0] is "00".
46-45 P2RXD[1:0]
52-51 P3RXD[1:0]
58-57 P4RXD[1:0]
64-63 P5RXD[1:0]
71-70 P6RXD[1:0]
78-77 P7RXD[1:0]
28 P0TXEN O Transmit enable. Active high, assertion indicates the MAC is present-
35 P1TXEN ing di-bits on TXD[1:0] f or transmission. TXEN is asserted synchro-
41 P2TXEN nously with first nibb le of preamble and remained asserted while all
4 7 P3TXEN di-bits transmitted are presented on RMII. TXEN is negated prior to 1st
53 P4TXEN REFCLK rising edge following the final di-bit of frame.
59 P5TXEN
66 P6TXEN
73 P7TXEN
30-29 P0TXD[1:0] O Transmit data. for P ort 0 ~ Port 7, synchronous to REFCLK and TXD[1]
37-36 P1TXD[1:0] is MSB. When TXEN is asserted, TXD[1:0] is accepted for transmis-
43-42 P2TXD[1:0] sion. TXD[1:0] is "00" when TXEN is deasserted.
49-48 P3TXD[1:0]
55-54 P4TXD[1:0]
61-60 P5TXD[1:0]
68-67 P6TXD[1:0]
75-74 P7TXD[1:0]
21 REFCLK I Reference Clock for RMII interface. 50MHz.
Subtotal 49
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
EXPANSION (inter-switch) BUS INTERFACE/OPTIONAL 10/100M MII INTERFACE
PIN # PIN NAME I/O DESCRIPTION
1 - 4 EXPDO[15:12]/MII_TXD[0:3] O Expansion data Out, EXPDO[15] is MSB. Frame data or
5 EXPDO[11]/MII_TXC command is output to the adjacent cascaded switch con
6 EXPDO[10]/MII_TXEN troller on the bus. A bus transaction consists of a com
7 EXPDO[9]/MII_COL mand phase followed by one or more data phases. Data
8 EXPDO[8]/MII_CRS or command is generated on the rising edge of OSCIN.
9-16 EXPDO[7:0] When CMDO is asserted, the command is on the bus .
Particular "start of Frame" command notifies start of frame
transmission to the adjacent cascaded switch controller;
and "End of F rame" indicates end of transmission.
If MII-PORT is tied to "1" during reset, the multiplexed
pins (pin 1-8) are configured as the output of the 10/100M
MII interface.
193-202 EXPDI[0:9] I Expansion data in. When CMDI is active, command mes
203 EXPDI[10]/MII_PORT sage is sampled on the rising edge of OSCIN. While "Start
204-207 EXPDI[11:14]/MII_RXD[0:3] of F rame" command is detected, s witch controller starts
208 EXPDI[15]/MII_RXD V to receive frame data. Till "End of Frame" presents, switch
controller stops data reception.
If MII_PORT is tied to "1" during reset, the multiplexed
pins (pin203-208) are configured as the input of the 10/
100M MII interface.
17 CMDO O Command enable out. Activ e high, assertion assertion
indicates available command is on the EXPDO[15:0].
192 CMDI I Command enable in. Active high, indicates command is
ready on the EXPDI[15:0].
18 FCOUT O Flow control out. Activ e high, assertion will f orce the ad
jacent cascaded switch controller to suspend current frame
transmission on expansion interface.
191 FCIN I Flow control in. Active high, assertion indicates the adja
cent cascaded controller could not accept any frame data
due to FIFO full.
Subtotal 36
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
BUFFER MEMORY INTERFACE
PIN # PIN NAME I/O DESCRIPTION
102-115 MD[63:50] I/O Memory data bus.64-bit and bi-directional.
118-129 MD[49:38]
132-143 MD[37:26]
146-164 MD[25:7]
165-171 MD[6:0]
174 MA16X O Memory address bus. Where MA[16], MA16X, and MA[17] could be
1 73 MA[17] used for chip enabling.
175 MA[16]
85-92 MA[15:8]
101-94 MA[7:0]
1 76 G W# O Global write. The signal is low f or memory write cycle and is high f or
memory read cycle.
1 77 CE# O Chip enable. Active low , enables memory read or write.
178 MMODE I Memory mode. High is for pipelined SSRAM, low for flowthrough
SSRAM. An external resistor should be connected.
179-180 MSIZE[1:0] I Memory size . Controller supports 3 different buffer memory configura-
tions, where to this pin in all cases.
MSIZE[1:0] = "00" reserved;
"01" 512KB;
"10" 1MB;
"11" 2MB.
External resistors should be connected to the pins in all cases.
Subtotal 88
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MX98206EC
PIN # PIN NAME I/O DESCRIPTION
189 EEPROM I EEPROM enable. Active high. Indicates configuration data is auto-
loaded from EEPROM after reset. In 2-controller cascade structure
only one EEPROM is required. The configuration data of upper half is
for master controller (device=0)*, and that of lower half one is for slave
controller (device=1).
Tying this pin to ground disables EEPROM interface and prevents
auto-configuration.
An external resister should be connected to this pin in all cases.
188 ECS I/O EEPROM chip select. Active high. In 1-controller application it is an
output pin to enable auto-loading from EEPROM. In 2-controller cas-
cade structure the master controller (device=0)* utilizes the pin as an
output pin to trigger slave controller (device=1, on which ECS is an
input pin) and EEPROM.
The pin should be pulled down with external resistor in operating.
1 8 7 ESK I/O EEPROM clock. 515KHz derived from system clock by internal PLL.
For 1-controller application or master controller (device=0)*, it is used
as an output pin to drive EEPROM and slave controller. For slave
controller (device=1), it is used as an input pin to receive clocking
information from master controller .
The pin should be pulled down with external resistor in operating.
1 86 ED I I/O EEPROM data input. The pin is connected to the corresponding EDI
pin on EEPROM part. In 2-controller cascade structure, the pin of
MX98206EC with device = 0 is used as an output pin. In MX98206EC
with device = 1, it is an input pin.
The pin should be pulled down with external resistor in operating.
185 EDO I EEPROM data output. The pin is connected to the corresponding EDO
pin on EEPROM part.
Subtotal 5
EEPROM INTERFACE
* Note: The "device" is designated b y pin LEDOUT# during reset.
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
PIN # PIN NAME I/O DESCRIPTION
181 OSCIN I System clock input. 66MHz. Single 66MHz clock source is used to
drive controller and external data buffer (SSRAM).
19 RESET# I Reset. Active low , be held lo w f or some time after pow er-on.
26 MTYPE/MDC I/O Memory type/Management data clock. During reset, the multiplexed
pin is used as input to identify whether SSRAM is of
1 chip_enable pin, (where MTYPE pulls high) or
3 chip_enable pins, (where MTYPE pulls low).
After reset, the multiplexed pin works as output pin (MDC) to provide
2.5MHz clock ref erence f or MDIO .
27 MDIO I/O Management data. Bi-directional RMII management port data pin.
MDIO is synchronous with respect to MDC, and is sampled on the
rising edge of MDC.
83 LEDCLK I/O Cascade/LED shift clock. During reset, the multiplexed pin is used as
input to identify application structure, where
Pull high, 2-controller cascade structure;
Pull low , 1-controller application.
After reset, the multiplexed pin works as an output pin (LEDCLK) to
provide 1.1MHz clock reference for serial LED data out.
84 LEDOUT# I/O Device/LED data out. During reset, the multiplexed pin is used as an
input pin to designate controller I.D . where
Pull high, device = 1 (slave);
Pull low, device = 0 (master).
After reset, the multiplexed pin works as a serial data out pin. The data
indicates the switch ports’ utilization ratio. LEDOUT# is active-low
serial data, of which "1" (high) bits turn off LED and "0" (low) bits turn
on LED. LEDOUT# is latched by exter nal latch device on the rising
edge of LEDCLK.
82 LEDPS I LED display mode selector . During reset, pull-high makes "all-port"
(PD) displa y mode be selected, while pull-low mak es "select-port" display
mode be chosen. On "select-port" display mode, LEDOUT# stream
contains the selected port number and its utilization data. Where port
selection is through high pulse trigger caused by external switch but-
ton. Power-on port 0 is selected, then the pulse will let controller se-
lect next port's utilization indication.
MISCELLANEOUS
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
20, 23, 25, V D D 3.3V
79, 81, 116,
131, 145,
183, 184
22, 24, 34, G ND
65, 72, 80,
93, 117, 130,
144, 172,
182, 190
Subtotal 30
Offset Register Offset Register
0x00H Configuration 0 0x0AH Port 4/5 RX_Buf Threshold
0x01H Configuration 1 0x0BH Port 6/7 RX_Buf Threshold
0x02H Aging Timer 0x0CH Expansion Port Rx_Buf Threshold
0x03H Time Base 0x0DH Broadcast Storming Control.
0x04H 802.3x Pause Timer 0x0EH Forcd 100/F
0x05H MAC Address 0 0x0FH Force 802.3x Flow Control
0x06H MAC Address 1 0x10H Reserved
0x07H MAC Address 2 0x11H Reserved
0x08H Port 0/1 RX_Buf Threshold 0x12H B/TX_Buf Threshold
0x09H Port 2/3 RX_Buf Threshold
Control Registers
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P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
Configuration 0 (Reg00H), default = 0xC072H
Bit Description Type Default
0.0 Col16#, R/W 0
1: pac ket that runs into 16 consecutive collision will NOT be dropped;
0: packet that runs into 16 consecutive collision will be dropped.
0.1 LED_8, R/W 1
1: 8-bit v alue used f or per port utilization indication;
0: 5-bit v alue used f or per port utilization indication.
0.2 MF, management frame preamble suppression R/W 0
1: controller will send management frames with preamble being suppressed on
MDIO interface;
0: controller will send management frames without preamble suppression.
0.3 Timeout#, R/W 0
1: pack et will NO T be dropped in despite of pack et being queued over 1 second.
0: packet will be dropped if packet has been queued over 1 second.
0.5-4 HashSel, 48-bit D A (SA)_MAC address, is translated separately to 8-bit pointer R /W 1 1
of address table f or address learning and recognition. The translation is by aid
of CRC generator within the controller . The selector helps to fine-tune the
hashing resolution.
00: bits [7:0] of CRC [D A or SA] are selected;
01: bits [15:8] of CRC [DA or SA] are selected;
10: bits [23:16] of CRC[DA or SA] are selected;
11: bits [31:24] of CRC[DA or SA] are selected.
0. 6 RGNT_ext, read cycle extension. The setting assures the accuracy of last data R / W 1
read in read cycle for different SSRAM models used.
0: pipeline SSRAM with 2T/2T character , or flowthrough SSRAM is used;
1: pipeline SSRAM with 2T/1T character is used.
0.15-7 Reserved 0xC00H
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MX98206EC
Configuration 1 (Reg01H), default = 0x001EH
Bit Description Type Default
1.1-0 AbortCnt, When a port is on flow control state , the setting will allow some e xtr a R/W 11
packet reception from attached host, on which the NIC card could not recognize
802.3x "pause" frame or operates at half-duplex mode. If fullness of buffer
memory reaches global reception threshold, some packets are still dropped.
00: 8 packets;
01: 16 packets;
10: 32 packets;
11: all packets.
1.3-2 BPCnt. The setting limits times of jam pattern sending on some half-duplex R / W 00
port that runs into flow control state .
00: back-pressure 8 times then stop;
01: back-pressure 16 times then stop;
10: back-pressure 32 times then stop;
11: back-pressure all the time till the amount of used pages drops into safe margin.
1.5-4 BoffOp, Backoff operation mode. In normal backoff algorithm same packet R /W 0 0
transmission delays {2n -1} (max.) slot time when collision occurs. Modification
of backoff algorithm is utilized to improve switched Ethernet performance on
half-duplex connection.
00: standard algorithm;
01: for first 2 collision follows standard backoff. More than 2 collision in
transmission, packet re-send delays only 0, 1,2,or 3 slot times.
10: packet re-send delays 0 slot time all the time;
11: reserved.
1.6 BPEn#, enable back-pressure flow control on half-duplex connection. R/W 0
1: disable;
0: enable.
1. 7 BP64, jam pattern packet length. R / W 0
1: 64 bytes;
0: 1024 bytes.
1.8 Reserved
1.9 Selmux, R/W 0
1: to re verse port numbering, namely ports 0~7 mapped to ports 7~0 and 8~11
mapped to 11~8;
0: none
1.10 MII-port speed 1:100M ; 0:10M R / W 0
1.11 MII-port duplex 1: Full duple x ; 0: Half duple x R / W 0
1.15-12 Reserved
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MX98206EC
Aging Timer (Reg02H), default = 0x012CH
Bit Description Type Default
2.15-0 The time period is defined to age out the least used entries on address table. R / W 0x12CH
Default is 300 (0x012CH) seconds.
Time Base Register (Reg03H), default = 0x1F78H
Bit Description Type Default
3.15-0 The setting determines count of system clock cycles for 125us. At 66MHz R /0 x1F78H
operation frequency, the count is 0x1F78. Controller utilizes 125us as internal
timing base for control logic.
802.3x Pause Timer (Reg04H), default = 0x01FFH
Bit Description Type Default
4.4-0 Reserved.
4.15-5 TxFCCnt, the timer determines the period, namely pause_time, to inhibit packet R /W 0x00FH
transmission from attached host for flow control.
The variable pause_time of "pause" fr ame is equal to TxFCCnt x 32 + 31.
MAC Address 0 (Reg05H), default = 0x00H
Bit Description Type Default
5.15-0 Controller MAC address bits [15:0]. R/W 0x00H
MAC Address 1 (Reg06H), default = 0x00H
Bit Description Type Default
6.15-0 Controller MAC address bits [31:16]. The MAC address is used in "pause" fr ame R / W 0x00H
MAC Address 2 (Reg07H), default = 0x00H
Bit Description Type Default
7.15-0 Controller MAC address bits [47:32]. R/W 0x00H
Port 0/1 Rx_Buf Threshold (Reg08H), default = **
Bit Description Type Default
8.7-0 Port 0 Rx_Buf Threshold *. R/W **
8.15-8 Port 1 Rx_Buf Threshold *. R/W **
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MX98206EC
Por t 2/3 Rx_Buf Threshold (Reg09H), default = **
Bit Description Type Default
9.7-0 Port 2 Rx_Buf Threshold *. R/W **
9.15-8 P ort 3 Rx_Buf Threshold *. R/W **
Por t 4/5 Rx_Buf Threshold (Reg0AH), default = **
Bit Description Type Default
A.7-0 Port 4 Rx_Buf Threshold *. R/W **
A.15-8 P ort 5 Rx_Buf Threshold *. R/W **
Por t 6/7 Rx_Buf Threshold (Reg0BH), default = **
Bit Description Type Default
B.7-0 Port 6 Rx_Buf Threshold *. R/W **
B.15-8 P ort 7 Rx_Buf Threshold *. R/W **
Expansion Por t Rx_Buf Threshold (Reg0CH), default = ***
Bit Description Type Default
C.7-0 Expansion P ort Rx_Buf Threshold. When the amount of pages used by expansion R/W ***
port's receive terminal is ov er the threshold defined, controller will inform the
adjacent cascaded partner to deter new frame transmission.
C.15-8 Reserved.
Broadcast Storming Control (Reg0DH), default = 0x2000H
Bit Description Type Default
D.12-0 Reserved
D .13 1: enable broadcast packet buffer control; 0: disable. R/W 1
If the amount of pages used by queued broadcast packets is over the threshold
defined in Reg12H, the next broadcast packet received is discarded.
D.15-14 Reserved.
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MX98206EC
Force 100Mbps Full-Duplex Mode, Port Map (Reg0EH), default =0x00H
Bit Description Type Default
E. 7-0 1: Force the corresponding MAC to operate on F ast Ehternet Full-duplex mode, R/W 0x000H
where bit E.7 is used f or port_7 and bit E.0 is used for port_0
E.15-8 Reserved
Force 802.3x Flow Control, Port Map (Reg 0FH), default = 0x00H
Bit Description Type Default
F.7-0 1: Force the corresponding MAC to be capable of IEEE Std, 802.3x frame-base R /W 0x000H
flow control where bit F.7 is used f or port_7, and bit F.0 is used for port_0.
F.15-8 Reserved
Reserved (Reg10H)
Bit Description Type Default
10.15-0 Reserved
Reserved (Reg11H)
Bit Description Type Default
11.15-0 Reserved
B/Tx_Buf Threshold (Reg12H), default = !!
Bit Description Type Default
12.7-0 Reserved
12.15-8 Broadcast Packet Tx_Buf Threshold. R/W !!
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MX98206EC
(Notes for above registers’ definition. Reg08H ~ Reg0CH)
* Note: The amount of used pages (not released) by ph ysical port's receive terminal is counted. If the amount is over
the threshold defined, controller will issue flow control frame on this port.
** Note: The default threshold on each port depends on buffer memory configuration. The setting is
Size: 512KB 1MB 2MB
Default: 0x8H 0x10H 0x20H
The threshold is register setting multiplied by 32.
*** Note: The default threshold on expansion port's receive terminal depends on buffer memory configuration. The
setting is
Size: 512KB 1MB 2MB
Default: 0x20H 0x40H 0x80H
The threshold is register setting m ultiplied by 32.
!! Note: The def ault threshold on total pages occupied by queued frames in e xpansion port's output b uffer or b y
queued broadcast frames depends on buff er memory configuration. The setting is
Size: 512KB 1MB 2MB
Default: 0x30H 0x60H 0xC0H
The threshold is register setting multiplied by 32.
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MX98206EC
Figure 4. Auto-Configuration Diagram in 2-Controller Cascade Structure
Functional Description
Clocks
MX98206EC requires a single 66MHz clock signal at OSCIN input pin as system clock and 50MHz at REFCLK as
timing reference on RMII interfaces. Internal logic derives clock references for other interfaces, namely 2.5MHz clock
applied on MDC/MDIO interface, 1.1Mhz clock on LED serial data interface, and 515KHz clock on EEPROM inter-
f ace. Same on-board 66MHz cloc k source also drives SSRAM parts directly.
Reset
A power-on, or hard reset is initiated by an active-low pulse on RESET# pin. In reset MX98206EC can identify its
"device" number and application structure (1-controller or 2-controller cascade) by pull-up/down the pins of LEDOUT#
and LEDCLK. The initialization process then loads all ports configurable parameters, resets internal state machines
to idle state, initializes embedded layer 2 address table, and frees data buffers. At the completion of reset sequence,
all ports are enabled f or pack et transmission and reception.
In 2-controller cascade structure, only one external EEPROM is required for auto-configuration. If pin of EEPROM is
low, MX98206EC runs under def ault configuration. Figure 4 below sho ws auto-configuration diagram in 2-controller
cascade structure.
MX98206EC
EEPROM
ECS
ESK
EDI
EDO
LEDOUT
MX98206EC
LEDOUT
EDO
EDI
ESK
ECS
EEPROM
“ dev ice = 0 “ “ device = 1 “
LEDCLK LEDCLK
VDD
GND
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MX98206EC
PHY Management
Via auto-negotiation procedure between PHYs on both end of connection link, the transmission mode on the link is
determined. The link operation is classified as 10Mbps-HDX, 10Mbps-FDX, 100Mbps-HDX, and 100Mbps-FDX, where
HDX means half-duplex and FDX means full-duple x. Moreover, under full-duplex mode, it is identified whether either
side supports frame-based flow control or not. MX98206EC through serial MDIO interface continuously monitors the
negotiation result in PHY registers, and MA C of each ph ysical port will operate accordingly.
MX98206EC also provides force-mode configur ing capability to force individual port to r un on Fast Ethernet, full-
duplex mode.
<Programmable Register>
Reg00H.2, MF bit.
Following standard PHY management through MDIO/MDC interface, a pattern of 32 consecutive "1" is used as
preamble in each read-write cycle. Set this bit to support preamble suppressed on management frame dr iven by
MX98207. The standard PHY management READ frame format is
Preamble ST OP PHYAD REGAD TA DATA IDLE
(32 bits) (2 bits) (2 bits) (5 bits) (5 bits) (2 bits) (16 bits)
1.......1 01 10 AAAAA RRRRR Z0 D....D Z
Reg01H.9, selmux bit.
Quad PHYs in the market today have two por t ordering in the chip pinout, clockwise and counter clockwise. The
setting enables system engineers to implement board la yout with an y PHY easily. With def ault setting (selmux = 0),
the PHY of AH104 from Altima Technologies is recommended.
Reg0EH.7-0
When the bit(s) of 8-bit map is set to 1, the corresponding port is forced to run on 100Mbps full-duplx mode,
Frame Reception
The frame received on 2-bit wide receive channel of RMII interface is queued in receive FIFO, and then stored in
external buffer memory . Several error conditions will be identified during data reception,
1.Runt frame error, if the frame size is less than 64 bytes;
2.CRC error , if FCS is not matched to the result of CRC calculation;
3.Long frame error , if fr ame size is larger than 1522 bytes;
4.Alignment error , if frame length is of non-integr al number of octets;
The bad frames will be discarded. If no errors are detected , the frame is stored and forwarded to egress port at wire
speed. Several pages of buffer memory could be occupied for frame storage, on each page 256-byte free memory is
allocated.
The data link management frames, namely IEEE 802.3x "pause" frame is recognized and no frame storage occurs.
Frame T ransmission
F rame tr ansmission begins while the output queue of ph ysical port is not empty. The frame data is mo v ed to output
FIFO from external buffer memory, and converted to 2-bit stream through transmit channel of RMII interface. MX98207
transmits frames in accordance to IEEE 802.3 standard. The egress port is responsible for preamble insertion,
collision back-off, and inter packet gap keeping. While late collision happens on half-duplex por t, the transmitted
frame is aborted. Several control bits are defined on half-duple x mode (see below).
In full-duplex mode, the egress port ignores the signaling of carrier activity and collision detection on channel media.
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MX98206EC
<Programmable Register>
Reg00H.0, Col16#.
Set this bit to drop the transmitted packet which runs into 16 consecutive collisions.
Reg00H.3, Timeout#.
Set this bit to drop frames which have been queued in buffer over 1 second.
Reg01H.5-4, BoffOP.
Set these bits to determine back-off operation mode on half-duple x ports.
Broadcast Storm Control
To prevent network melted down due to broadcast storm, MX98207 can be programmed to restrict storage amount of
broadcast frame inside. While the storage of broadcast frame gets over the threshold, the next coming broadcast
frame(s) is dropped. Three type of frame are vie wed as broadcast frame.
1.Received frame with DL_DA as FF-FF-FF-FF-FF-FF;
2.Receiv ed frame with DL_D A as 1x-xx-xx-xx-xx-xx;
3.Received frame with unknown destination (unicast) address.
<Programmable Register>
Reg0DH.13, enable_key of broadcast storm control.
Reg12H.15-8, broadcast frame storage watermark.
The setting of this byte indicates the maximum amount of pages could be used for broadcast frame storage. Each
page allocates 256-byte space in b uffer memory .
Flow Control
Flow control mechanism is implemented to avoid abnormal packet drop due to traffic congestion on egress ports. The
input traffic on each physical port and global frame queuing is monitored and counted in pages, where each page
allocates 256-byte in buffer memory. Two kinds of thresholds are defined for flow control, namely global reception
threshold per chip, and reception threshold per port.
While the total pages occupied by queued fr ames are ov er the output queuing threshold on certain egress port, the
f orthcoming frame destined to this port is dropped. While the output queue is in saf ety margin again, frame rela y to
this port is back to normal operation.
While the amount of pages used (not released yet) b y certain ingress port is over reception threshold, MX98206EC
will identify this port as heavy b uff er memory consumer and force this port on flow control state. The port is back to
normal operation when several occupied pages are released to free pool.
While the fullness of buff er memory is over global reception threshold, all ports are forced on flow control state. Only
multiple occupied pages are released to free pool, each port will be bac k to normal operation. The global reception
threshold depends on external buffer memory configuration and is set by controller itself.
While physical port(s) is under flow control state, MX98206EC will issue specific "pause" frame on full-duplex port, or
"jam" the half-duplex connection bus to deter further frame transmission from attached host (or device). On full
duple x connection, the attached host will dela y f or period of pause_time defined, and then re-start frame transmis-
sion. On half-duplex connection, the attached host will back-off till jam pattern disappearing, and then re-start frame
transmission. After the delay, if the global reception or reception per por t still runs over threshold, the flow control
procedure repeats.
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MX98206EC
Similar idea is applied to expansion port, except that MX98207 will send out proprietary "stop" command to adjacent
cascaded partner for inhibition of frame transmission, and then send out proprietary "continue" command as soon as
occupied pages being released to free pool.
<Programmable Register>
Reg01H.6, BPEn#, enable_k ey of flow controlling on half-duple x ports.
Reg01H.7, BP64
The bit determines the length of jam pattern used in back-pressure operation.
Reg04H.15-8, TxFCCnt.
Determine the pause_time to be filled in pause frame.
Reg08H, 09H, 0AH, 0BH, 13H, and 14H.
Set reception threshold of each ingress port. The 1-byte variable indicates total pages can be used. Each page
allocates 256-byte space in b uff er memory.
Reg0CH.
Set reception threshold of expansion bus. The 1-byte variable indicates total pages can be used. Each page allocates
256-byte space in b uff er memory .
Reg0DH, enable_k eys of flow controlling on egress ports.
Reg0EH, 0FH, 10H, 11H, 15H, and 16H.
Set output queuing threshold of each egress port. The 1-byte v ariable indicates total pages can be used. Each page
allocates 256-byte space in b uff er memory.
Reg12H.7-0.
Set output queuing threshold on e xpansion b us . The 1-b yte variable indicates total pages can be used. Each page
allocates 256-byte space in b uff er memory.
Reg0FH. 7-0.
When the pyhsical port runs on "forced" 100Mbps full-duplex mode, the corresponding bit on Reg0F. 7-0 can be set to
1 to indicate the MA C supports frame-based flow control mechanism.
Address Learning and Recognition
After a good pack et is receiv ed, address resolution logic begins address lookup . The destination MA C address and
source MAC address associated are retr ieved. The source MAC address is used to build up an address table. By
searching the address table, the unicast destination MAC address will be recognized, and stored frame is forwarded
to destined port.
In both of address learning and recognition, the 48-bit MAC address is converted to a 8-bit search index via hash
transformation. In learning, the entry designated by search index is checked to be valid or not. If non-valid, a new
entry is generated with putting the information of source MAC address and ingress port I.D.. A 4-layer structure is
provided in learning mechanism. If v alid, the 4-lay er mechanism can keep 4 diff erent MAC addresses in one certain
entry to increase hashing resolution. In recognition, the MAC address in table entry designated by search index is
used to compare with destination MA C address. If both are matched, the associated port I.D . in entry is the destina-
tion port. Otherwise, the received frame will be classified as a broadcast frame , and be flooded through ev ery port
(e xcept source port).
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MX98206EC
The memory space within MX98206EC can keep 1K MAC addresses. Aging mechanism is supported, namely the
address information is aged out if not be referred in 300sec (default, the parameter is programmable). The newly learnt
MACs will be kept in table.
Through expansion bus, two address tables used in 2-controller cascade structure are synchronized.
<Programmable Register>
Reg02H.
Aging timer defined to age out the least used entries in address table. Default value is for 300 seconds.
Queue Management
The buff er memory is partitioned into pages, each page allocates 256-byte memory space. Buffer management will
dispatch free pages for each received frame. After frame reception complete, the descriptor information is passed to
buff er controller of the egress port.
For unicast frame, the occupied pages will be released for reuse after transmission complete. For broadcast frame,
switch controller does not make copies of frame, but count the times of transmission of broadcast frame that should
be performed. Till all ports (except source port) complete (broadcast) frame transmission, the occupied pages are
released to free buffer pool.
External (up to 2MB) SSRAM is used for frame buffer . MX98206EC supports Store-and-Forward s witching scheme.
Each frame reception and frame transmission needs to access the e xternal buff er memory. Queue manager g rants
those access requests to provide fair access to the memory, and to meet different traffic throughput on each port
(10M-HDX, 10M-FDX, 100M-HDX, or 100M-FDX). MX98206EC can support up to 4.2Gbps (64b @66MHz) memory
access bandwidth for the oper ation of 12 200Mbps per port (at full-duplex mode) plus tr affic flow on e xpansion bus.
Pins of MTYPE/MDC, MSIZE, and MMODE are provided for flexibility of selection of SSRAMs in system design.
Figure 5 below shows the SSRAM chip_enable diagram with different MTYPE value.
Figure 5. SSRAMs Chip_Enable Diagram with Different MTYPE V alue
GND
MX98206EC
SSRAM
# 0
CE1#
CE2
CE3#
SSRAM
# 1
CE1#
CE2
CE3#
SSRAM
# 2
CE1#
CE2
CE3#
SSRAM
# 3
CE1#
CE2
CE3#
CE#
MA16X
MA[17]
MA[16]
MX98206EC
SSRAM
# 0
CE#
SSRAM
# 1
CE#
SSRAM
# 2
CE#
SSRAM
# 3
CE#
CE#
MA[16]
MA[17]
MA16X
“ MTYPE = 0 ““ MTYPE = 1 “
MTYPE MTYPE
VDD
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MX98206EC
<Programmable Register>
Reg00H.6, RGNT_ext.
The setting depends on SSRAM used.
Expansion Bus Interface
2 MX98206ECs can be cascaded back-to-back through expansion bus interface. The bus interface provides data
receive channel, data transmit channel (both are 16-bit wide, running at up to 66MHz), and control signaling.
The stream on the expansion bus includes pure frame data, address table updating information, and control message.
The operation on e xpansion bus is command-based. The active signal present on CMD_I (or CMD_O) pin indicates
command message on data channel, otherwise frame or address updating inf ormation is on data channel. "Start of
Frame" command associates with beginning of frame data transmission on data channel, then "End of Frame"
terminates data transmission. During frame transmission, controller asserts FCOUT to request cascaded partner to
suspend frame transmission. The address updating inf ormation is used to synchronize both address tab les in cas-
cade architecture, whenever new entry generation.
When the amount of un-relayed frames runs over threshold defined, MX98206EC will issue proprietary "stop" com-
mand to notify the cascaded par tner no further frame reception allowed on data receive channel. Figure 6 below
shows 2-controller cascade structure diagram.
Figure 6. 2-Controller Cascade Structure Diagram
MX98206EC
EXPDO
CMDO
FCOUT
EXPDI
CMDI
LEDOUT
MX98206EC
LEDOUT
“ dev ice = 0 “ “ dev ice = 1 “
EXPDI
CMDI
FCIN
16
EXPDO
CMDO
16
FCIN FCOUT
66MHz
OSCIN
LEDCLK LEDCLK
VDD
GND
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MX98206EC
MII Port Selection and Application
In addition to the cascaded back-to-bac k connection, MX98206EC off ers another w a y to be further integrated into
the internet world. With the MII_P ort pin tied to pull-up, MX98206EC can be configured as a 9-port switch with 8 RMII
+ 1 MII ports, and the extra MII port will act like a general interface to the G-MAC environment, which serves
perfectly in the home gateway architecture.
The ideal system diagram of putting MX98206EC and MX98726EC together is shown in Figure.7. Users can build
their broadband internet system and share the uplink bandwidth into local area network via the G-MAC + Switch
combination.
ADSL
or
cable
modem
Flash / DRAM
uP
Routip
Engine
G-MAC
MX98726/8
G-MAC
MX98726/8
HPNA
Bluetooth
802.11b
wireless
LAN
8 Port Switch
MX98206EC
Internet
Ethernet
Phone Line
RF
RF
MII
MII
Figure 7. MX98206EC (Switch) + MX98726/8EC (G-MAC) System Block Diagram
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MX98206EC
LED Interface
Through LED interf ace , MX98206EC pro vides visibility of per port utilization (other information of link activity, data
rate, and duple x operation mode to be retrieved from the attached PHYs). The utilization information is measured as
the ratio of frame data reception over 10Mbps or 100Mbps receive channel. A serial active-low data_out pin is
supplied to drive on-board latch buffer circuit for LED monitor. 8-bit utilization per port is provided for physical port
performance indication.
5-bit utilization indication is also provided. The mapping is depicted below .
8-Bit Value [7:0] Utilization
1111_1110 ~ 2 %
1111_1100 ~ 10 %
1111_1000 ~ 20 %
1111_0000 ~ 35 %
1110_0000 ~ 50 %
1100_0000 ~ 65 %
1000_0000 ~ 80 %
0000_0000 ~ 95 %
5-Bit Value[4:0] Utilization
1_1110 ~ 2 %
1_1100 ~ 10 %
1_1000 ~ 35 %
1_0000 ~ 65 %
0_0000 ~ 95 %
The LEDCLK provides 1.1MHz timing reference. The serial data is generated on the rising edge of LEDCLK. In the
periodic interval of 60 ms the utilization indication is updated once . MX98206EC can provides "all-port" displa y and
"select-port" display as well. An external push-button part is added for implementation of "select-port" display mode.
When power-on, port 0 is selected. Once the button is pushed, a high pulse triggers LEDPS pin to make next port be
selected to output utilization information.
n "all-port" display mode, LEDOUT# sequence is a consecutive stream of 8-bit (or 5-bit) utilization words f or port 0 till
to port 11. In "select-port" display mode, LEDOUT# sequence contains 8-bit (or 5-bit) utilization word plus 12-bit port
I.D., namely '(MSB)0111_1111_1111(LSB)' for port 0, '(MSB)1011_1111_1111(LSB)' for port 1, etc.. The MSB is
shifted out first.
<Program Register>
Reg00H.1, LED_8.
User can select 8-bit or 5-bit display mode by defining this bit.
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MX98206EC
Timing Diagram
OSCIN
t01
RESET#
t02
t03
T # Description MIN TYP MAX UNIT
.t01 System clock period. 15 15.15 ns
.t02 System clock high time. 6.7 7.5 8.3 ns
.t04 RESET# low pulse duration. 1 ms
Reset and Clock Timing
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MX98206EC
PHY Management (MDIO) Read Timing
T # Description MIN TYP MAX UNIT
.t11 MDC high time. 2 00 ns
.t12 MDC clock period. 400 ns
.t13 MDC f alling edge to MDIO delay. 3 8 ns
.t14 MDC falling edge to MDIO Hi-Z. 3 8 ns
.t15 MDIO setup time. 2 ns
.t16 MDIO hold time. 2 ns
MDC
MDIO
t11
t12
t13 t14
t15 t16
Register
Address Q15 Q0
TA
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MX98206EC
RMII Interface Timing
T # Description MIN TYP MAX UNIT
.t21 REFCLK high time. 9 10 1 1 ns
.t22 REFCLK clock period. 2 0 ns
.t23 REFCLK to TXEN delay. 3.5 10.5 ns
.t24 REFCLK to TXD delay. 3. 5 11.5 ns
.t25 CRSD V setup time . 0 ns
.t26 CRSD V hold time. 1.5 ns
.t27 RXD setup time. 0 ns
.t28 RXD hold time. 1.5 ns
TXD
t22
t23
t24
REFCLK
TXEN
RXD
t25
CRSDV
t21
t26
t27 t28
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MX98206EC
SSRAM Interface Timing
Pipeline, SSRAM Read/Write Cycle
T # Description MIN TYP MAX UNIT
.t31 OSCIN to CE# and GW# delay . 4 1 0 ns
.t32 OSCIN to MA[17:0] delay. 4 9 .5 ns
.t33 OSCIN to MD[63:0] delay. 3.5 11.5 ns
.t34 MD[63:0] setup time. 1 ns
.t35 MD[63:0] hold time. 0.5 ns
TA Turn around time. 2 cycle
MA
OSCIN
CE#
MD
GW#
A1 A2 A3 A4 A5 A6 A7 A8
READ TA WRITE
t34 t35
Q1 Q2 Q3 Q4 D1 D2 D3 D4
t32
t31
t33
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MX98206EC
Flowthrough, SSRAM Read/Write Cycle
T # Description MIN TYP MAX UNIT
TA Turn around time. 2 cycle
MA
OSCIN
CE#
MD
GW#
A1 A2 A3 A4 A5 A6 A7 A8
READ TA WRITE
t34 t35
Q1 Q2 Q3 Q4 D1 D2 D3 D4
t32
t31
t33
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MX98206EC
LED Driver Interface Timing
T # Description MIN TYP MAX UNIT
.t40 LED update clock period. 6 0 ms
.t41 LEDCLK period. 880 ns
.t42 LEDCLK high pulse width. 4 40 ns
.t43 LEDCLK low pulse width. 440 ns
.t44 LEDCLK falling edge to LEDOUT# delay. 2 8
LEDCLK
LEDOUT#
t40
t41
t43
t42
t44
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MX98206EC
LED Driver Interface Timing
T # Description MIN TYP MAX UNIT
.t50 CMDO pulse width. 1 cycle
.t51 OSCIN to COMO delay . 3 7.5 ns
.t52 OSCIN to EXPDO[15:0] dela y . 3 7. 5 ns
.t53 OSCIN to FCOUT delay . 3 7.5 ns
.t54 FCOUT pulse width. 1 cycle
.t55 CMDI, EXPDI[15:0], and FCIN setup time 0 ns
.t56 CMDI, EXPDI[15:0], and FCIN hold time. 2 ns
OSCIN
CMDO
EXPDO
FCOUT
SOF EOF
Data
t50
t52
t51
t53 t54
CMDI
t55 t56
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MX98206EC
Expansion Bus Interface Timing
OSCIN
CMDO
EXPDO
FCOUT
SOF EOFData
t50
t51
T # Description MIN TYP MAX UNIT
.t50 CMDO pulse width. 1 cycle
.t51 FCOUT pulse width. 1 cycle
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MX98206EC
T # Description MIN TYP MAX UNIT
.t61 MII_TXC high time. 16 2 0 2 4 ns
.t62 MII_TXC clock period. 40 ns
.t63 MII_TXC rise time. 4 ns
.t64 MII_TXC fall time 4 ns
.t65 MII_TXC to MII_signal output delay time 3. 5 11.5 ns
.t66 MII_signal input setup time 10 n s
.t67 MII_signal input hold time 1 0 n s
MII Interface Timing
t63 t64
t66
t65
t67
t61
t62
MII_TXC
MII_TXEN
MII_TXD[3:0]
MII_COL
MII_RXDV
MII_RXD[3:0]
MII_CRS
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MX98206EC
Electrical Specification
Absolute Maximum Ratings
Parameter Value
VDD , Supply Voltage . -0.3V ~ +3.6V
VI , Input Voltage. -0.3V ~ VDD + 0.3V
VO , Output Voltage. -0.3V ~ VDD + 0.3V
II , Input Current. +/- 10 mA
TSTG , Storage Temperature.
VESD , Electrostatic Discharge.
DC Characteristics
Parameter MIN TYP MAX Unit
VOh , Output voltage-high, IOh =V
VOl , Output v oltage-low, IOh = V
IOZ , High impedance state output current. uA
Iih , Input current-high. uA
Iil , Input current-low . uA
Vih , Input voltage-high. V
Vil , Input v oltage-lo w. V
ICC , Supply current. mA
Supply Voltage 3.3V +/- 10 %
Operating Temperature 0o C ~ 70o C
Power Dissipation
Recommended Operating Conditions
35
P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
PACKAGE INFORMATION
208-PIN PLASTIC QU AD FLA T P ACK
ITEM MILLIMETERS INCHES
A 31.20 ± .30 1.228 ± .12
B 28.00 ± .10 1.102 ± .004
C 28.00 ± .10 1.102 ± .004
D 31.20 ± .30 1.228 ± .012
E 25.35 .999
F 1.33 [REF.] .052 [REF.]
G 1.33 [REF.] .052 [REF.]
H .30 [Typ.] .012 [Typ.]
I .65 [Typ.] .026 [Typ.]
J 1.60 [REF.] .063 [REF.]
K .80 ± .20 .031 ± .008
L .15 [Typ.] .006 [Typ.]
M .10 max. .004 max.
N 3.35 max. .132 max.
O .10 min. .004 min.
P 3.68 max. .145 max.
NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material
condition.
F
N
MK
L
J
P
O
ECD
401
80
81120
121
160 41
IH
G
B
A
36
P/N:PM0661 REV. 0.2, JUN. 09, 2000
MX98206EC
REVISION HISTORY
Revision Destription Page Date
0.0 Preliminary data created. NO V/08/1999
0.1 1. Update eneral Description P1 FEB/10/2000
2. Modify ontrol Registers P0 8
3.Update definition of bit 8 Reg01H P10
4.Update definition of Reg0DH P12
5.Modify definition of Reg0EH, 0FH, 10H, and 11H P13
6.Reserve bit 7-0 Reg12H P13
7.Delete statement of "! Note" P 14
8.Modify statement of section "PHY Management" P 16
9.Add statement of Ref0EH. 11-0 P16
10.Modify statement of section "Flow Control" P 17
11.Delete statement of Reg01H.8 P18
12.Add statement of Reg0FH.11-0 P18
13.Redefine registers "default value".
0. 2 1.Update part number and Rev. Info all pages JUN/09/2000
2.Update general description P01
3.Add Fig.2 Functional Block Diagr am f or optional MII port P0 3
4.Modify definition of EXPANSION pins P 06
5.Add bits 10-11 and their statement of Reg01H P12
6.Add Fig.7 for Switch + GMAC configuration P 23
7.Add MII interface Timing P 33
8.Add TOP SIDE MARKING descriptioin P37
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
T AIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
37
MX98206EC
MX98206EC
C0013
F4044937B1
36CAX
TAIWAN
TOP SIDE MARKING
line 1 : MX98206EC is MXIC parts No.
"E" :PQFP
"C" : commercial grade
line 2 : Assembly Date Code.
line 3 : W af er Lot No .
line 4 : "36C" : revision code,
"A" : bonding option
"X" : not used
line 5 : State
