SN74LVC1G34 SCES519I - DECEMBER 2003 - REVISED JUNE 2011 www.ti.com SINGLE BUFFER GATE Check for Samples: SN74LVC1G34 FEATURES 1 * 2 * * * * * * Available in the Texas Instruments NanoFreeTM Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.5 ns at 3.3 V Low Power Consumption, 1-A Max ICC 24-mA Output Drive at 3.3 V DBV PACKAGE (TOP VIEW) N.C. A 2 GND 3 * * DCK PACKAGE (TOP VIEW) VCC 5 1 Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) N.C. 1 A 2 GND 3 DRL PACKAGE (TOP VIEW) VCC 5 YZP PACKAGE (TOP VIEW) A B1 GND C1 A GND A1 B1 A2 B2 VCC Y 1 6 VCC A 2 5 N.C. GND 3 4 Y YFP PACKAGE (TOP VIEW) A GND GND 3 4 Y DSF PACKAGE (TOP VIEW) N.C. A GND 1 6 2 5 3 4 VCC N.C. Y Y 1 2 DNU VCC B A No ball C GND Y A C2 2 VCC Table 1. YZP PACKAGE TERMINAL ASSIGNMENTS DNU - Do not use YZV PACKAGE (TOP VIEW) N.C. VCC A2 A 5 Y 4 See mechanical drawings for dimensions. N.C. - No internal connection A1 1 Y 4 DRY PACKAGE (TOP VIEW) DNU N.C. A1 A2 B1 B2 VCC Y Table 2. YZV/YFP PACKAGE TERMINAL ASSIGNMENTS B GND Y A A VCC 1 2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2011, Texas Instruments Incorporated SN74LVC1G34 SCES519I - DECEMBER 2003 - REVISED JUNE 2011 www.ti.com DESCRIPTION/ORDERING INFORMATION This single buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G34 performs the Boolean function Y = A in positive logic. NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Table 3. ORDERING INFORMATION PACKAGE (1) TA NanoFreeTM - WCSP (DSBGA) 0.23-mm Large Bump - YFP SN74LVC1G34YFPR _ _ _ C9_ SN74LVC1G34YZPR _ _ _ C9_ NanoFreeTM - WCSP (DSBGA) Reel of 3000 0.23-mm Large Bump - YZV (Pb-free) SN74LVC1G34YZVR ____ C9 QFN - DSF Reel of 5000 SN74LVC1G34DSFR C9 QFN - DRY Reel of 5000 SN74LVC1G34DRYR C9 Reel of 3000 SN74LVC1G34DBVR Reel of 250 SN74LVC1G34DBVT Reel of 3000 SN74LVC1G34DCKR Reel of 250 SN74LVC1G34DCKT Reel of 4000 SN74LVC1G34DRLR Reel of 3000 NanoFreeTM - WCSP (DSBGA) 0.23-mm Large Bump - YZP -40C to 85C SOT (SOT-23) -DBV SOT (SC-70) - DCK SOT (SOT-553) - DRL (1) (2) TOP-SIDE MARKING (2) ORDERABLE PART NUMBER C34_ C9_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2 has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). FUNCTION TABLE INPUT A OUTPUT Y H H L L LOGIC DIAGRAM (POSITIVE LOGIC) (DBV, DCK, DSF, DRY, DRL, and YZP Package) A 2 4 Y LOGIC DIAGRAM (POSITIVE LOGIC) (YFP and YZV Package) A 2 1 3 Y Copyright (c) 2003-2011, Texas Instruments Incorporated SN74LVC1G34 SCES519I - DECEMBER 2003 - REVISED JUNE 2011 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 6.5 V VI Input voltage range -0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) -0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) -0.5 VCC + 0.5 V IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA (3) Continuous current through VCC or GND JA Package thermal impedance (4) DBV package 206 DCK package 252 DRL package 142 DSF package 300 DRY package 234 YFP/YZP package 132 YZV package Tstg (1) (2) (3) (4) Storage temperature range C/W 116 -65 150 C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Copyright (c) 2003-2011, Texas Instruments Incorporated 3 SN74LVC1G34 SCES519I - DECEMBER 2003 - REVISED JUNE 2011 www.ti.com Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 5.5 1.5 UNIT V 0.65 x VCC VCC = 1.65 V to 1.95 V VIH MIN 1.65 VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 0.7 x VCC VCC = 4.5 V to 5.5 V 0.35 x VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V 0.3 x VCC VCC = 4.5 V to 5.5 V -4 VCC = 1.65 V -8 VCC = 2.3 V IOH High-level output current -16 VCC = 3 V Low-level output current t/v TA (1) 4 Input transition rise or fall rate Operating free-air temperature mA -24 -32 VCC = 4.5 V IOL V VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V mA 24 VCC = 4.5 V 32 VCC = 1.8 V 0.15 V, 2.5 V 0.2 V 20 VCC = 3.3 V 0.3 V 10 VCC = 5 V 0.5 V 10 -40 85 ns/V C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright (c) 2003-2011, Texas Instruments Incorporated SN74LVC1G34 SCES519I - DECEMBER 2003 - REVISED JUNE 2011 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 A VOH 1.65 V 1.2 IOH = -8 mA 2.3 V 1.9 IOL = 100 A 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 (1) 0.4 Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND IO = 0 0.55 0 to 5.5 V 1 A 0 10 A 1 A 500 A 1.65 V to 5.5 V One input at VCC - 0.6 V, Other inputs at VCC or GND V 0.55 4.5 V VI = 5.5 V or GND Ci 3.8 3V IOL = 32 mA ICC 2.3 4.5 V IOL = 24 mA UNIT V IOH = -32 mA IOL = 16 mA II MAX 2.4 3V IOH = -24 mA TYP (1) VCC - 0.1 1.65 V to 5.5 V IOH = -4 mA IOH = -16 mA VOL MIN 3 V to 5.5 V VI = VCC or GND 3.3 V 3.5 pF All typical values are at VCC = 3.3 V, TA = 25C. Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V 0.15 V MIN MAX 2 VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V MIN MAX MIN MAX MIN MAX 1.5 6 1 3.5 1 2.9 9.9 VCC = 5 V 0.5 V UNIT ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V 0.15 V MIN MAX 3.2 VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V MIN MAX MIN MAX MIN MAX 1.5 4.4 1.5 4.1 1 3.2 8.6 VCC = 5 V 0.5 V UNIT ns Operating Characteristics TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 16 16 16 18 Copyright (c) 2003-2011, Texas Instruments Incorporated UNIT pF 5 SN74LVC1G34 SCES519I - DECEMBER 2003 - REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 15 pF 15 pF 15 pF 15 pF 1 M 1 M 1 M 1 M 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Copyright (c) 2003-2011, Texas Instruments Incorporated SN74LVC1G34 SCES519I - DECEMBER 2003 - REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Copyright (c) 2003-2011, Texas Instruments Incorporated 7 PACKAGE OPTION ADDENDUM www.ti.com 21-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G34YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) Addendum-Page 1 Samples (Requires Login) SN74LVC1G34DBVR SNAGCU (3) Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 21-Oct-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LVC1G34YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74LVC1G34YZVR ACTIVE DSBGA YZV 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G34DBVR SOT-23 DBV 5 3000 178.0 9.2 SN74LVC1G34DBVR SOT-23 DBV 5 3000 180.0 SN74LVC1G34DBVT SOT-23 DBV 5 250 178.0 SN74LVC1G34DBVT SOT-23 DBV 5 250 SN74LVC1G34DCKR SC70 DCK 5 SN74LVC1G34DCKR SC70 DCK SN74LVC1G34DCKT SC70 DCK SN74LVC1G34DCKT SC70 SN74LVC1G34DRLR SN74LVC1G34DRLR SN74LVC1G34DRYR 3.3 3.2 1.55 4.0 8.0 Q3 9.2 3.17 3.23 1.37 4.0 8.0 Q3 9.2 3.3 3.2 1.55 4.0 8.0 Q3 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74LVC1G34DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC1G34YFPR DSBGA YFP 4 3000 178.0 9.2 0.89 0.89 0.58 4.0 8.0 Q1 SN74LVC1G34YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 SN74LVC1G34YZVR DSBGA YZV 4 3000 180.0 8.4 1.02 1.02 0.63 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G34DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G34DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0 SN74LVC1G34DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G34DBVT SOT-23 DBV 5 250 205.0 200.0 33.0 SN74LVC1G34DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74LVC1G34DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G34DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74LVC1G34DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G34DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74LVC1G34DRLR SOT DRL 5 4000 180.0 180.0 30.0 SN74LVC1G34DRYR SON DRY 6 5000 180.0 180.0 30.0 SN74LVC1G34DSFR SON DSF 6 5000 180.0 180.0 30.0 SN74LVC1G34YFPR DSBGA YFP 4 3000 220.0 220.0 35.0 SN74LVC1G34YZPR DSBGA YZP 5 3000 220.0 220.0 34.0 SN74LVC1G34YZVR DSBGA YZV 4 3000 220.0 220.0 34.0 Pack Materials-Page 2 X: Max = 0.802 mm, Min =0.742 mm Y: Max = 0.802 mm, Min =0.742 mm X: Max = 0.802 mm, Min =0.742 mm Y: Max = 0.802 mm, Min =0.742 mm X: Max = 0.802 mm, Min =0.742 mm Y: Max = 0.802 mm, Min =0.742 mm IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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