SN74LVC1G34YZVR - Texas Instruments

See mechanical drawings for dimensions.

N.C. – No internal connection

DBV PACKAGE

(TOP VIEW)

GND

VCC

N.C.

DCK PACKAGE

(TOP VIEW)

GND

N.C. VCC

DRL PACKAGE

(TOP VIEW)

VCC

N.C.

GNDGND Y

DRY PACKAGE

(TOP VIEW)

A N.C.

N.C. 6

GND Y

VCC

1N.C.

GND

DSF PACKAGE

(TOP VIEW)

VCC

N.C.

DNU – Do not use

YZP PACKAGE

(TOP VIEW)

C1 C2

A1 A2

GND

DNU VCC

B1 B2

A1 A2

YZV PACKAGE

(TOP VIEW)

GND

AVCC

B1 B2

A1 A2

YFP PACKAGE

(TOP VIEW)

GND

VCC

SN74LVC1G34

www.ti.com

SCES519I –DECEMBER 2003–REVISED JUNE 2011

SINGLE BUFFER GATE

Check for Samples: SN74LVC1G34

1FEATURES

2•Available in the Texas Instruments NanoFree™•Ioff Supports Live Insertion, Partial Power

Package Down Mode, and Back Drive Protection

•Supports 5-V VCC Operation •Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•Inputs Accept Voltages to 5.5 V •ESD Protection Exceeds JESD 22

•Max tpd of 3.5 ns at 3.3 V –2000-V Human-Body Model (A114-A)

•Low Power Consumption, 1-μA Max ICC –200-V Machine Model (A115-A)

• ±24-mA Output Drive at 3.3 V –1000-V Charged-Device Model (C101)

Table 1. YZP PACKAGE TERMINAL

ASSIGNMENTS

1 2

ADNU VCC

BA No ball

CGND Y

Table 2. YZV/YFP PACKAGE TERMINAL

ASSIGNMENTS

BGND Y

AA VCC

1 2

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2NanoFree is a trademark of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN74LVC1G34

SCES519I –DECEMBER 2003–REVISED JUNE 2011

www.ti.com

DESCRIPTION/ORDERING INFORMATION

This single buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G34 performs the Boolean

function Y = A in positive logic.

NanoFree™package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

Table 3. ORDERING INFORMATION

TOP-SIDE

TAPACKAGE(1) ORDERABLE PART NUMBER MARKING(2)

NanoFree™ – WCSP (DSBGA) SN74LVC1G34YFPR _ _ _ C9_

0.23-mm Large Bump –YFP Reel of 3000

NanoFree™ – WCSP (DSBGA) SN74LVC1G34YZPR _ _ _ C9_

0.23-mm Large Bump –YZP

NanoFree™ – WCSP (DSBGA) _ _ _ _

Reel of 3000 SN74LVC1G34YZVR

0.23-mm Large Bump –YZV (Pb-free) C9

µQFN –DSF Reel of 5000 SN74LVC1G34DSFR C9

–40°C to 85°CQFN –DRY Reel of 5000 SN74LVC1G34DRYR C9

Reel of 3000 SN74LVC1G34DBVR

SOT (SOT-23) –DBV C34_

Reel of 250 SN74LVC1G34DBVT

Reel of 3000 SN74LVC1G34DCKR

SOT (SC-70) –DCK Reel of 250 SN74LVC1G34DCKT C9_

SOT (SOT-553) –DRL Reel of 4000 SN74LVC1G34DRLR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.

YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).

YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2

has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).

FUNCTION TABLE

INPUT OUTPUT

A Y

H H

L L

LOGIC DIAGRAM (POSITIVE LOGIC)

(DBV, DCK, DSF, DRY, DRL, and YZP Package)

LOGIC DIAGRAM (POSITIVE LOGIC)

(YFP and YZV Package)

SN74LVC1G34

www.ti.com

SCES519I –DECEMBER 2003–REVISED JUNE 2011

Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VCC Supply voltage range –0.5 6.5 V

VIInput voltage range –0.5 6.5 V

VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V

VOVoltage range applied to any output in the high or low state(2) (3) –0.5 VCC + 0.5 V

IIK Input clamp current VI<0–50 mA

IOK Output clamp current VO<0–50 mA

IOContinuous output current ±50 mA

Continuous current through VCC or GND ±100 mA

DBV package 206

DCK package 252

DRL package 142

θJA Package thermal impedance(4) DSF package 300 °C/W

DRY package 234

YFP/YZP package 132

YZV package 116

Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The value of VCC is provided in the recommended operating conditions table.

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

SN74LVC1G34

SCES519I –DECEMBER 2003–REVISED JUNE 2011

www.ti.com

Recommended Operating Conditions(1)

MIN MAX UNIT

Operating 1.65 5.5

VCC Supply voltage V

Data retention only 1.5

VCC = 1.65 V to 1.95 V 0.65 ×VCC

VCC = 2.3 V to 2.7 V 1.7

VIH High-level input voltage V

VCC = 3 V to 3.6 V 2

VCC = 4.5 V to 5.5 V 0.7 ×VCC

VCC = 1.65 V to 1.95 V 0.35 ×VCC

VCC = 2.3 V to 2.7 V 0.7

VIL Low-level input voltage V

VCC = 3 V to 3.6 V 0.8

VCC = 4.5 V to 5.5 V 0.3 ×VCC

VIInput voltage 0 5.5 V

VOOutput voltage 0 VCC V

VCC = 1.65 V –4

VCC = 2.3 V –8

IOH High-level output current –16 mA

VCC = 3 V –24

VCC = 4.5 V –32

VCC = 1.65 V 4

VCC = 2.3 V 8

IOL Low-level output current 16 mA

VCC = 3 V 24

VCC = 4.5 V 32

VCC = 1.8 V ±0.15 V, 2.5 V ±0.2 V 20

Δt/Δv Input transition rise or fall rate VCC = 3.3 V ±0.3 V 10 ns/V

VCC = 5 V ±0.5 V 10

TAOperating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN74LVC1G34

www.ti.com

SCES519I –DECEMBER 2003–REVISED JUNE 2011

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT

IOH =–100 μA 1.65 V to 5.5 V VCC –0.1

IOH =–4 mA 1.65 V 1.2

IOH =–8 mA 2.3 V 1.9

VOH V

IOH =–16 mA 2.4

3 V

IOH =–24 mA 2.3

IOH =–32 mA 4.5 V 3.8

IOL = 100 μA 1.65 V to 5.5 V 0.1

IOL = 4 mA 1.65 V 0.45

IOL = 8 mA 2.3 V 0.3

VOL V

IOL = 16 mA 0.4

3 V

IOL = 24 mA 0.55

IOL = 32 mA 4.5 V 0.55

IIVI= 5.5 V or GND 0 to 5.5 V ±1μA

Ioff VIor VO= 5.5 V 0 ±10 μA

ICC VI= 5.5 V or GND IO= 0 1.65 V to 5.5 V 1 μA

ΔICC One input at VCC –0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 μA

CiVI= VCC or GND 3.3 V 3.5 pF

(1) All typical values are at VCC = 3.3 V, TA= 25°C.

Switching Characteristics

over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 1)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

FROM TO ±0.15 V ±0.2 V ±0.3 V ±0.5 V

PARAMETER UNIT

(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX

tpd A Y 2 9.9 1.5 6 1 3.5 1 2.9 ns

Switching Characteristics

over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 2)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

FROM TO ±0.15 V ±0.2 V ±0.3 V ±0.5 V

PARAMETER UNIT

(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX

tpd A Y 3.2 8.6 1.5 4.4 1.5 4.1 1 3.2 ns

Operating Characteristics

TA= 25°CVCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

TEST

PARAMETER UNIT

CONDITIONS TYP TYP TYP TYP

Cpd Power dissipation capacitance f = 10 MHz 16 16 16 18 pF

tsu

From Output

Under Test

(see Note A)

LOAD CIRCUIT

S1 VLOAD

Open

GND

Data Input

Timing Input VI

0 V

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPLH

VOH

VOL

0 V

Input

Output

Waveform 1

S1 at VLOAD

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH − V∆≈0 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VLOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.

D. The outputs are measured one at a time, with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

VMVM

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

5 V ± 0.5 V

1 MΩ

VCC RL

2 × VCC

6 V

2 × VCC

VLOAD CL

15 pF

0.15 V

0.3 V

V∆

VCC

3 V

VCC

VCC/2

1.5 V

VCC/2

tr/tf

≤2 ns

≤2.5 ns

INPUTS

SN74LVC1G34

SCES519I –DECEMBER 2003–REVISED JUNE 2011

www.ti.com

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms

tsu

From Output

Under Test

(see Note A)

LOAD CIRCUIT

S1 VLOAD

Open

GND

Data Input

Timing Input VI

0 V

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPLH

VOH

VOL

0 V

Input

Output

Waveform 1

S1 at VLOAD

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH − V∆≈0 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VLOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.

D. The outputs are measured one at a time, with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

VMVM

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

5 V ± 0.5 V

1 kΩ

500 Ω

VCC RL

2 × VCC

6 V

2 × VCC

VLOAD CL

30 pF

50 pF

0.15 V

0.3 V

V∆

VCC

3 V

VCC

VCC/2

1.5 V

VCC/2

tr/tf

≤2 ns

≤2.5 ns

INPUTS

SN74LVC1G34

www.ti.com

SCES519I –DECEMBER 2003–REVISED JUNE 2011

PARAMETER MEASUREMENT INFORMATION

Figure 2. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com 21-Oct-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

SN74LVC1G34DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS