CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] Features * Registered inputs and outputs for pipelined operation The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. * 128K x 32 common I/O architecture * 3.3V core power supply (VDD) * 2.5V/3.3V I/O power supply (VDDQ) * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1339G operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. * Available in lead-free 100-Pin TQFP package, lead-free and non-lead-free 119-Ball BGA package * "ZZ" Sleep Mode Option Logic Block Diagram A 0, A 1, A A DDRESS REGISTER 2 A [1:0] M ODE A DV CLK Q1 BURST COUNTER CLR A ND Q0 LOGIC A DSC A DSP BW D DQ D BYTE W RITE REGISTER DQ D BYTE W RITE DRIVER BW C DQ C BYTE W RITE REGISTER DQ C BYTE W RITE DRIVER DQ B BYTE W RITE REGISTER DQ B BYTE W RITE DRIVER BW B GW CE 1 CE 2 CE 3 OE ZZ ENA BLE REGISTER SENSE A M PS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQ A BYTE W RITE DRIVER DQ A BYTE W RITE REGISTER BW A BW E M EM ORY A RRA Y INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL 1 Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05520 Rev. *F * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 5, 2006 [+] Feedback CY7C1339G Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS Standby Current 40 40 40 40 mA Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP Pinout BYTE C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1339G 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC BYTE B BYTE A MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BYTE D NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC Document #: 38-05520 Rev. *F Page 2 of 18 [+] Feedback CY7C1339G Pin Configurations (continued) 119-Ball BGA Pinout 1 2 3 4 5 VDDQ A NC/288M NC/144M CE2 A A ADSP A A A ADSC VDD A A DQC DQC NC DQC VSS VSS NC CE1 VSS VSS NC DQB DQB DQB F G H J VDDQ DQC DQC VDDQ DQC DQC DQC VDD VSS BWc VSS NC OE ADV GW VDD VSS BWB VSS NC DQB DQB DQB VDD VDDQ DQB DQB VDDQ K DQD DQD VSS CLK VSS DQA DQA L DQD DQD BWD NC BWA DQA DQA M N VDDQ DQD DQD DQD VSS VSS BWE A1 VSS VSS DQA DQA VDDQ DQA P DQD NC VSS A0 VSS NC DQA R T NC NC A MODE VDD A A NC A A NC/72M NC/36M NC ZZ U VDDQ NC NC NC NC NC VDDQ A B C D E 6 7 A VDDQ NC/9M NC/576M A NC/1G Pin Definitions I/O Description A0, A1, A Name InputSynchronous BWA, BWB BWC, BWD InputSynchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 are fed to the two-bit counter.. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous CE2 InputSynchronous CE3 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. OE InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Document #: 38-05520 Rev. *F Page 3 of 18 [+] Feedback CY7C1339G Pin Definitions (continued) Name I/O Description ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical Asynchronous "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs I/OSynchronous VDD Power Supply Power supply inputs to the core of the device. VSS Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state condition. Ground Ground for the core of the device. VDDQ I/O Power Supply Power supply for the I/O circuitry. VSSQ I/O Ground Ground for the I/O circuitry. MODE NC,NC/9M, NC/18M. NC/72M, NC/144M, NC/288M, NC/576M, NC/1G InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. - No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die. Functional Overview all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. The CY7C1339G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Single Read Accesses Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to Document #: 38-05520 Rev. *F This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE Page 4 of 18 [+] Feedback CY7C1339G signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSP The CY7C1339G provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BW[A:D] signals. The CY7C1339G provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1339G is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1339G is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data Burst Sequences Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD - 0.2V tZZS Device operation to ZZ ZZ > VDD - 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to snooze current This parameter is sampled tRZZI ZZ Inactive to exit snooze current This parameter is sampled Document #: 38-05520 Rev. *F Min. Max. Unit 40 mA 2tCYC ns 2tCYC ns 2tCYC 0 ns ns Page 5 of 18 [+] Feedback CY7C1339G Truth Table [2, 3, 4, 5, 6, 7] Operation Add. Used ADSP ADSC ADV Deselect Cycle, Power-down None CE1 CE2 CE3 ZZ H X X L X L X WRITE OE CLK X X L-H Tri-State DQ Deselect Cycle, Power-down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power-down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power-down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power-down None L X H L H L X X X L-H Tri-State Snooze Mode, Power-down None X X X H X X X X X X Tri-State READ Cycle, Begin Burst External L H L L L X X X L L-H Q READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State WRITE Cycle, Begin Burst External L H L L H L X L X L-H D READ Cycle, Begin Burst External L H L L H L X H L L-H Q READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State READ Cycle, Continue Burst Next H X X L X H L H L L-H Q READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05520 Rev. *F Page 6 of 18 [+] Feedback CY7C1339G Partial Truth Table for Read/Write [2, 8] GW BWE BWD BWC BWB BWA Read Function H H X X X X Read H L H H H H Write Byte A - DQA H L H H H L Write Byte B - DQB H L H H L H Write Bytes B, A H L H H L L Write Byte C- DQC H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D- DQD H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Note: 8.Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05520 Rev. *F Page 7 of 18 [+] Feedback CY7C1339G Maximum Ratings DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. -65C to +150C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied............................................. -55C to +125C Operating Range Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V Range Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD Commercial DC Voltage Applied to Outputs in tri-state ............................................ -0.5V to VDDQ + 0.5V Ambient Temperature 0C to +70C Industrial -40C to +85C Automotive -40C to +125C VDD VDDQ 3.3V -5%/+10% 2.5V -5% to VDD Electrical Characteristics Over the Operating Range[9, 10] Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.6 V VDDQ I/O Supply Voltage 2.375 VDD V VOH Output HIGH Voltage VOL VIH VIL IX Output LOW Voltage Input HIGH Input LOW Voltage[9] Voltage[9] Input Leakage Current except ZZ and MODE for 3.3V I/O, IOH = -4.0 mA 2.4 V for 2.5V I/O, IOH = -1.0 mA 2.0 V for 3.3V I/O, IOL = 8.0 mA 0.4 V for 2.5V I/O, IOL = 1.0 mA 0.4 V for 3.3V I/O 2.0 VDD + 0.3V V for 2.5V I/O 1.7 VDD + 0.3V V for 3.3V I/O -0.3 0.8 V for 2.5V I/O -0.3 0.7 V -5 5 A GND VI VDDQ Input Current of MODE Input = VSS 5 Input = VDD Input Current of ZZ 30 A 5 A 4-ns cycle, 250 MHz 325 mA 5-ns cycle, 200 MHz 265 mA 6-ns cycle, 166 MHz 240 mA 7.5-ns cycle, 133 MHz 225 mA 4-ns cycle, 250 MHz 120 mA 5-ns cycle, 200 MHz 110 mA 6-ns cycle, 166 MHz 100 mA Industrial/ 7.5-ns cycle, 133 MHz Commercial 90 mA Automotive 7.5-ns cycle, 133 MHz 115 mA All speeds 40 mA IOZ Output Leakage Current GND VI VDDQ, Output Disabled IDD VDD Operating Supply Current ISB2 Automatic CE Power-down Current--TTL Inputs A A -5 Input = VSS Input = VDD ISB1 A -30 VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC Automatic CE VDD = Max, Device Deselected, Power-down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 -5 Notes: 9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 10. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05520 Rev. *F Page 8 of 18 [+] Feedback CY7C1339G Electrical Characteristics Over the Operating Range[9, 10] (continued) Parameter Description Test Conditions VDD = Max, Device Deselected, or Automatic CE Power-down VIN 0.3V or VIN > VDDQ - 0.3V Current--CMOS Inputs f = fMAX = 1/tCYC ISB3 Automatic CE Power-down Current--TTL Inputs ISB4 VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 Min. Max. Unit 4-ns cycle, 250 MHz 105 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.5-ns cycle, 133 MHz 75 mA All Speeds 45 mA BGA Package Unit Capacitance[11] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions TQFP Package TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V 5 5 pF 5 5 pF 5 7 pF Test Conditions TQFP Package BGA Package Unit 30.32 34.1 C/W 6.85 14.0 C/W Thermal Resistance[11] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 Thermal Resistance (Junction to Case) AC Test Loads and Waveforms 3.3V I/O Test Load R = 317 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50 Z0 = 50 10% GND 5 pF R = 351 VT = 1.5V INCLUDING JIG AND SCOPE (a) (c) R = 1667 2.5V OUTPUT 10% R = 1538 VT = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF (a) ALL INPUT PULSES VDDQ OUTPUT RL = 50 Z0 = 50 1 ns 1 ns (b) 2.5V I/O Test Load 90% 10% 90% (b) 1 ns 1 ns (c) Note: 11. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05520 Rev. *F Page 9 of 18 [+] Feedback CY7C1339G Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17] -250 Parameter tPOWER Description Min. [12] VDD(Typical) to the first Access Max. -200 Min. Max. -166 Min. Max. -133 Min. Max. Unit 1 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5.0 6.0 7.5 ns tCH Clock HIGH 1.7 2.0 2.5 3.0 ns tCL Clock LOW 1.7 2.0 2.5 3.0 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise [13, 14, 15] 2.6 1.0 2.8 1.0 1.5 1.5 ns Clock to Low-Z Clock to High-Z[13, 14, 15] 2.6 2.8 3.5 4.0 ns tOEV OE LOW to Output Valid 2.6 2.8 3.5 4.0 ns tOEHZ OE LOW to Output OE HIGH to Output High-Z[13, 14, 15] 0 0 ns tCHZ tOELZ 0 4.0 tCLZ Low-Z[13, 14, 15] 0 3.5 0 2.6 0 0 2.8 ns 0 3.5 ns 4.0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns tADS ADSC, ADSP Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns tADVS ADV Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns tWES GW, BWE, BWX Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 ns tAH Address Hold After CLK Rise 0.3 0.5 0.5 0.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.3 0.5 0.5 0.5 ns tADVH ADV Hold After CLK Rise 0.3 0.5 0.5 0.5 ns Hold Times tWEH GW, BWE, BWX Hold After CLK Rise 0.3 0.5 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 ns Notes: 12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 15. This parameter is sampled and not 100% tested. 16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 17. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05520 Rev. *F Page 10 of 18 [+] Feedback CY7C1339G Switching Waveforms Read Cycle Timing[18] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BW[A:D] tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON'T CARE UNDEFINED Note: 18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05520 Rev. *F Page 11 of 18 [+] Feedback CY7C1339G Switching Waveforms (continued) Write Cycle Timing[18, 19] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BW[A :D] tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON'T CARE Extended BURST WRITE UNDEFINED Note: 19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document #: 38-05520 Rev. *F Page 12 of 18 [+] Feedback CY7C1339G Switching Waveforms (continued) Read/Write Cycle Timing[18, 20, 21] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BW[A:D] tCES tCEH CE ADV OE tDS tCO tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON'T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 20. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 21. GW is HIGH. Document #: 38-05520 Rev. *F Page 13 of 18 [+] Feedback CY7C1339G Switching Waveforms (continued) ZZ Mode Timing [22, 23] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON'T CARE Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 23. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05520 Rev. *F Page 14 of 18 [+] Feedback CY7C1339G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1339G-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1339G-133BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1339G-133AXE 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Automotive CY7C1339G-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1339G-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1339G-166BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1339G-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1339G-166BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1339G-166BGXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1339G-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1339G-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1339G-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1339G-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Document #: 38-05520 Rev. *F Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1339G-250AXI CY7C1339G-250BGXI Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1339G-250AXC CY7C1339G-250BGXC Commercial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1339G-200AXI CY7C1339G-200BGXI Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1339G-200AXC CY7C1339G-200BGXC 250 Operating Range 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1339G-133AXI CY7C1339G-133BGXI 200 Package Type CY7C1339G-133AXC CY7C1339G-133BGXC 166 Package Diagram Industrial 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free Page 15 of 18 [+] Feedback CY7C1339G Package Diagrams 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.000.20 1.400.05 14.000.10 81 100 80 1 20.000.10 22.000.20 0.300.08 0.65 TYP. 30 121 (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0 MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0-7 R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.600.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL Document #: 38-05520 Rev. *F A Page 16 of 18 [+] Feedback CY7C1339G Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) O0.05 M C O0.25 M C A B A1 CORNER O0.750.15(119X) O1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.000.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30 TYP. 14.000.20 0.15(4X) 0.15 C 2.40 MAX. B 0.900.05 0.25 C 12.00 51-85115-*B C 0.600.10 0.56 SEATING PLANE All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05520 Rev. *F Page 17 of 18 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1339G Document History Page Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM Document Number: 38-05520 REV. Orig. of ECN NO. Issue Date Change Description of Change ** 224368 See ECN RKF New data sheet *A 288909 See ECN VBL In Ordering Info section, Changed TQFP to PB-free TQFP Added PB-free BG package *B 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBDs for JA and JC to their respective values on the Thermal Resistance table Updated the Ordering Information by shading and unshading MPNs as per availability *C 351194 See ECN PCI Updated Ordering Information Table *D 366728 See ECN PCI Added VDD/VDDQ test conditions in DC Table Modified test condition in note# 10 from VIH < VDD to VIH < VDD *E 420883 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Added Automotive Range in Operating Range Table Updated the Ordering Information *F 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Updated the Ordering Information table. Document #: 38-05520 Rev. *F Page 18 of 18 [+] Feedback