CY7C1339G-133AXCT - Cypress Semiconductor

4-Mbit (128K x 32) Pipelined Sync SRAM

CY7C1339G

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05520 Rev. *F Revised July 5, 2006

Features

• Registered inp uts and outputs for pipelined op eration

• 128K × 32 common I/O architectur e

• 3.3V core power supply (VDD)

• 2.5V/3.3V I/O power supply (VDDQ)

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel®

Pentium® interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchr onous output ena bl e

• A vailable in lead-free 100-Pin TQFP package, lead-free

and non-lead-fre e 119-Ball BGA package

• “ZZ” Sleep Mode Option

Functional Description[1]

The CY7C1339G SRAM integrates 128K x 32 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW[A:D], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1339G operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS

ADV

CLK BURST

COUNTER

AND

LOG IC

CLR

ADSP

ADSC

MODE

BWE

ENABLE

OUTPUT

REGISTERS

SEN SE

AMPS

OUTPUT

BU FFERS

PIPELINED

ENABLE

INPUT

REGISTERS

A0, A1, A

MEMORY

ARRAY

DQs

SLEEP

CONTROL

[1:0]

DQA

BYTE

W RITE REG ISTER

DQB

BYTE

WRITE REGISTER

DQC

BYTE

W RITE REG ISTER

DQD

BYTE

WRITE REGISTER

DQA

BYTE

WRITE DRIVER

DQB

BYTE

WRITE DRIVER

DQC

BYTE

WRITE DRIVER

DQD

BYTE

WRITE DRIVER

Logic Block Diagram

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 2 of 18

Pin Configurations

Selection Guide

250 MHz 200 MHz 166 MHz 133 MHz Unit

Maximum Access Time 2.6 2.8 3.5 4.0 ns

Maximum Operating Current 325 265 240 225 mA

Maximum CMOS Standby Current 40 40 40 40 mA

NC/72M

NC/36M

VSS

VDD

NC/18M

NC/9M

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

BYTE A

BYTE B

BYTE D

BYTE C

CY7C1339G

100-Pin TQFP Pinout

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 3 of 18

Pin Configurations (continued)

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LOW , and CE1, CE2, and CE3 are sampled active. A1, A0

are fed to the two-bit counter..

BWA, BWB

BWC, BWDInput-

Synchronous Byte Write Select Inputs, active LOW . Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW Input-

Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global

write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).

BWE Input-

Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

CLK Input-

Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW , during a burst operation.

CE1Input-

Synchronous Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with

CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

when a new external address is loaded.

CE2Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE3 to select/deselect the device.CE2 is sampled only when a new external address is

loaded.

CE3Input-

Synchronous Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is

loaded. Not connected for BGA. Whe r e referenced, CE3 is assumed active throughout this

document for BGA.

OE Input-

Asynchronous Output Enable, asynchronous input, active LOW . Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as

input data pins. OE is masked during the first clock of a read cycle when emerging from a

deselected state.

2345671

VDDQ

NC/288M

NC/144M NCDQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

CE2A

DQC

VDDQ

DQC

VDDQ

DQD

NC VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

NCNCNCNC NC/36MNC/72M NC

VDDQ

AAAA

NC/9M

AA0

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS NC

MODE

BWB

BWc

NC VDD NC

BWA

BWE

BWD

119-Ball BGA Pinout

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 4 of 18

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (tCO) is 2.6 ns

(250-MHz device).

The CY7C1339G supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486™

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW , (2)

CE1, CE2, CE3 are all asserted active, and (3) the Write

signals (GW , BWE) are all deserted HIGH. ADSP is ignored if

CE1 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the Address

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 2.6 ns (250-MHz device) if OE is active

LOW. The onl y exception occurs w hen the SR AM is emerg ing

from a deselected state to a selected state, its outputs are

always tri-stated during the first cycle of the access. After the

first cycle of the access, the outputs are controlled by the OE

ADV Input-

Synchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

Synchronous Address Strobe from Processor, sampled on the rising edge of CL K, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1, A0

are also loaded into the burst counter . When ADSP and ADSC are both asserted, only ADSP is

recognized. ASDP is ignored when CE1 is deasserted HIGH.

ADSC Input-

Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1, A0

are also loaded into the burst counter . When ADSP and ADSC are both asserted, only ADSP is

recognized.

ZZ Input-

Asynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or

left floating. ZZ pin has an internal pull-down.

DQs I/O-

Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The direction

of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When

HIGH, DQs are placed in a tri-state conditi o n.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the core of the device.

VDDQ I/O Power

Supply Power supply for the I/O circuitry.

VSSQ I/O Ground Ground for the I/O circuitry.

MODE Input-

Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left

floating selects interleaved burst sequence. This is a strap pin and should remain static during

device operation. Mode Pin has an internal pull-up.

NC,NC/9M,

NC/18M.

NC/72M,

NC/144M,

NC/288M,

NC/576M,

NC/1G

–No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M,

NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the

die.

Pin Definitions (continued)

Name I/O Description

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 5 of 18

signal. Consecutive single Read cycles are supported. Once

the SRAM is deselected at clock rise by the chip select and

either ADSP or ADSC signals, its output will tri-state immedi-

ately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE1, CE2, CE3 are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array . The Write signals (GW , BWE, and BW[A:D]) and

ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW[A:D]

signals. The CY7C133 9G provides Byte Write capability that

is described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

Wri te (B W[A:D]) input, will selectively w rite to only the desired

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.

Because the CY7C1339G is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQs inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and

(4) the appropriate combination of the Write inputs (GW , BWE,

and BW[A:D]) are asserted active to conduct a Write to the

desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancement logic while being delivered to the memory array .

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to the DQs is written into the

corresponding address location i n the memory core. If a Byte

Write is conducted, only the selected byte s are written. Bytes

not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations.

Because the CY7C1339G is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQs inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Burst Sequen ce s

The CY7C1339G provides a two-bit wraparound counter, fed

by A1, A0, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst se quence. T he burst seq uence is user se lectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected p rior to entering

the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must

remain inactive for the duration of tZZREC after the ZZ input

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Snooze mode standby current ZZ > VDD – 0.2V 40 mA

tZZS Device operati on to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to snooze current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit snooze current This parameter is sampled 0 ns

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 6 of 18

Truth Table[2, 3, 4, 5, 6, 7]

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power-down None H X X L X L X X X L-H Tri-State

Deselect Cycle, Power-down None L L X L L X X X X L-H Tri-State

Deselect Cycle, Power-down None L X H L L X X X X L-H Tri-State

Deselect Cycle, Power-down None L L X L H L X X X L-H Tri-State

Deselect Cycle, Power-down None L X H L H L X X X L-H Tri-State

Snooze Mode, Power-down None X X X H X X X X X X Tri-State

READ Cycle, Begin Burst External L H L L L X X X L L-H Q

READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

WRITE Cycle, Begin Burst External L H L L H L X L X L-H D

READ Cycle, Begin Burst External L H L L H L X H L L-H Q

READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

READ Cycle, Continue Burst Next X X X L H H L H L L-H Q

READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D

WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D

READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byt e Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals

(BWA, BWB, BWC, BWD), BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

6. The SRAM always initiates a read cycle when ADSP is asse rted, regard less of the st ate of GW, BWE, or BW[A: D]. Writes may occur only on subsequen t clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

don't care for the remainder of the write cycle.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycle s. During a read cycle a ll d ata bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 7 of 18

Partial Truth Table for Read/Write[2, 8]

Function GW BWE BWDBWCBWBBWA

Read HHXXXX

Read HLHHHH

Write Byte A – DQAHLHHHL

Write Byte B – DQBHLHHLH

Write Bytes B, A H L H H L L

Write Byte C– DQCHLHLHH

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D– DQDHLLHHH

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B HLLLLH

Write All Bytes HLLLLL

Write All Bytes LXXXXX

Note:

8.Table only lists a partial listin g of the byte write combinati ons. Any combination of BW X is valid. Appropriate write will be done based on which byte write is active.

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 8 of 18

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +4.6V

Supply Voltage on VDDQ Relative to GND......–0.5V to +VDD

DC Voltage Appli ed to Outputs

in tri-state............. .. ............................. –0.5V to VDDQ + 0.5V

DC Input Voltage ............................... ... .–0.5V to VDD + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current............... ... ... ............................... > 200 mA

Operating Range

Range Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V

–5%/+10% 2.5V –5%

to VDD

Industrial –40°C to +85°C

Automotive –40°C to +125°C

Electrical Characteristics Over the Operating Range[9, 10]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage 2.375 VDD V

VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V

for 2.5V I/O, IOH = –1.0 mA 2.0 V

VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA 0.4 V

for 2.5V I/O, IOL = 1.0 mA 0.4 V

VIH Input HIGH Voltage[9] for 3.3V I/O 2.0 VDD + 0.3V V

for 2.5V I/O 1.7 VDD + 0.3V V

VIL Input LOW Voltage[9] for 3.3V I/O –0.3 0.8 V

for 2.5V I/O –0.3 0.7 V

IXInput Leakage Current

except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5 µA

Input Current of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply

Current VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 325 mA

5-ns cycle, 200 MHz 265 mA

6-ns cycle, 166 MHz 240 mA

7.5-ns cycle, 133 MHz 225 mA

ISB1 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 120 mA

5-ns cycle, 200 MHz 110 mA

6-ns cycle, 166 MHz 100 mA

Industrial/

Commercial 7.5-ns cycle, 133 MHz 90 mA

Automotive 7.5-ns cycle, 133 MHz 1 15 mA

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f = 0

All speeds 40 mA

Notes:

9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

10.TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

[+] Feedback [+] Feedback

CY7C1339G

Document #: 38-05520 Rev. *F Page 9 of 18

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected, or

VIN ≤ 0.3V or VIN > VDDQ – 0.3V

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 105 mA

5-ns cycle, 200 MHz 95 mA

6-ns cycle, 166 MHz 85 mA

7.5-ns cycle, 133 MHz 75 mA

ISB4 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0 All Speeds 45 mA

Capacitance[11]

Parameter Description Test Conditions TQFP

Package BGA

Package Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 3.3V

55pF

CCLK Clock Input Capacitance 5 5 pF

CI/O Input/Output Capacitance 5 7 pF

Thermal Resistance[11]

Parameter Description Test Conditions TQFP

Package BGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient) Test conditi ons follow standard test

methods and procedures for

measuring thermal impedance, per

EIA/JESD51

30.32 34.1 °C/W

ΘJC Thermal Resistance

(Junction to Case) 6.85 14.0 °C/W

AC Test Loads and Waveforms

Note:

11.Tested initially and after any design or proc ess change that may affect these parameters.

Electrical Characteristics Over the Operating Range[9, 10] (continued)

Parameter Description Test Conditions Min. Max. Unit

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

OUTPUT

R = 1667Ω

R = 1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

OUTPUT

R = 1667Ω

R = 1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

2.5V I/O Test Load

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CY7C1339G

Document #: 38-05520 Rev. *F Page 10 of 18

Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17]

Parameter Description

–250 –200 –166 –133

UnitMin. Max. Min. Max. Min. Max. Min. Max.

tPOWER VDD(Typical) to the first Access[12] 1111ms

Clock

tCYC Clock Cycle Time 4.0 5.0 6.0 7.5 ns

tCH Clock HIGH 1.7 2.0 2.5 3.0 ns

tCL Clock LOW 1.7 2.0 2.5 3.0 ns

Output Times

tCO Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns

tDOH Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns

tCLZ Clock to Low-Z[13, 14, 15] 0000ns

tCHZ Clock to High-Z[13, 14, 15] 2.6 2.8 3.5 4.0 ns

tOEV OE LOW to Output Valid 2.6 2.8 3.5 4.0 ns

tOELZ OE LOW to Output Low-Z[13, 14, 15] 0000ns

tOEHZ OE HIGH to Output High-Z[13, 14, 15] 2.6 2.8 3.5 4.0 ns

Set-up Times

tAS Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tADS ADSC, ADSP Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tADVS ADV Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tWES GW, BWE, BWX Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tDS Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

tCES Chip Enable Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 ns

Hold Times

tAH Address Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tADH ADSP, ADSC Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tADVH ADV Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tWEH GW, BWE, BWX Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tDH Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

tCEH Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

Notes:

12.This pa rt has a voltage regulat or internally; tPOWER is the time t hat the power needs to be supplied above VDD(minimum) initially before a r ead or write operation

can be initiated.

13.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transit ion is measured ± 200 mV from steady-state voltage.

14.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specificat ions do n ot imply a bus cont entio n con dition, bu t ref lect parameters guaranteed over worst ca se user conditi ons. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

15.This p a rameter is sampled and not 100% tested.

16.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

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CY7C1339G

Document #: 38-05520 Rev. *F Page 11 of 18

Switching Waveforms

Read Cycle Timing[18]

Note:

18.On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

BW[A:D]

ata Out (Q) High-Z

tCLZ tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

ADV

suspends

burst.

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1) Q(A2)

Q(A2 + 1)

Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

DON’T CARE UNDEFINED

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CY7C1339G

Document #: 38-05520 Rev. *F Page 12 of 18

Write Cycle Timing[18, 19]

Note:

19.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BW[A :D]

ata Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2)

D(A2 + 1) D(A2 + 1)

D(A1) D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are

ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

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CY7C1339G

Document #: 38-05520 Rev. *F Page 13 of 18

Read/Write Cycle Timing[18, 20, 21 ]

Notes:

20.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

21.GW is HIGH.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BW[A:D]

ata Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

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CY7C1339G

Document #: 38-05520 Rev. *F Page 14 of 18

ZZ Mode Timing [22, 23]

Notes:

22.Device must be deselected when entering ZZ mode. See Cycle Descriptions t able for all possible signal conditions to deselect the device.

23.DQs are in high-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

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CY7C1339G

Document #: 38-05520 Rev. *F Page 15 of 18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

133 CY7C1339G-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1339G-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-133BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1339G-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

CY7C1339G-133BGI 51-85115 119 -ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-133BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1339G-133AXE 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Automotive

166 CY7C1339G-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1339G-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-166BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1339G-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

CY7C1339G-166BGI 51-85115 119 -ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-166BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

200 CY7C1339G-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1339G-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-200BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1339G-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

CY7C1339G-200BGI 51-85115 119 -ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-200BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

250 CY7C1339G-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1339G-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-250BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1339G-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

CY7C1339G-250BGI 51-85115 119 -ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1339G-250BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

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CY7C1339G

Document #: 38-05520 Rev. *F Page 16 of 18

Package Diagrams

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

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CY7C1339G

Document #: 38-05520 Rev. *F Page 17 of 18

© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Diagrams (continued)

1.27

20.32

2165437

12.00

19.50

30° TYP.

2.40 MAX.

A1 CORNER

0.70 REF.

2143657

Ø1.00(3X) REF.

7.62

22.00±0.20

14.00±0.20

1.27

0.60±0.10

0.15 C

0.15(4X)

Ø0.05 M C

Ø0.75±0.15(119X)

Ø0.25MCAB

SEATING PLANE

0.90±0.05

3.81

10.16

0.25 C

0.56

51-85115-*B

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

All products and company names mentioned in this document ma y be the trademarks of their respective holders.

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CY7C1339G

Document #: 38-05520 Rev. *F Page 18 of 18

Document History Page

Document Title: CY7C1339G 4-Mbit (128K x 32) Pipeline d Sync SRAM

Document Number: 38-05520

REV. ECN NO. Issue Date Orig. of

Change Description of Cha ng e

** 22 4368 See ECN RKF New data sheet

*A 288909 See ECN VBL In Ordering Info section, Changed TQFP to PB-free TQFP

Added PB-free BG package

*B 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA

Package as per JEDEC standards and updated the Pin Definitions accordin gly

Modified VOL, VOH test conditions

Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resis-

tance table

Updated the Ordering Information by shading and unshading MPNs as per

availability

*C 351194 S ee ECN PCI Upda ted Ordering Informa tion Table

*D 366728 See ECN PCI Added VDD/VDDQ test conditions in DC Table

Modified test condition in note# 10 from VIH < VDD to VIH < VDD

*E 420883 See ECN RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

North First Street” to “198 Champion Court”

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristi cs Table

Replaced Package Name column with Package Diagram in the Ordering In for-

mation table

Replaced Package Diagram of 51-85050 from *A to *B

Added Automotive Range in Operating Range Table

Updated the Ordering Information

*F 48 0368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Updated the Ordering Information table.

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