DS-CPC1466 - R00B www.clare.com 1
PRELIMINARY
CPC1466
Broadband ADSL/VDSL DC Termination IC
Features
•Meets wetting (sealing) current requirements per
ITU-T G.991.2
•Integrated bridge rectifier for polarity correction
•Uses inexpensive opto-coupler for DC sealing
current monitoring
•Electronic inductor, breakover, and latch circuits
•Current limiting and excess power protection circuits
•ADSL/VDSL compatible with low-pass filter network
•MLT and SARTS compatible
•Compatible with portable test sets
•Small SOIC or Micro-Leadframe Package (MLP)
•MLP package 60 percent smaller than SOIC
Applications
•ADSL/VDSL broadband modems
•Router and bridge customer premises equipment
•Leased line equipment
•Mechanized Loop Test (MLT) networks
•Switched Access Remote Test System (SARTS)
networks
Figure 1. CPC1466 Block Diagram
Description
The CPC1466 is a DC Termination IC for broadband
ADSL/VDSL applications. The high-voltage,
monolithic device provides a path for DC wetting
(sealing) current in customer premises equipment
(CPE) to eliminate phone line corrosion on DSL
twisted-pair copper lines without telephone voice
services (i.e. only broadband services).
Internally, a bridge rectifier provides a
polarity-insensitive DC termination for DSL loop
sealing current. The IC includes an electronic inductor,
break-over and latch circuits, current limit and excess
power protection. A sealing current detect output
provides the means to monitor the loop for the
presence of sealing current in the loop.
The CPC1466 is manufactured in Clare’s high voltage
BCDMOS process that is used extensively in
telephony applications worldwide.
Ordering Information
PR+
NC
NC
TIP
RING
NC
NC
PR-
TC
NC
NC
RS
PD
NC
NC
COM
Current Limit
and Excess
Power Protection
Electronic
Inductor,
Breakover,
Latch, and
Opto Driver
Bridge
Rectifier
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Part Number Description
CPC1466D DC Termination IC, 16-pin SOIC in tubes,
47/tube
CPC1466DTR DC Termination IC, 16-pin SOIC tape and reel,
1000/reel
CPC1466M DC Termination IC, 16-pin MLP in tubes,
52/tube
CPC1466MTR DC Termination IC, 16-pin MLP tape and reel,
1000/reel
CPC1466
2 www.clare.com R00B
PRELIMINARY
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.1 DC Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.2 AC Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.3 Transition Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Sealing Current Monitor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5.1 LED Trigger Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Surge Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.1 Activation - On-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.2 Deactivation - Off-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Photo-Diode (PD) Output Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 On-State Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6.1 Typical Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6.2 Over-Voltage Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 MLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Printed Circuit Board Layout Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 MLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.2 MLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
R00B www.clare.com 3
PRELIMINARY
1. Specifications
1.1 Package Pinout 1.2 Pin Description
1.3 Absolute Maximum Ratings
Electrical absolute maximum ratings are at 25°C.
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
PR+
NC
NC
TIP
RING
NC
NC
PR-
TC
NC
NC
RS
PD
NC
NC
COM
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin Name Description
1 PR+ Protection resistor positive side
2 NC No connection
3 TIP Tip Lead
4 NC No connection
5 NC No connection
6 RING Ring lead
7 NC No connection
8 PR- Protection resistor negative side
9 COM Common
10 NC No connection
11 PD Photo-diode (LED input current)
12 NC No connection
13 RS Current limiting resistor
14 NC No connection
15 NC No connection
16 TC Timing capacitor
Parameter Minimum Maximum Unit
Maximum Voltage
(T to R, R to T)* - 300 V
Power dissipation - 1 W
Operating temperature -40 +85 °C
Operating relative humidity 5 95 %
Storage temperature -40 +125 °C
CPC1466
4 www.clare.com R00B
PRELIMINARY
1.4 Electrical Characteristics
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing
requirements. Typical values are characteristic of the
device and are the result of engineering evaluations.
In addition, typical values are provided for
informational purposes only and are not part of the
testing requirements.
All electrical specifications are provided for TA=25°C
1.4.1 DC Characteristics, Normal Operation
For operational templates: (see Figure 2 on page 5) and (see Figure 3 on page 5).
1.4.2 AC Characteristics, Normal Operation
For test conditions: (see Figure 4 on page 6).
1.4.3 Transition Characteristics, Normal Operation
For activation/deactivation test conditions: (see Figure 5 on page 7).
Parameter Conditions Symbol Minimum Typical Maximum Unit
Activate/Non-activate Voltage Off State VAN 30.0 35.0 39.0 V
Breakover current - IBO -0.51mA
DC Voltage drop Active State, 1 mA ≤ ISL ≤ 20 mA VON -12.515 V
DC leakage current VOFF = 20 V ILKG -1.55µA
Hold/Release current Active State IH/R 0.1 0.5 1.0 mA
Minimum on current VON < 54 V IMIN1 20 38 - mA
54 V ≤ VON ≤ 100 V for 2 seconds,
source resistance 200 Ω to 4 kΩIMIN2 9.0 45 - mA
VON > 100 V IMIN3 00.1-mA
Maximum on current VON ≤ 70 V IMAX1 -38.470mA
VON > 70 V IMAX2 -- mA
Photodiode drive current Active State IPD 0.2 0.3 10 mA
Parameter Conditions Symbol Minimum Typical Maximum Unit
AC impedance 200 Hz to 50 kHz ZMT 10 38 -kΩ
Linearity distortion ƒ = 200 Hz to 40 kHz, ISL = 1 mA to
20 mA, VAPP ≤ 12 VPP
D4070 - dB
Parameter Conditions Symbol Minimum Typical Maximum Unit
Activate time (see Figure 6 on page 7) t1 3.0 13 50 ms
Deactivate time (see Figure 7 on page 7) t2 3.0 - 100 ms
VON
1kΩ
-----------
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PRELIMINARY
Figure 2. I-V Requirements Template, 0 V to 50 V
Figure 3. I-V Requirements Template, 0 V to 250 V
1A
100 mA
10 mA
1 mA
100 A
10 A
1A
0
µ
µ
µ
Current
Absolute Voltage (V)
01020304050
Transition
Region
Transition
Region
On State
Off State
I
MAX1
I
MIN1
V
ON
I
HR
I
BO
I
LKG
V
AN
1A
100 mA
10 mA
1 mA
100 A
10 A
1A
0
µ
µ
µ
Current
Absolute Voltage (V)
0 50 100 150 200 250
I
MAX1
I
MIN2
I
MIN1
IMAX2
70 V, 70 mA
54 V, 9 mA
100 V, 0 mA
CPC1466
6 www.clare.com R00B
PRELIMINARY
Figure 4. Test Circuit for ac Impedance and Linearity
68 Fµ
1k Ω
DUT
VAPP
ac generator
ISL
1 - 20 mA
dc current source
Vmt
Vsig
Zmt
1000 Vmt
×
Vsig
----------------------------=
Linearity 20 Vmt
Vsig2ndHarmonic
----------------------------------------
log 20 1000
67.5
------------
log+=
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PRELIMINARY
Figure 5. Test Circuit for Activate and Deactivate Times
Figure 6. Applied Waveform for Activation Test
Figure 7. Applied Waveform for Deactivation Test
1Fµ
85 Ω
DUT
Pulse
generator
85 mH
40 V
30 V
20 V
10 V
0
43.5 V
Source Impedance
200 to 4kΩΩ
t1
500 ms
Measure
2.0 mA
1.5 mA
1.0 mA
0.5 mA
0
Current source limited to 30 V
t2
500 ms
Measure
CPC1466
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PRELIMINARY
1.5 Sealing Current Monitor Characteristics
1.5.1 LED Trigger Characteristics
For test conditions: (see Figure 8 on page 8).
Figure 8. Test Circuit for LED Operation
Parameter Conditions Symbol Minimum Typical Maximum Unit
Applied dc battery Voltage - - -43.5 - -56 VDC
Frequency (pulses per second) - - 4 - 8 -
Percent break - - 40 - 60 %
Number of pulses - - 6 - 10 -
Total Loop Resistance - - 200 - 4000 Ω
Required opto-coupler response
Number of applied pulses per make/break - - - 1 - -
Pulse width (opto on) (see Figure 8 on page 8) TON 10 - - ms
Pulse width (opto off) (see Figure 8 on page 8) TOFF 10 - - ms
CPC1466
VOUT
TIP
RING
2.2k
5%
Ω
4W
PR+
NC
NC
TIP
RING
NC
NC
PR-
TC
NC
NC
RS
PD
NC
NC
COM
1Fµ
68.1
1%
Ω
1/4 W
85Ω
25Ω
25Ω
+
R
200 - 4k
900 - 4.5k (MLT)
LOOP
ΩΩ
ΩΩ
V
-43.5V to -56V
BAT
85mH
Series rotary dial
Shunt rotary dial
1
2
3
6
5
4
75kΩ
V
5V
CC
1Fµ
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R00B www.clare.com 9
PRELIMINARY
Figure 9. Typical ADSL/VDSL Application Diagram
Digital
Control
Circuitry
Transceiver
TIP
RING
2.2k
5%
4W
DC
Blocking
Capacitor
1Fµ
68
1%
1/4W
1
2
3
6
5
4
75k
V
CC
CPC1466
PR+
NC
NC
TIP
RING
NC
NC
PR-
TC
NC
NC
RS
PD
NC
NC
COM
Current Limit
and Excess
Power Protection
Electronic
Inductor,
Breakover,
Latch, and
Opto Driver
Bridge
Rectifier
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CPC1225N
Solid State
Relay
SSR
30 - 35mH
with Loop Current
L1
L2
C1
SP1
CPC1466
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PRELIMINARY
2. Functional Description
2.1 Introduction
The CPC1466 can be used for a number of DSL
designs requiring a dc hold circuit such as ADSL
modem applications. Typical ADSL applications will
use a filter circuit design similar to the one shown in
Figure 9‚ “Typical ADSL/VDSL Application Diagram”
on page 9.
The DC Termination IC performs two fundamental
functions in an ADSL modem application; as an
electronic inductor providing a low impedance dc
termination with a high impedance ac termination and
second as part of the sealing current detection system
for automated line sensing. This function provides an
excellent method to monitor for the presence of
sealing current. Generally, loss of sealing current
indicates loop loss.
As can be seen in the application circuit in Figure 9 on
page 9, CPC1466 designs require few external
components. For the CPC1466, all that is needed is a
circuit protector, two resistors and a capacitor. To
ensure DSL signal integrity over a wide variety of
conditions a POTS splitter type filter is recommended
to isolate the DSL traffic from the termination.
2.2 Surge Protection
Although the CPC1466 self protects via current
limiting, it requires over-voltage surge protection to
protect against destructive over-voltage transients.
Clare recommends the use of a crowbar-type surge
protector to limit the surge voltage seen by the
CPC1466 to less than 250 V. The protection device
must be able to withstand the surge requirements
specified by the appropriate governing agency in
regions where the product will be deployed. Teccor,
Inc. and Bourns, Inc. make suitable surge protectors
for most applications. Devices such as Teccor’s
P1800SD or P2000SD Sidactors and Bourns’
TISP4220H3BJ or TISP4240H3BJ thyristors should
provide suitable protection.
2.3 Bridge Rectifier
The bridge rectifier in the CPC1466 ensures that the
device is polarity insensitive and provides consistent
operational characteristics if the tip to ring polarity is
reversed.
2.4 State Transitions
The dc tip to ring voltage-current characteristics of the
CPC1466 are shown in Figure 2‚ “I-V Requirements
Template, 0 V to 50 V”, and in Figure 3‚ “I-V
Requirements Template, 0 V to 250 V” on page 5.
Transition timings are illustrated in Figure 6‚ “Applied
Waveform for Activation Test”, and in Figure 7‚
“Applied Waveform for Deactivation Test”. The test
configuration for these timings is given in Figure 5‚
“Test Circuit for Activate and Deactivate Times”. All
timing figures are located on page 7.
State transition timings are set by the 1 µF capacitor
connected between the TC and COM pins.
2.4.1 Activation - On-State
Application of battery voltage to the loop causes the
CPC1466 to conduct whenever the voltage exceeds
approximately 35 V. With application of sufficient
voltage applied across the tip and ring terminals, the
CPC1466 will initially conduct a nominal 150 µA of
sealing current for approximately 20 ms prior to
activation. Once activated, the CPC1466 will remain in
the on state for as long as the loop current exceeds a
nominal 0.5 mA.
The CPC1466 turn-on timing circuit assures device
activation will occur within 50 ms of an applied voltage
greater than 43.5 V but not within the first 3 ms.
2.4.2 Deactivation - Off-State
While the CPC1466 activation protocol is based on an
initial minimum voltage level, deactivation is based on
a diminished sealing current level. Deactivation occurs
when the nominal sealing current level drops below
0.5 mA with guaranteed deactivation occurring for
sealing current levels less than 0.1 mA
The turn-off timing circuit deactivates the sealing
current hold circuit when 1 mA of sealing current has
been removed for 100 ms but ignores periods of loss
up to 3 ms.
2.5 Photo-Diode (PD) Output Behavior
Output from the PD pin provides a minimum of 0.2 mA
of photodiode drive current for an optocoupler’s LED
anytime sealing current exceeds 1 mA.
Because LED current is interrupted whenever loop
current is interrupted, the optocoupler provides an
R00B www.clare.com 11
PRELIMINARY
excellent means of indicating loop availability for
designs with a full time sealing current requirement. In
addition, for pulsed sealing current loops, the status
from this detector when used in conjuntion with the
timing of modem retraining events can be used as an
indicator to determine if the sealing current event is
clearing line impairments.
2.6 On-State Behavior
2.6.1 Typical Conditions
On-state sealing current levels are determined by the
network’s power feed circuit and the loop’s dc
impedance. To compensate for low loop resistance or
very high loop voltage, the CPC1466 limits the
maximum sealing current to 70 mA.
The CPC1466 manages package power dissipation
by shunting excess sealing current through the 2.2 kΩ
4W power resistor located between the PR+ and PR-
pins.
2.6.2 Over-Voltage Conditions
Potentials in excess of 100 V applied to the tip and
ring interface will cause the CPC1466 to disable the
sealing current hold circuit and enter a standby state
with very little current draw. Once the over-voltage
condition is removed, the CPC1466 automatically
resumes normal operation.
CPC1466
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PRELIMINARY
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 SOIC
NOTES:
1. Coplanarity = 0.004 (0.1016) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
3. Sum of package height, standoff, and coplanarity does not exceed 0.083 (2.108).
inches
(mm)
DIMENSIONS
0.083 MAX
(2.108 MAX.)
SEE NOTE 3
0.350 TYP
(8.890 TYP.)
0.016 TYP
(0.406 TYP.)
LEAD TO PACKAGE STANDOFF:
MIN: 0.001 (0.0254)
MAX: 0.004 (0.102)
0.400±0.015
(10.160±0.381)
0.295±0.005
(7.493±0.127)
0.408±0.005
(10.363±0.127)
0.050 TYP
(1.270 TYP)
0.025 X 45˚
(0.635 X 45˚)
0.010 ±0.0005
(0.254 ±0.0127)
0.040 TYP
(1.016 TYP)
0.020±0.004
(0.508±0.1016)
PIN 1
PIN 16
R00B www.clare.com 13
PRELIMINARY
3.1.2 MLP
EXPOSED
METALLIC PAD
7.00 ± 0.25
(0.276 ± 0.01)
6.00 ± 0.25
(0.236 ± 0.01)
INDEX AREA TOP VIEW
SEATING
PLANE
SIDE VIEW
0.90 ± 0.10
(0.035 ± 0.004)
0.33, + 0.07, - 0.05
(0.013, + 0.003, - 0.002)
0.02, + 0.03, - 0.02
(0.0008, + 0.0012, - 0.0008)
0.20
(0.008)
1.80
(0.071)
0.40
(0.016)
4.00 ± 0.05
(0.157 ± 0.002)
0.55 ± 0.10
(0.022 ± 0.004)
6.00 ± 0.05
(0.236 ± 0.002)
BOTTOM VIEW Dimensions
mm
(inch)
Terminal Tip
0.80
(0.032)
16
1
0.55 ± 0.10
(0.022 ± 0.004)
0.55 ± 0.10
(0.022 ± 0.004)
0.23
(0.009)
CPC1466
14 www.clare.com R00B
PRELIMINARY
3.2 Printed Circuit Board Layout Pattern
3.2.1 SOIC 3.2.2 MLP
NOTE: As the metallic pad on the bottom of the MLP
package is connected to the substrate of the die, Clare
recommends that no printed circuit board traces or
vias be placed under this area.
3.3 Tape and Reel Packaging
3.3.1 SOIC
1.90
(0.075)
1.27
(0.050)
mm
(inches)
DIMENSIONS
9.30
(0.366)
0.60
(0.024)
DIMENSIONS
mm
(inches)
5.70
(0.224)
0.40
(0.016)
1.15
(0.045)
0.80
(0.031)
1.15
(0.045)
0.65
(0.026)
0.40
(0.016)
0.43
(0.017)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Tape and Reel Packaging for 16-Pin SOIC Package
Dimensions
mm
(inches)
Embossment
Embossed
Carrier
330.2 Dia
(13.00 Dia)
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
User Direction of Feed
Top Cover
Tape
P=12.00
(0.47) A0=10.90 + 0.15
(0.429 + 0.010)
B0=10.70 + 0.15
(0.421 + 0.01)
W=16.00 + 0.30
(0.630 + 0.010)
K0=3.20 + 0.15
(0.193 + 0.01)
K1=2.70 + 0.15
(0.106 + 0.01)
R00B www.clare.com 15
PRELIMINARY
3.3.2 MLP
3.4 Soldering
3.4.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity
for this product using IPC/JEDEC standard
J-STD-020. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-033 per
the labeled moisture sensitivity level (MSL), level 1 for
the SOIC package, and level 3 for the MLP package.
3.4.2 Reflow Profile
For proper assembly, this component must be
processed in accordance with the current revision of
IPC/JEDEC standard J-STD-020. Failure to follow the
recommended guidelines may cause permanent
damage to the device resulting in impaired
performance and/or a reduced lifetime expectancy.
3.5 Washing
Clare does not recommend ultrasonic cleaning of this
part.
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Tape and Reel Packaging for 6mm x 7mm 16-Pin MLP Package
Dimensions
mm
(inches)
Embossment
Embossed
Carrier
330.2 Dia
(13.00 Dia)
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
K
0
=1.61 + 0.10
(0.063 + 0.004)
B
0
=7.24 + 0.10
(0.285 + 0.004)
W=16.00 + 0.30
(0.630 + 0.012)
P=12.00 + 0.10
(0.472 + 0.004) A
0
=6.24 + 0.10
(0.246 + 0.004)
Pin 1
F
or additional information please visit www.clare.com
C
lare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
c
hanges to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
f
orth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
p
roducts, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
T
he products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
t
he body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
p
erson or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specifications: DS-CPC1466 - R00B
© Copyright 2007, Clare, Inc.
All rights reserved. Printed in USA.
6/29/2007
