SLIS032A - JULY 1995 - REVISED MAY 2005 D Low rDS(on) . . . 5 Typical D Avalanche Energy . . . 30 mJ D Eight Power DMOS-Transistor Outputs of D D D D DW OR N PACKAGE (TOP VIEW) NC VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G GND 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Devices Are Cascadable Low Power Consumption description The TPIC6B595 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregister clear (SRCLR) is high. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOStransistor outputs have sink-current capability. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 NC GND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK GND NC - No internal connection logic symbol G RCK SRCLR SRCK SER IN 9 EN3 12 8 C2 R 13 3 SRG8 C1 1D 2 4 5 6 7 14 15 16 17 2 18 DRAIN0 DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 SER OUT This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sinkcurrent capability. Each output provides a 500-mA typical current limit at TC = 25C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B595 is characterized for operation over the operating case temperature range of -40C to 125C. Copyright 1995 - 2005, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLIS032A - JULY 1995 - REVISED MAY 2005 logic diagram (positive logic) G RCK SRCLR 9 12 4 D SRCK 13 D C2 C1 CLR SER IN 5 3 D DRAIN1 D C2 C1 CLR 6 D DRAIN2 D C2 C1 7 CLR D DRAIN3 D C2 C1 CLR 14 DRAIN4 D C2 D C1 CLR 15 D DRAIN5 D C2 C1 16 CLR D DRAIN6 D C2 C1 17 CLR D DRAIN7 D C2 C1 CLR 10, 11, 19 18 2 DRAIN0 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SER OUT GND SLIS032A - JULY 1995 - REVISED MAY 2005 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 50 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted) Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed drain current, each output, all outputs on, ID, TC = 25C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA Continuous drain current, each output, all outputs on, ID, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Peak drain current single output, IDM,TC = 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration 100 s and duty cycle 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25C, L = 200 mH, IAS = 0.5 A (see Figure 4). DISSIPATION RATING TABLE PACKAGE TC 25C POWER RATING DW N DERATING FACTOR ABOVE TC = 25C TC = 125C POWER RATING 1389 mW 11.1 mW/C 278 mW 1050 mW 10.5 mW/C 263 mW POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLIS032A - JULY 1995 - REVISED MAY 2005 recommended operating conditions Logic supply voltage, VCC High-level input voltage, VIH MIN MAX UNIT 4.5 5.5 V 0.85 VCC Low-level input voltage, VIL Pulsed drain output current, TC = 25C, VCC = 5 V (see Notes 3 and 5) V 0.15 VCC V 500 mA -500 Setup time, SER IN high before SRCK, tsu (see Figure 2) 20 ns Hold time, SER IN high after SRCK, th (see Figure 2) 20 ns Pulse duration, tw (see Figure 2) 40 Operating case temperature, TC -40 ns C 125 electrical characteristics, VCC = 5 V, TC = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA VSD Source-to-drain diode forward voltage IF = 100 mA VOH High-level output voltage, SER OUT VOL Low-level output voltage, SER OUT IIH IIL MAX IOH = - 20 A, VCC = 4.5 V IOH = - 4 mA, VCC = 4.5 V IOL = 20 A, VCC = 4.5 V High-level input current IOL = 4 mA, VCC = 5.5 V, VCC = 4.5 V VI = VCC Low-level input current VCC = 5.5 V, VI = 0 4.49 4 4.2 0.005 0.1 0.3 0.5 A -1 A 150 300 0.4 5 Logic supply current at frequency fSRCK = 5 MHz,CL = 30 pF, All outputs off, See Figures 2 and 6 IN Nominal current IDSX Off-state drain current rDS(on) Static drain-source on-state resistance See Notes 5, 6, and 7 VDS = 40 V, ID = 100 mA, VCC = 5.5 V, TC = 125C VCC = 4.5 V ID = 100 mA, VCC = 4.5 V ID = 350 mA, TC = 125C, See Notes 5 and 6 and Figures 7 and 8 V 1 100 ICC(FRQ) V V 20 All outputs on VDS(on) = 0.5 V, IN = ID, TC = 85C VDS = 40 V, VCC = 5.5 V 4.4 1 All outputs off VCC = 5.5 V UNIT V 0.85 Logic supply current 4 TYP 50 ICC NOTES: 3. 5. 6. 7. MIN 90 A A mA mA 0.1 5 0.15 8 4.2 5.7 6.8 9.5 A A VCC = 4.5 V 5.5 8 Pulse duration 100 s and duty cycle 2%. Technique should limit TJ - TC to 10C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLIS032A - JULY 1995 - REVISED MAY 2005 switching characteristics, VCC = 5 V, TC = 25C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output from G tr tf Rise time, drain output ta trr Reverse-recovery-current rise time Propagation delay time, high-to-low-level output from G MIN TYP CL = 30 pF, ID = 100 mA, See Figures 1, 2, and 9 Fall time, drain output UNIT 150 ns 90 ns 200 ns 200 ns 100 IF = 100 mA, di/dt = 20 A/s, See Notes 5 and 6 and Figure 3 Reverse-recovery time MAX ns 300 NOTES: 5. Technique should limit TJ - TC to 10C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. thermal resistance PARAMETER RJA TEST CONDITIONS DW package Thermal resistance, junction-to-ambient MIN 90 All 8 outputs with equal power N package MAX 95 UNIT C/W PARAMETER MEASUREMENT INFORMATION 5V 24 V 7 2 8 13 Word Generator (see Note A) 3 12 9 SRCLR SRCK 5 4 3 2 1 0 DRAIN 4 -7, 14 -17 Output G 0V 5V SER IN CL = 30 pF (see Note B) RCK 5V G RL = 235 DUT 5V 0V ID VCC SER IN 6 SRCK 0V 5V RCK 0V 5V SRCLR 0V GND 10, 11, 19 24 V DRAIN1 0.5 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 1. Resistive-Load Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLIS032A - JULY 1995 - REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION 5V G 5V 50% 50% 0V 24 V tPLH tPHL 2 8 13 Word Generator (see Note A) 3 12 9 V SRCLR CC SRCK Output ID RL = 235 4 -7, 14 -17 DUT 24 V 90% 10% 10% tr Output 0.5 V tf SWITCHING TIMES DRAIN SER IN CL = 30 pF (see Note B) RCK G 90% GND 5V 50% SRCK 0V tsu 10, 11, 19 th 5V TEST CIRCUIT SER IN 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 2. Test Circuit, Switching Times, and Voltage Waveforms TP K DRAIN Circuit Under Test 0.1 A 2500 F 250 V di/dt = 20 A/s + L = 1 mH IF (see Note A) 25 V IF - TP A 0 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note B) ta 50 trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The VGG amplitude and RG are adjusted for di/dt = 20 A/s. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 s, t2 = 7 s, and t3 = 3 s. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLIS032A - JULY 1995 - REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION 5V 15 V tw 2 8 V SRCLR CC 10.5 3 Word Generator (see Note A) 12 9 DUT 4 -7, 14 -17 DRAIN RCK See Note B 0V IAS = 0.5 A 200 mH SER IN G 5V Input ID 13 SRCK tav ID VDS GND V(BR)DSX = 50 V MIN VDS 10, 11, 19 VOLTAGE AND CURRENT WAVEFORMS SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A. Energy test level is defined as EAS = IAS x V(BR)DSX x tav/2 = 30 mJ. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 10 2.5 VCC = 5 V TC = - 40C to 125C 4 I CC - Supply Current - mA IAS - Peak Avalanche Current - A TC = 25C 2 1 0.4 2 1.5 1 0.5 0.2 0.1 0.1 0.2 0.4 1 2 4 10 0 0.1 1 10 100 f - Frequency - MHz tav - Time Duration of Avalanche - ms Figure 6 Figure 5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLIS032A - JULY 1995 - REVISED MAY 2005 TYPICAL CHARACTERISTICS 18 VCC = 5 V See Note A 16 14 TC = 125C 12 10 8 6 TC = 25C 4 TC = - 40C 2 0 0 100 200 300 400 500 ID - Drain Current - mA 600 700 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) - Static Drain-to-Source On-State Resistance - r DS(on) - Drain-to-Source On-State Resistance - DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 8 ID = 100 mA See Note A 7 TC = 125C 6 5 TC = 25C 4 3 TC = - 40C 2 1 0 4 6 6.5 4.5 5 5.5 VCC - Logic Supply Voltage - V Figure 7 Figure 8 SWITCHING TIME vs CASE TEMPERATURE 300 ID = 100 mA See Note A tf Switching Time - ns 250 tr 200 tPLH 150 tPHL 100 50 -50 -25 0 25 50 75 100 TC - Case Temperature - C Figure 9 NOTE C: Technique should limit TJ - TC to 10C maximum. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 125 7 SLIS032A - JULY 1995 - REVISED MAY 2005 THERMAL INFORMATION MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY I D - Maximum Continuous Drain Current of Each Output - A 0.45 VCC = 5 V 0.4 0.35 0.3 0.25 TC = 25C 0.2 0.15 TC = 100C 0.1 TC = 125C 0.05 0 1 2 3 4 5 6 7 8 I D - Maximum Peak Drain Current of Each Output - A MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.5 d = 10% 0.45 d = 20% 0.4 0.35 d = 50% 0.3 0.25 d = 80% 0.2 0.15 VCC = 5 V TC = 25C d = tw/tperiod = 1 ms/tperiod 0.1 0.05 N - Number of Outputs Conducting Simultaneously 0 1 2 3 4 5 6 7 8 N - Number of Outputs Conducting Simultaneously Figure 10 Figure 11 Revision History DATE REV PAGE 5/18/05 A 5 7/1995 * SECTION Figure 1 DESCRIPTION Changed SRCLR timing diagram Original reversion NOTE: Page numbers for previous revisions may differ from page numbers in the current version. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 15-Jun-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPIC6B595DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595N ACTIVE PDIP N 20 20 Pb-Free (RoHS) (3) Samples (Requires Login) CU NIPDAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6B595DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.1 2.65 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6B595DWR SOIC DW 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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