ZL40205 Precision 1:6 LVPECL Fanout Buffer with On-Chip Input Termination Data Sheet February 2013 Features Ordering Information ZL40205LDG1 ZL40205LDF1 Inputs/Outputs 32 Pin QFN 32 Pin QFN Trays Tape and Reel Matte Tin Package Size: 5 x 5 mm -40oC to +85oC * Accepts differential or single-ended input * LVPECL, LVDS, CML, HCSL, LVCMOS * On-chip input termination resistors and biasing for AC coupled inputs Applications * Six precision LVPECL outputs * General purpose clock distribution * Operating frequency up to 750 MHz * Low jitter clock trees * Logic translation Power * Clock and data signal restoration * Options for 2.5 V or 3.3 V power supply * * Core current consumption of 110 mA Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC * On-chip Low Drop Out (LDO) Regulator for superior power supply rejection * Wireless communications * High performance microprocessor clock distribution Performance * Ultra low additive jitter of 36 fs RMS out0_p out0_n out1_p out1_n ctrl vt Termination and Bias Buffer out2_p out2_n out3_p out3_n clk_p clk_n out4_p out4_n out5_p out5_n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2012, Microsemi Corporation. All Rights Reserved. ZL40205 Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 Microsemi Corporation ZL40205 Data Sheet List of Figures Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Simplified Diagram of input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11 - Clock Input - DC-coupled 3.3V CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12 - Simplified Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 13 - LVPECL Basic Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14 - LVPECL Parallel Output Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 16 - LVPECL AC Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17 - LVPECL AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 18 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 20 - Differential and Single-Ended Output Voltages Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 21 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Microsemi Corporation ZL40205 Data Sheet Change Summary Below are the changes from the November 2012 issue to the February 2013 issue: Page 7 Item Change Figure 4 Changed text to indicate the circuit is not recommended for VDD_driver=2.5V. 4 Microsemi Corporation ZL40205 1.0 Data Sheet Package Description 24 22 20 out3_n 18 out1_n out1_p out3_p vdd gnd gnd vdd out2_n out2_p The device is packaged in a 32 pin QFN 16 out4_n 26 out0_n 14 28 NC 12 gnd (E-pad) NC 10 32 NC vdd VDD_core 8 gnd clk_n 6 ctrl 4 clk_p gnd 2 VDD_core vdd NC NC 30 vt NC out5_p out5_n vt out0_p out4_p Figure 2 - Pin Connections 5 Microsemi Corporation ZL40205 2.0 Data Sheet Pin Description Pin # Name 3, 6 clk_p, clk_n, 28, 27, 26, 25, 24, 23, 18, 17, 16, 15, 14, 13 Description Differential Input (Analog Input). Differential (or single ended) input signals. For all input configurations see "Clock Inputs" on page 6 out0_p, out0_n Differential Output (Analog Output). Differential outputs. out1_p, out1_n out2_p, out2_n out3_p, out3_n out4_p, out4_n out5_p, out5_n 9, 19, 22, 32 vdd Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal. 1, 8 vdd_core Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal. 2, 7, 20, 21 gnd 4 vt On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm termination resistors. The use of this pin is detailed in section 3.1, "Clock Inputs", for various input signal types. 5 ctrl Digital Control for On-Chip Input Termination (Input). Selects differential input mode; 0: DC coupled LVPECL or LVDS modes 1: AC coupled differential modes This pin are internally pulled down to GND. The use of this pin is detailed in section 3.1, "Clock Inputs", for various input signal types. 10, 11, 12, 29, 30, 31 NC No Connection. Leave unconnected. Ground. 0 V. 6 Microsemi Corporation ZL40205 3.0 Data Sheet Functional Description The ZL40205 is an LVPECL clock fan out buffer with six output clock drivers capable of operating at frequencies up to 750MHz. The ZL40205 provides an internal input termination network for DC and AC coupled inputs; optional input biasing for AC coupled inputs is also provided. The ZL40205 can accept DC or AC coupled LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external termination is also available. The ZL40205 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40C to +85C. The device block diagram is shown in Figure 1; its operation is described in the following sections. 3.1 Clock Inputs The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate. A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in Figure 3. clk_p 50 Receiver 50 clk_n Vt Bias ctrl Figure 3 - Simplified Diagram of Input Stage This following figures give the components values and configuration for the various circuits compatible with the input stage and the use of the Vt and ctrl pins in each case. In the following diagrams were the ctrl pin is logically one and the Vt pin is not connected, the Vt pin can be instead connected to VDD with a capacitor. A capacitor can also help in Figure 4 between Vt and VDD. This capacitor will minimize the noise at the point between the two internal termination resistors and improve the overall performance of the device. 6 Microsemi Corporation ZL40205 Data Sheet VDD_driver VDD 22 Ohms Zo = 50 Ohms clk_p LVPECL Driver clk_n Zo = 50 Ohms Vt 22 Ohms R "0" Ctrl For 3.3 V: R= 50 Ohms For V: R= 22 Ohms Not2.5 recommended for VDD_driver=2.5V Figure 4 - Clock Input - LVPECL - DC Coupled VDD_driver VDD 22 Ohms Z o = 50 Ohms clk_p LVPECL Driver clk_n 22 Ohms Z o = 50 Ohms R NC "1" R For 3.3 V: R= 150 Ohms For 2.5 V: R= 85 Ohms Figure 5 - Clock Input - LVPECL - AC Coupled 7 Microsemi Corporation Vt Ctrl ZL40205 Data Sheet VDD_driver VDD Zo = 50 Ohms clk_p LVDS Driver clk_n Zo = 50 Ohms NC "0" Vt Ctrl Figure 6 - Clock Input - LVDS - DC Coupled VDD_driver VDD Note: R is only needed to provide a DC path for the LVDS driver. See driver data sheet for more information. Zo = 50 Ohms clk_p LVDS Driver R clk_n Zo = 50 Ohms NC "1" For VDD_driver = 3.3 V: R= 900 Ohms For VDD_driver = 2.5 V: R = 680 Ohms Figure 7 - Clock Input - LVDS - AC Coupled 8 Microsemi Corporation Vt Ctrl ZL40205 Data Sheet VDD_driver R VDD R Zo = 50 Ohms clk_p CML Driver clk_n Zo = 50 Ohms NC "1" Vt Ctrl R= 50 Ohms Figure 8 - Clock Input - CML- AC Coupled VDD_driver VDD Zo = 50 Ohms clk_p HCSL Driver clk_n Zo = 50 Ohms R NC R "1" R= 50 Ohms Figure 9 - Clock Input - HCSL- AC Coupled 9 Microsemi Corporation Vt Ctrl ZL40205 Data Sheet VDD_driver VDD CMOS Driver Zo = 50 Ohms clk_p clk_n Vt "1" Ctrl Figure 10 - Clock Input - AC-coupled Single-Ended VDD_driver VDD CMOS Driver Zo = 50 Ohms clk_p clk_n NC "1" Vt Ctrl Figure 11 - Clock Input - DC-coupled 3.3V CMOS 10 Microsemi Corporation ZL40205 3.2 Data Sheet Clock Outputs LVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since there is a different device with the same inputs and LVDS outputs. out_p out_n Figure 12 - Simplified Output Driver The methods to terminate the ZL40205 LVPECL drivers are shown in the following figures. VDD VDD ZL40205 clk_p Z o = 50 Ohm s clk_n Z o = 50 Ohm s LVPECL Receiver 50 Ohm s 50 Ohm s VDD - 2 Figure 13 - LVPECL Basic Output Termination 11 Microsemi Corporation ZL40205 Data Sheet VDD_Rx VDD ZL40205 clk_p Z o = 50 Ohm s clk_n Z o = 50 Ohm s LVPECL Receiver 50 Ohm s For VDD = 2.5 V: R = 20 Ohm s For VDD = 3.3 V: R = 50 Ohm s 50 Ohm s R Figure 14 - LVPECL Parallel Output Termination VDD_Rx VDD R1 ZL40205 clk_p Z o = 50 Ohm s clk_n Z o = 50 Ohm s VDD_Rx R1 LVPECL Receiver R2 R2 For VDD = 2.5 V: R1 = 250 Ohm s, R2 = 62.5 Ohm s For VDD = 3.3 V: R1 = 127 Ohm s, R2 = 82 Ohm s Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination 12 Microsemi Corporation ZL40205 VDD Data Sheet VDD_Rx For VDD = 2.5 V: R = 60 Ohms For VDD = 3.3 V: R = 120 Ohms R1 ZL40205 clk_p Zo = 50 Ohms clk_n Zo = 50 Ohms VDD_Rx R1 100 nF R LVPECL Receiver 100 nF R2 R R2 For VDD_Rx = 2.5 V: R1 = 250 Ohms, R2 = 62.5 Ohms For VDD_Rx = 3.3 V: R1 = 127 Ohms, R2 = 82 Ohms Figure 16 - LVPECL AC Output Termination VDD VDD_Rx For VDD = 2.5 V: R = 60 Ohm s For VDD = 3.3 V: R = 120 Ohm s 50 ZL40205 clk_p Z o = 50 Ohm s 100 nF clk_n Z o = 50 Ohm s R 50 CM L Receiver 100 nF R Figure 17 - LVPECL AC Output Termination for CML Inputs 13 Microsemi Corporation ZL40205 3.3 Data Sheet Device Additive Jitter The ZL40205 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40205 is random and as such it is not correlated to the jitter of the input clock signal. The square of the resultant random RMS jitter at the output of the ZL40205 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive random jitter due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 18. Jadd2 Jin2 Jin Jadd Jps Jout Jps2 + + = Random input clock jitter (RMS) = Additive jitter due to the device (RMS) = Additive jitter due to power supply noise (RMS) = Resultant random output clock jitter (RMS) Figure 18 - Additive Jitter 14 Microsemi Corporation Jout2= Jin2+Jadd2+Jps2 ZL40205 3.4 Data Sheet Power Supply This device operates employing either a 2.5V supply or 3.3V supply. 3.4.1 Sensitivity to power supply noise Power supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40205 is equipped with a low drop out (LDO) regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise. 3.4.2 Power supply filtering Jitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure 19. * * * * 10 F capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating 0.1 F capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating Capacitors should be placed next to the connected device power pins a 0.3 ohm resistor is recommended Figure 19 - Decoupling Connections for Power Pins vdd_core 0.1 F 0.1 F 1 8 0.15 vdd 10 F 0.1 F 0.1 F 10 F 3.4.3 9 ZL40205 19 22 32 PCB layout considerations The power nets in Figure 19 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device. 15 Microsemi Corporation ZL40205 4.0 Data Sheet AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter Sym. Min. Max. Units VDD_R -0.5 4.6 V VPIN -0.5 VDD V 1 Supply voltage 2 Voltage on any digital pin 4 LVPECL output current Iout 30 mA 5 Soldering temperature T 260 C 6 Storage temperature TST 125 C 7 Junction temperature Tj 125 C 8 Voltage on input pin Vinput VDD V 9 Input capacitance each pin Cp 500 fF -55 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated Recommended Operating Conditions* Characteristics Sym. Min. Typ. Max. Units 1 Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V 2 Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V 3 Operating temperature TA -40 25 85 C * Voltages are with respect to ground (GND) unless otherwise stated DC Electrical Characteristics - Current Consumption Characteristics Sym. Min. Typ. Max. Units Notes 1 Supply current LVPECL drivers unloaded Idd_unload 110 mA Unloaded 2 Supply current LVPECL drivers loaded (all outputs are active) Idd_load 209 mA Including power to RL = 50 Units Notes DC Electrical Characteristics - Inputs and Outputs - for 3.3 V Supply Characteristics Sym. Min. Typ. Max. 1 CMOS control logic high-level input voltage VCIH 0.7*VDD 2 CMOS control logic low-level input voltage VCIL 3 CMOS control logic Input leakage current IIL 4 Differential input common mode voltage VCM 1.1 2.0 V 5 Differential input voltage difference VID 0.25 1 V 6 Differential input resistance VIR 80 120 ohm V 0.3*VDD 1 16 Microsemi Corporation 100 V A VI = VDD or 0 V ZL40205 Data Sheet DC Electrical Characteristics - Inputs and Outputs - for 3.3 V Supply Characteristics Sym. Min. VDD 1.40 7 LVPECL output high voltage VOH 8 LVPECL output low voltage VOL 9 LVPECL output differential voltage* VOD Typ. Max. Units Notes V VDD 1.62 V 0.9 V Max. Units 0.5 * This parameter was measured from 125 MHz to 750 MHz. DC Electrical Characteristics - Inputs and Outputs - for 2.5 V Supply Characteristics Sym. Min. Typ. 1 Differential input common mode voltage VCM 1.1 1.6 V 2 Differential input voltage difference VID 0.25 1 V 3 Differential input resistance VIR 80 120 ohm 4 LVPECL output high voltage VOH VDD 1.40 5 LVPECL output low voltage VOL 6 LVPECL output differential voltage* VOD 100 Notes V VDD 1.62 V 0.9 V 0.4 * This parameter was measured from 125 MHz to 750 MHz. VOD 2*VOD Figure 20 - Differential and Single-Ended Output Voltages Parameter Definitions AC Electrical Characteristics* - Inputs and Outputs (see Figure 21) - for 2.5/3.3 V supply. Characteristics Sym. Min. Typ. Max. Units 750 MHz 1 2 ns 1 Maximum Operating Frequency 1/tp 2 Input to output clock propagation delay tpd 3 Output to output skew tout2out 50 100 ps 4 Part to part output skew tpart2part 80 300 ps 5 Output clock Duty Cycle degradation 2 Percent 6 LVPECL Output clock slew rate 0 tPWH/ tPWL -2 0 rSL 0.75 1.2 * Supply voltage and operating temperature are as per Recommended Operating Conditions 17 Microsemi Corporation V/ns Notes ZL40205 Data Sheet tP tPWL tPWH Input tpd Output Figure 21 - Input To Output Timing 18 Microsemi Corporation ZL40205 5.0 Data Sheet Performance Characterization Additive Jitter at 2.5 V* Output Frequency (MHz) Jitter Measurement Filter Typical RMS (fs) 1 125 12 kHz - 20 MHz 139 2 212.5 12 kHz - 20 MHz 109 3 311.04 12 kHz - 20 MHz 85 4 425 12 kHz - 20 MHz 57 5 500 12 kHz - 20 MHz 50 6 622.08 12 kHz - 20 MHz 40 7 750 12 kHz - 20 MHz 36 Notes *The values in this table were taken with an approximate slew rate of 0.8 V/ns. Additive Jitter at 3.3 V* Output Frequency (MHz) Jitter Measurement Filter Typical RMS (fs) 1 125 12 kHz - 20 MHz 115 2 212.5 12 kHz - 20 MHz 85 3 311.04 12 kHz - 20 MHz 72 4 425 12 kHz - 20 MHz 55 5 500 12 kHz - 20 MHz 48 6 622.08 12 kHz - 20 MHz 41 7 750 12 kHz - 20 MHz 39 Notes *The values in this table were taken with an approximate slew rate of 0.8 V/ns. Additive Jitter from a Power Supply Tone* Carrier frequency Parameter Typical Units 125MHz 25 mV at 100 kHz 115 fs RMS 750MHz 25 mV at 100 kHz 59 fs RMS Notes * The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for VDD = 2.5 V. The magnitude of the interfering tone is measured at the DUT. 19 Microsemi Corporation ZL40205 6.0 Data Sheet Typical Behavior 0.5 0.4 0.3 Voltage 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 Time (ns) Typical Phase Noise at 622.08 MHz Typical Waveformat 155.52 MHz 0.8 1 0.95 Propagation Delay (ns) Voltage 0.75 0.7 0.65 0.9 0.85 0.8 0.75 0.6 0 100 200 300 400 500 600 700 0.7 800 -60 Frequency (MHz) -40 -20 0 20 40 60 80 Temperature (C) VOD versus Frequency Propagation Delay versus Temperature Note: This is for a single device. For more details see the 20 Microsemi Corporation 100 ZL40205 Data Sheet 60 -75 55 Addivite Jitter (fs RMS) -80 PSRR (dBc) -85 -90 -95 -100 -105 50 45 40 35 30 25 20 15 10 100 150 200 250 300 350 400 450 100 500 200 250 300 350 400 450 500 Power Supply Noise Frequency (kHz) with 25 mV magnitude Power Supply Noise Frequency (kHz) with 25 mV magnitude Power Supply Tone Frequency (at 25 mV) versus PSRR at 125 MHz Power Supply Tone Frequency (at 25 mV) versus Additive Jitter at 125 MHz 300 -74 -76 250 Additive Jitter (fs RMS) -78 PSRR (dBc) 150 -80 -82 -84 -86 200 150 100 50 -88 -90 20 40 60 80 0 100 Power Supply Tone Magnitude at 100 kHz (mV) Power Supply Tone Magnitude (at 100 kHz) versus PSRR at 125 MHz 20 30 40 50 60 70 80 90 Power Supply Tone Magnitude at 100 kHz (mV) 100 Power Supply Tone Magnitude (at 100 kHz) versus Additive Jitter at 125 MHz 21 Microsemi Corporation ZL40205 7.0 Data Sheet Package Characteristics Thermal Data Parameter Symbol Test Condition Value Junction to Ambient Thermal Resistance JA Still Air 1 m/s 2 m/s 37.4 33.1 31.5 o Junction to Case Thermal Resistance JC 24.4 oC/W Junction to Board Thermal Resistance JB 19.5 oC/W Maximum Junction Temperature* Tjmax 125 oC Maximum Ambient Temperature TA 85 oC 22 Microsemi Corporation Unit C/W ZL40205 8.0 Mechanical Drawing 23 Microsemi Corporation Data Sheet For more information about all Microsemi productsvisit our Web Site at www.microsemi.com Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively "Microsemi") is believed to be reliable. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Microsemi's conditions of sale which are available on request. Purchase of Microsemi's I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Microsemi, ZL, and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Microsemi Corporation. TECHNICAL DOCUMENTATION - NOT FOR RESALE