UT54ACS109E Dual J-K Flip-Flops Septenber 2010 www.aeroflex.com/Logic FEATURES PINOUTS * 0.6m CRH CMOS Process - Latchup immune * High speed * Low power consumption * Wide operating power supply of 3.0V to 5.5V * Available QML Q or V processes * 16-lead flatpack 16-Lead Flatpack Top View CLR1 1 16 VDD J1 2 15 CLR2 K1 3 14 J2 CLK1 PRE1 4 5 13 12 K2 DESCRIPTION Q1 6 11 PRE2 The UT54ACS109E is a dual J-K positive triggered flip-flop. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the J and K input can be changed without affecting the levels at the outputs. The flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D flip-flops if J and K are tied together. Q1 7 8 10 9 Q2 VSS PRE1 J1 CLK1 K1 CLR1 PRE2 FUNCTION TABLE J2 (5) (2) (4) (3) (1) (14) (13) K2 (15) CLR2 CLK J K Q Q L H X X X H L H L X X X L H L L X X X H1 H1 H H L L L H H H H L Toggle H H L H No Change H H H H H H L X X H J1 C1 K1 R (6) (7) Q1 Q1 (10) Q2 (12) CLK2 CLR S (11) OUTPUT PRE Q2 LOGIC SYMBOL The devices are characterized over full HiRel temperature range of -55C to +125C. INPUTS CLK2 (9) Q2 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. L No Change Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum. In addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. 1 LOGIC DIAGRAM PRE Q CLK J Q K CLR OPERATIONAL ENVIRONMENT1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. 2 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD + .3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 3.0 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C 3 DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS109E7 ( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C) SYMBOL VIL VIH IIN VOL VOH IOS IOL IOH Ptotal Description CONDITION Low-level input voltage 1 High-level input voltage 1 VDD MAX UNIT 3.0V 0.9 V 5.5V 1.65 3.0V 2.1 5.5V 3.85 -1 A 3.0V 0.25 V 4.5V 0.25 VIN = VDD or VSS 5.5V Low-level output voltage 3 IOL = 100A Short-circuit output current 2 ,4 Low level output current9 High level output current9 Power dissipation 2, 8 IOH = -100A V 1 Input leakage current High-level output voltage 3 MIN 3.0V 2.75 4.5V 4.25 3.0V -100 100 5.5V -200 200 VIN = VDD or VSS 3.0V 6 VOL = 0.4V 5.5V 8 VIN = VDD or VSS 3.0V -6 VOH = VDD-0.4V 5.5V -8 CL = 50pF 5.5V 3.0V 2.9 0.8 mW/ MHz 5.5V 10 A VO = VDD and VSS V mA mA mA IDDQ Quiescent Supply Current VIN = VDD or VSS CIN Input capacitance 5 = 1MHz 0V 15 pF Output capacitance 5 = 1MHz 0V 15 pF COUT Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/ MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2. 8. Power dissipation specified per switching output. 9. This value is guaranteed based on characterization data, but not tested. 4 AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS109E2 (VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C) SYMBOL tPLH1 PARAMETER CLK to Q, Q VDD CL = 30pF CL = 50pF tPHL1 CLK to Q, Q CL = 30pF CL = 50pF tPLH2 PRE to Q CL = 30pF CL = 50pF tPHL2 PRE to Q CL = 30pF CL = 50pF tPLH3 CLR to Q CL = 30pF CL = 50pF tPHL3 CLR to Q CL = 30pF CL = 50pF fMAX4 tSU1 MAXIMUM UNIT ns 3.0V & 3.6V 4 23 4.5V & 5.5V 4 19 3.0V & 3.6V 4 27 4.5V & 5.5V 4 23 3.0V & 3.6V 5 27 4.5V & 5.5V 5 23 3.0V & 3.6V 5 31 4.5V & 5.5V 5 27 3.0V & 3.6V 1 16 4.5V & 5.5V 1 12 3.0V & 3.6V 1 20 4.5V & 5.5V 1 16 3.0V & 3.6V 1 19 4.5V & 5.5V 1 15 3.0V & 3.6V 1 23 4.5V & 5.5V 1 19 3.0V & 3.6V 2 16 4.5V & 5.5V 2 12 3.0V & 3.6V 2 20 4.5V & 5.5V 2 16 3.0V & 3.6V 2 19 4.5V & 5.5V 2 15 3.0V & 3.6V 2 23 4.5V & 5.5V 2 19 Maximum clock frequency CL = 50pF 3.0V, 4.5V, and 5.5V PRE or CLR inactive setup time before CLK CL = 50pF 3.0V, 4.5V, and 5.5V 5 MINIMUM 62 5 ns ns ns ns ns ns ns ns ns ns ns MHz ns tSU2 Data setup time before CLK CL = 50pF 3.0V, 4.5V, and 5.5V 5 ns tH3 Data hold time after CLK CL = 50pF 3.0V, 4.5V, and 5.5V 3 ns tW Minimum pulse width PRE or CLR low CLK high CLK low CL = 50pF 3.0V, 4.5V, and 5.5V 8 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2. 3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. 4. Historically maximum frequency "fMAX" was based off minimum pulse width (tW), fMAX = 1/2tW. In practice, the achievable fMAX is dictated by the CLK to Q propagation delays listed in the AC electrical table. For a more complete description on calculating the applicable fMAX reference, the application note titled "Frequency vs Load Capacitance for the MSI Product Family" is located at www.aeroflex.com/ 6 Packaging Ordering Information UT54ACS109E UT54 *** **** - * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Screening: (Note 3) C = HiRel Temperature Range (-55oC to +125oC) Package Type: U = 16-lead ceramic bottom-brazed dual-in-line Flatpack Part Number: 109E = Dual J-K Flip-Flops I/O Type: ACS = CMOS compatible I/O level Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices have 48 hours of burn-in and are test at -55oC, room temperature, and 125oC. Radiation characterisitics are neither tested nor guaranteed and may not be specified. 8 UT54ACS109E: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 16-lead ceramic bottom-brazed dual-in-line Flatpack Class Designator: Q = QML Class Q V = QML Class V Device Type: 02 = 1 rad(Si)/sec 03 = 50 to 300 rads(Si)/sec Drawing Number: 96540 = UT54ACS109E Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 9 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced HiRel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex Colorado Springs (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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