1
UT54ACS14E/UT54ACTS14E
Hex Inverting Schmitt Triggers
July, 2013
www.aeroflex.com/Logic
Datasheet
FEATURES
m CRH CMOS Process
- Latchup immune
High speed
Low power consumption
Wide power supply operating ran ge of 3.0V to 5.5V
Available QML Q or V processes
14-lead flatpack
UT54ACS14E - SMD 5962-96524
UT54ACTS14E - SMD 5962-96525
FUNCTION TABLE
LOGIC SYMB OL
DESCRIPTION
The UT54ACS14E and the UT54ACTS14E are hex inverters
with schmitt trigger inputs. The circuits perform the Boolean
function Y = A.
The devices are characterized over full HiRel temperature
range of -55C to +125C.
PINOUTS
14-Lead Flatpack
Top View
LOGIC DIAG RAM
INPUT OUTPUT
A Y
H L
L H
Y1
Y2
Y3
Y4
(1)
A1
(5)
A3
(11)
A5 (13)
A6
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
1
(3)
A2
(9)
A4
(2)
(10)
(12)
(4)
(8)
Y5
Y6
(6)
VDD
A6
Y6
A5
Y5
A4
Y4
A1
Y1
A2
Y2
A3
Y3
VSS
114
213
312
411
510
69
78
Y4
Y3
Y1
Y2
Y6
Y5
A4
A3
A1
A2
A6
A5
2
OPERATIONAL ENVIRONMENT 1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, PD = (Tj(max) - Tc(max) ) / jc
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 108 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -0.3 to VDD + 0.3 V
TSTG Storage Temperature range -65 to +150 C
TJMaximum junction temperature +175 C
TLS Lead temperature (soldering 5 seconds) +300 C
JC Thermal resistance junction to case 15 C/W
IIDC input current 10 mA
PDMaximum package power dissipation
permitted @ Tc = +125oC
3.3 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 3.0 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to +125 C
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DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS14E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C)
SYMBOL DESCRIPTION CONDITION MIN MAX UNIT
VT+ Schmitt trigger positive-going
threshold 1VDD from 3.0V to 5.5V 0.7VDD V
VT- Schmitt trigger negative-going
threshold 1VDD from 3.0V to 5.5V 0.3VDD V
VH1 Range of hysteresis (VT+ - VT-)VDD from 4.5V to 5.5V 0.6 1.5 V
VH2 Range of hysteresis (VT+ - VT-) VDD from 3.0V to 3.6V 0.3 1.2 V
IIN Input leakage current VIN = VDD or VSS -1 1A
VOL Low-level output voltage 3IOL = 100A
VDD from 3.0V to 5.5V
0.25 V
VOH High-level output voltage 3IOH = -100A
VDD from 3.0V to 5.5V
VDD - 0.25 V
IOS1 Short-circuit output current 2 ,4 VO = VDD and VSS
VDD from 4.5V to 5.5V
-200 200 mA
IOS2 Short-circuit output current 2 ,4 VO = VDD and VSS
VDD from 3.0V to 3.6V
-100 100 mA
IOL1 Low level output current9
(sink)
VIN = VDD or VSS
VOL = 0.4V
VDD from 4.5V to 5.5V
8mA
IOL2 Low level output current 9
(sink)
VIN = VDD or VSS
VOL = 0.4V
VDD from 3.0V to 3.6V
6mA
IOH1 High level output current9
(source)
VIN = VDD or VSS
VOH = VDD - 0.4V
VDD from 4.5V to 5.5V
-8 mA
IOH2 High level output current9
(source)
VIN = VDD or VSS
VOH = VDD - 0.4V
VDD from 3.0V to 3.6V
-6 mA
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second .
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Me thod 1019.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
Ptotal1 Power dissipation 2, 8 CL = 50pF
VDD from 4.5V to 5.5V
1.9 mW/
MHz
Ptotal2 Power dissipation 2, 8 CL = 50pF
VDD from 3.0V to 3.6V
0.76 mW/
MHz
IDDQ Quiescent Supply Current VIN = VDD or VSS
VDD from 3.0V to 5.5V
10 A
CIN Input capacitance 5 = 1MHz, VDD = 0 15 pF
COUT Output capacitance 5 = 1MHz, VDD = 0 15 pF
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AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS14E2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019.
SYMBOL PARAMETER Condition VDD MINIMUM MAXIMUM UNIT
tPHL Input to Yn CL = 50pF 3.0V to 3.6 V 2 18 ns
4.5V to 5.5 V 2 18 ns
tPLH Input to Yn CL = 50pF 3.0V to 3.6 V 2 17 ns
4.5V to 5.5 V 2 13 ns
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DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS14E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C)
SYMBOL DESCRIPTION CONDITION MIN MAX UNIT
VT+1 Schmitt trigger positive-going
threshold 1VDD from 4.5V to 5.5V 2.25 V
VT+2 Schmitt trigger positive-going
threshold 1VDD from 3.0V to 3.6V 2.0 V
VT-1 Schmitt trigge r negat ive-going
threshold 1VDD from 4.5V to 5.5V 0.5 V
VT-2 Schmitt trigge r negat ive-going
threshold 1VDD from 3.0V to 3.6V 0.5 V
VH1 Range of hysteresis (VT+1 - VT-1)VDD from 4.5V to 5.0V 0.4 1.5 V
VH2 Range of hysteresis (VT+2 - VT-2)VDD from 3.0V to 3.6V 0.2 1.2 V
IIN Input leakage current VIN = VDD or VSS -1 1A
VOL1 Low-level output voltage 3IOL = 8mA
VDD from 4.5V to 5.5V
0.4 V
VOL2 Low-level output voltage 3IOL = 6mA
VDD from 3.0V to 3.6V
0.4 V
VOH1 High-level output voltage 3IOH = -8mA
VDD from 4.5V to 5.5V
0.7VDD V
VOH2 High-level output voltage 3IOH = -6mA
VDD from 3.0V to 3.6V
2.4 V
IOS1 Short-circuit output current 2 ,4 VO = VDD or VSS
VDD from 4.5V to 5.5V
-200 200 mA
IOS1 Short-circuit output current 2 ,4 VO = VDD or VSS
VDD from 3.0V to 3.6V
-100 100 mA
IOL1 Low level output current9VIN = VDD or VSS
VOL = 0.4V
VDD from 4.5V to 5.5V
8mA
IOL2 Low level output current9VIN = VDD or VSS
VOL = 0.4V
VDD from 3.0V to 3.6V
6mA
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Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second .
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Me thod 1019.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
IOH1 High level output current9VIN = VDD or VSS
VOH = VDD-0.4V,
VDD from 4.5V to 5.5V
-8 mA
IOH2 High level output current9VIN = VDD or VSS
VOH = VDD - 0.4V
VDD from 3.0V to 3.6V
-6 mA
Ptotal1 Power dissipation 2, 8 CL = 50pF
VDD from 4.5V to 5.5V
1.3 mW/
MHz
Ptotal2 Power dissipation 2, 8 CL = 50pF
VDD from 3.0V to 3.6V
0.5 mW/
MHz
IDDQ Quiescent Supply Current VIN = VDD or VSS
VDD from 3.0V to 5.5V
10 A
IDDQ Quiescent Supply Current Delta For input under test
VIN = VDD -2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
3.1 mA
CIN Input capacitance 5 = 1MHz, VDD = 0 15 pF
COUT Output capacitance 5 = 1MHz, VDD = 0 15 pF
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AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS14E2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019.
SYMBOL PARAMETER Condition VDD MINIMUM MAXIMUM UNIT
tPHL Input to Yn CL = 50pF 3.0V to 3.6V 220 ns
4.5V to 5.5V 2 9
tPLH Input to Yn CL = 50pF 3.0V to 3.6V 320 ns
4.5V to 5.5V 212
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Figure 1. 14-Lead Flatpack
1. All exposed metallized areas are gold plated over
electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF-
38535.
4. Dimension symbol is in accordance with MIL-
PRF-38533.
5. Lead position and colanarity are not measured.
UT54ACS14E/UT54ACTS14E: SMD
Drawing Number:
96524 = UT54ACS14E
Device Type:
02 = 1 rad(Si)/sec
Package Type:
X = 14-lead ceramic bottom-brazed dual-in-line Flatpack
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
5962 ***** ** * *
**
Total Dose: (Note 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
03 = 50 to 300 rads(Si)/sec
Class Designator:
Q = QML Class Q
V = QML Class V
96525 = UT54ACTS14E
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML-2 and V is not available without radiation testing. For prototyping inquiries, contact factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test
Method 1019 Condition A and section 3. 11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5
rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.
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