ADJD-S313-QR999 Miniature Surface-Mount RGB Digital Color Sensor Data Sheet Description Features The ADJD-S313-QR999 is a cost effective, CMOS digital output RGB color sensor in miniature surface-mount package with a mere size of 5x5x0.75mm. The IC comes with integrated RGB filters, an analog-to-digital converter and a digital core for communication and sensitivity control. The output allows direct interface to micro-controller or other logic control for further signal processing without the need of any additional components. * Fully integrated RGB digital color sensor This device is designed to cater for wide dynamic range of illumination level and is ideal for applications like portable or mobile devices which demand higher integration, smaller size and low power consumption. Sensitivity control is performed by the serial interface and can be optimized individually for the different color channel. The sensor can also be used in conjunction with a white LED for reflective color management. * Built in internal oscillator General Specifications Feature Value * Digital I/O via 2-wire serial interface * Industry's smallest form factor - QFN 5x5x0.75mm * Adjustable sensitivity for different levels of illumination * Uniformly distributed RGB photodiode array * 7 bit resolution per channel output * Sleep function when not in use * No external components * Low supply voltage (VDD) 2.6V * 0C to 70C operating temperature * Lead free package Applications * General color detection and measurement Interface 100kHz serial interface * Mobile appliances such as mobile phones, PDAs, MP3 players,etc. Supply * Consumer appliances 2.6V digital (nominal), 2.6V analog (nominal) * Portable medical equipments * Portable color detector/reader Powering the Device No voltage must be applied to IO's during power-up and power-down ramp time VDDD / VDDA 0V tVDD_RAMP ESD Protection Diode Turn-On During Power-Up and Power-Down A particular power-up and power-down sequence must be used to prevent any ESD diode from turning on inadvertently. The figure above describes the sequence. In general, AVDD and DVDD should power-up and powerdown together to prevent ESD diodes from turning on inadvertently. During this period, no voltage should be applied to the IO's for the same reason. Ground Connection AGND and DGND must both be set to 0V and preferably star-connected to a central power source as shown in the application diagram. A potential difference between AGND and DGND may cause the ESD diodes to turn on inadvertently. Block Diagram SDASLV SCLSLV XRST Control Core Gain Selection RGB PHOTOSENSOR ARRAY SLEEP PHOTOCURRENT TO VOLTAGE CONVERSION RED ANALOG TO DIGITAL CONVERSION 2 PHOTOCURRENT TO VOLTAGE CONVERSION GREEN PHOTOCURRENT TO VOLTAGE CONVERSION BLUE Electrical Specifications Absolute Maximum Ratings (Notes 1 & 2) Parameter Symbol Minimum Maximum Units Storage temperature TSTG_ABS -40 85 C Digital supply voltage, DVDD to DVSS VDDD_ABS -0.5 3.7 V Analog supply voltage, AVDD to AVSS VDDA_ABS -0.5 3.7 V Input voltage VIN_ABS -0.5 VDDD+0.5 V Solder Reflow Peak temperature TL_ABS 235 C Human Body Model ESD rating ESDHBM_ABS 2 kV Notes All I/O pins All pins, human body model per JESD22-A114-B Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Units Free air operating temperature TA 0 25 70 C Digital supply voltage, DVDD to DVSS VDDD 2.5 2.6 3.6 V Analog supply voltage, AVDD to AVSS VDDA 2.5 2.6 3.6 V Output current load high IOH 3 mA Output current load low IOL 3 mA Input voltage high level (Note 4) VIH 0.7 VDDD VDDD V Input voltage low level (Note 4) VIL 0 0.3 VDDD V DC Electrical Specifications Over Recommended Operating Conditions (unless otherwise specified) Parameter Symbol Conditions Minimum Typical (Note 3) Output voltage high level (Note 5) VOH IOH = 3mA VDDD-0.8 VDDD-0.4 Output voltage low level (Note 6) VOL IOL = 3mA 0.2 0.4 V Dynamic supply current (Note 7,8) IDD_DYN (Note 9) 9.4 14 mA Static supply current (Note 8) IDD_STATIC (Note 9) 2.7 Sleep-mode supply current (Note 8) IDD_SLP (Note 9) 0.2 Input leakage current ILEAK -10 Maximum Units V mA 15 uA 10 uA AC Electrical Specifications Parameter Symbol Internal clock frequency fCLK 3 Conditions Minimum Typical (Note 3) Maximum Units 16 26 38 MHz Optical Specification Parameter Symbol Conditions Dark offset* VD Ee = 0 Typical (Note 3) Minimum Maximum 65 Units LSB *code is from dark code to (dark code + 128LSB) Minimum sensitivity Parameter Symbol Conditions Minimum Irradiance Responsivity Re P = 460 nm Refer Note 10 B P = 542 nm Refer Note 11 G P = 622 nm Refer Note 12 R Typical (Note 3) Maximum 33 Units LSB / (mW/cm2) 47 73 Maximum sensitivity Parameter Symbol Conditions Minimum Irradiance Responsivity Re P = 460 nm Refer Note 10 B P = 542 nm Refer Note 11 G P = 622 nm Refer Note 12 R Typical (Note 3) Maximum 1104 Units LSB / (mW/cm2) 1552 2210 Minimum sensitivity Parameter Symbol Saturation Irradiance (note 13) Conditions Minimum P = 460 nm Refer Note 10 B P = 542 nm Refer Note 11 G P = 622 nm Refer Note 12 R Typical (Note 3) Maximum 4.59 Units mW/ cm2 3.18 2.05 Maximum sensitivity Parameter Saturation Irradiance (note 13) 4 Symbol Conditions Minimum P = 460 nm Refer Note 10 B P = 542 nm Refer Note 11 G P = 622 nm Refer Note 12 R Typical (Note 3) 0.14 0.10 0.07 Maximum Units mW/ cm2 Spectral response 1 0.8 Relative sensitivity Notes: 1. The "Absolute Maximum Ratings" are those values beyond which damage to the device may occur. The device should not be operated at these limits. The parametric values defined in the "Electrical Specifications" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 2. Unless otherwise specified, all voltages are referenced to ground. 3. Specified at room temperature (25C) and VDDD = VDDA = 2.6V. 4. Applies to all DI pins. 5. Applies to all DO pins. SDASLV go tri-state when output logic high. Minimum VOH depends on the pull-up resistor value. 6. Applies to all DO and DIO pins. 7. Dynamic testing is performed with the IC operating in a mode representative of typical operation. 8. Refers to total device current consumption. 9. Output and bidirectional pins are not loaded. 10. Test condition is blue light of peak wavelength (P) 460 nm and spectral half width (1/2) 25 nm. 11. Test condition is green light of peak wavelength (P) 542 nm and spectral half width (1/2) 35 nm 12. Test condition is red light of peak wavelength (P) 622 nm and spectral half width (1/2) 20 nm 13. Saturation irradiance = (MSB)/(Irradiance responsivity) 0.6 0.4 0.2 0 400 500 600 Wavelength (nm) 700 Typical spectral response when the gains for all the color channels are set at equal. Serial Interface Timing Information Parameter Symbol Minimum Maximum Units SCL clock frequency fscl 0 100 kHz (Repeated) START condition hold time tHD:STA 4 - s Data hold time tHD:DAT 0 3.45 s SCL clock low period tLOW 4.7 - s SCL clock high period tHIGH 4.0 - s Repeated START condition setup time tSU:STA 4.7 - s Data setup time tSU:DAT 250 - ns STOP condition setup time tSU:STO 4.0 - s Bus free time between START and STOP conditions tBUF 4.7 - s tHIGH tHD:STA tSU:DAT tBUF tSU:STA SDA SCL S Sr tLOW tHD:DAT Figure 1. Serial Interface Bus Timing Waveforms 5 tHD:STA P tSU:STO S High Level Description The sensor needs to be configured before it can be used. The gain selection needs to be set for optimum performance depending on light levels. The flowcharts below describe the different procedures required. SENSOR GAIN OPTIMIZATION SENSOR OPERATION Step 1 Hardware Reset Step 1 Hardware Reset Step 2 Device Initialization Step 2 Device Initialization Step 3 - 4 Select sensor gain settings Step 3 - 4 Select sensor gain settings Step 5 Acquire ADC readings Step 5 Acquire dark offset and store current offset values ADC readings optimum? NO Step 6 Acquire ADC readings YES STOP Sensor gain optimization flowchart * Please refer to application note for more detailed information. 6 Step 7 Compute sensor values STOP Sensor operation flowchart Detail Description Setup Value for Integration Time A hardware reset (by asserting XRST) should be performed before starting any operation. The following value can be written to each of the integration time registers to adjust the gain of the sensor. The default value after reset for these registers is 07H. The user controls and configures the device by programming a set of internal registers through a serial interface. At the start of application, the following setup data must be written to the setup registers: Value (Hex) Integration Time Slot 00 1 01 2 Register Setup Data (Hex) 02 3 03 SETUP0 01 03 4 04 SETUP1 01 04 5 0C SETUP2 01 05 6 0D SETUP3 01 06 7 0E SETUP4 01 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 Address (Hex) Sensor Gain Settings The sensor gain can be adjusted by varying the photodiode size and integration time of the sensor manually through the following registers. Sensor Sensitivity ~ Photodiode Size x Integration Time Slot Address (Hex) Register Description 0E 15 0B PDASR Red Channel Photodiode Size 0F 16 0A PDASG Green Channel Photodiode Size 09 PDASB Blue Channel Photodiode Size Sensor ADC Output Registers 11 TINTR Red Channel Integration Time 10 TINTG Green Channel Integration Time To obtain sensor ADC value, `02' Hex must be written to ACQ register before reading the Sensor ADC Output Registers. 0F TINTB Blue Channel Integration Time Setup Value for Photodiode Size Address (Hex) Register Description The following value can be written to each of the photodiode size registers to adjust the gain of the sensor. The default value after reset for these registers is 07H. 02 ACQ Acquire sensor analog to digital converter (ADC) values when 02H is written. Reset to 00H when sensor acquisition is completed Value (Hex) Photodiode Size 44 ADCR Sensor Red channel ADC value 01 1/4 43 ADCG Sensor Green channel ADC value 03 1/2 42 ADCB Sensor Blue channel ADC value 07 3/4 0F Full 7 Serial Interface Reference START/STOP Condition Description The master initiates and terminates all serial data transfers. To begin a serial data transfer, the master must send a unique signal to the bus called a START condition. This is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The programming interface to the ADJD-S313 is a 2-wire serial bus. The bus consists of a serial clock (SCL) and a serial data (SDA) line. The SDA line is bi-directional on ADJD-S313 and must be connected through a pull-up resistor to the positive power supply. When the bus is free, both lines are HIGH. The 2-wire serial bus on ADJD-S313 requires one device to act as a master while all other devices must be slaves. A master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer while a device addressed by the master is called a slave. Slaves are identified by unique device addresses. Both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. A transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus. The ADJD-S313 serial bus interface always operates as a slave transceiver with a data transfer rate of up to 100kbit/s. The master terminates the serial data transfer by sending another unique signal to the bus called a STOP condition. This is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH. The bus is considered to be busy after a START (S) condition. It will be considered free a certain time after the STOP (P) condition. The bus stays busy if a repeated START (Sr) is sent instead of a STOP condition. The START and repeated START conditions are functionally identical. Data Transfer The master initiates data transfer after a START condition. Data is transferred in bits with the master generating one clock pulse for each bit sent. For a data bit to be valid, the SDA data line must be stable during the HIGH period of the SCL clock line. Only during the LOW period of the SCL clock line can the SDA data line change state to either HIGH or LOW. SDA SCL S P START condition STOP condition Figure 1. START/STOP Condition SDA SCL Data valid Figure 2. Data Bit Transfer 8 Data change The SCL clock line synchronizes the serial data transmission on the SDA data line. It is always generated by the master. The frequency of the SCL clock line may vary throughout the transmission as long as it still meets the minimum timing requirements. The master by default drives the SDA data line. The slave drives the SDA data line only when sending an acknowledge bit after the master writes data to the slave or when the master requests the slave to send data. The SDA data line driven by the master may be implemented on the negative edge of the SCL clock line. The master may sample data driven by the slave on the positive edge of the SCL clock line. Figure shows an example of a master implementation and how the SCL clock line and SDA data line can be synchronized. A complete data transfer is 8-bits long or 1-byte. Each byte is sent most significant bit (MSB) first followed by an acknowledge or not acknowledge bit. Each data transfer can send an unlimited number of bytes (depending on the data format). SDA data sampled on the positive edge of SCL SDA SCL SDA data driven on the negative edge of SCL Figure 3. Data Bit Synchronization Acknowledge/Not acknowledge The receiver must always acknowledge each byte sent in a data transfer. In the case of the slavereceiver and master-transmitter, if the slavereceiver does not send an acknowledge bit, the master-transmitter can either STOP the transfer or generate a repeated START to start a new transfer. P SDA SCL MSB S or Sr 1 LSB 2 ACK 8 9 MSB 1 LSB 2 8 START or repeated START condition SDA pulled LOW by receiver SDA (SLAVE-RECEIVER) SCL (MASTER) Figure 5. Slave-Receiver Acknowledge 9 9 Sr Sr or P STOP or repeated START condition Figure 4. Data Byte Transfer SDA (MASTER-TRANSMITTER) NO ACK Acknowledge LSB SDA left HIGH by transmitter 8 9 Acknowledge clock pulse In the case of the master-receiver and slavetransmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. The master can then send a STOP or repeated START condition to begin a new data transfer. In all cases, the master generates the acknowledge or not acknowledge SCL clock pulse. Addressing Each slave device on the serial bus needs to have a unique address. This is the first byte that is sent by the master-transmitter after the START condition. The address is defined as the first seven bits of the first byte. The eighth bit or least significant bit (LSB) determines the direction of data transfer. A `one' in the LSB of the first byte indicates that the master will read data from the addressed slave (masterreceiver and slave-transmitter). A `zero' in this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver). A device whose address matches the address sent by the master will respond with an acknowledge for the first byte and set itself up as a slavetransmitter or slave-receiver depending on the LSB of the first byte. The slave address on ADJD-S313 is 0x58 (7-bits). SDA (SLAVE-TRANSMITTER) P SDA (MASTER-RECEIVER) SDA left HIGH by receiver SCL (MASTER) 8 MSB LSB A6 A5 A4 A3 A2 A1 A0 1 0 1 1 0 0 0 Slave address 10 Not acknowledge R/W Sr 9 Acknowledge clock pulse Figure 6. Master-Receiver Acknowledge Figure 7. Slave Addressing SDA left HIGH by transmitter LSB STOP or repeated START condition Data format ADJD-S313 uses a register-based programming architecture. Each register has a unique address and controls a specific function inside the chip. To write to a register, the master first generates a START condition. Then it sends the slave address for the device it wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants to write to the slave. The addressed device will then acknowledge the master. The master writes the register address it wants to access and waits for the slave to acknowledge. The master then writes the new register data. Once the slave acknowledges, the master generates a STOP condition to end the data transfer. Start condition S To read from a register, the master first generates a START condition. Then it sends the slave address for the device it wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants to write to the slave. The addressed device will then acknowledge the master. The master writes the register address it wants to access and waits for the slave to acknowledge. The master then generates a repeated START condition and resends the slave address sent previously. The least significant bit (LSB) of the slave address must indicate that the master wants to read from the slave. The addressed device will then acknowledge the master. The master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. The master then generates a STOP condition to end the data transfer. Master will write data A6 A5 A4 A3 A2 A1 A0 W Stop condition A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Master sends slave address Master writes register address Slave acknowledge P Master writes register data Slave acknowledge Slave acknowledge Figure 8. Register Byte Write Protocol Start condition S A6 A5 A4 A3 A2 A1 A0 W Master will read data Stop condition A D7 D6 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A Master writes register address Master sends slave address Master reads register data Master sends slave address Slave acknowledge Figure 9. Register Byte Read Protocol 11 Repeated start condition Master will write data Slave acknowledge Slave acknowledge P Master not acknowledge Application Diagrams Powering the Device Ground Connection HOST SYSTEM 15 SLEEP 10k AGND and DGND must both be set to 0V and preferably star-connected to a central power source as shown in the application diagram. A potential difference between AGND and DGND may cause the ESD diodes to turn on inadvertently. 10k 10k 10k DVDD SDA 10 XRST 12 SDASLV SCL 11 SCLSLV XRST HOST SYSTEM AVDD 19 Voltage Regulator AGND 8, 16, 17, 18 DGND 5, 6 DVDD 7 Voltage Regulator Star-connected ground Pin Information PIN NAME TYPE DESCRIPTION 1 NC No connect No connect. Leave floating. 2 NC No connect No connect. Leave floating. 3 NC No connect No connect. Leave floating. 4 NC No connect No connect. Leave floating. 5 DGND Ground Tie to digital ground. 6 DGND Ground Tie to digital ground. 7 DVDD Power Digital power pin. 8 AGND Ground Tie to analog ground. 9 NC No connect No connect. Leave floating. 10 XRST Input Global, asynchronous, active-low system reset. When asserted low, XRST resets all registers. Minimum reset pulse low is 10 s and must be provided by external circuitry. 11 SCLSLV Input 12 SDASLV Input/Output (tri-state high) SDASLV and SCLSLV are the serial interface communications pins. SDASLV is the bidirectional data pin and SCLSLV is the interface clock. A pull-up resistor should be tied to SDASLV because it goes tri-state to output logic 1. 13 NC No connect No connect. Leave floating. 14 NC No connect No connect. Leave floating. 15 SLEEP Input When SLEEP=1, the device goes into sleep mode. In sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. 16 AGND Ground Tie to analog ground. 17 AGND Ground Tie to analog ground. 18 AGND Ground Tie to analog ground. 19 AVDD Power Analog power pin. 20 NC No connect No connect. Leave floating. 12 Package Dimensions Bottom View NOTE: DIMENSIONS ARE IN MILIMETERS (MM) 13 Recommended Reflow Profile It is recommended that Henkel Pb-free solder paste LF310 be used for soldering ADJD-S313. Below is the recommended soldering profile. T-peak T-reflow 230 5C/sec. 218 C/sec. DELTA-FLUX = 2 C/sec. max. TEMPERATURE T-max. T-min. DELTA-COOLING = 2 C/sec. max. 160 C 120C DELTA-RAMP = 1C/sec. max. 40-60 sec. max. 20-40 sec. max. t-pre t-peak TIME 20 Lead QFN Recommended PCB Land Pad Design 20 Lead QFN Recommended Stencil Design IPC-SM-782 is used as the standard for the PCB land pad design. Recommended PCB finishing is OSP. A stencil thickness of 2.18mm (6 mils) for this QFN package is recommended. 0.8 mm 0.4 mm 0.8 mm 3.19 mm 0.4 mm 5.5 mm 3.19 mm 2.18mm 3.9 mm 5.5 mm 14 Recommendations for Handling and Storage of ADJD-S313 Before Opening the MBB (Moisture Barrier Bag) After Opening the MBB (Moisture Barrier Bag) * The sensor component must be kept at 30C and 60%RH or less * The sensor component must be kept sealed in a MBB (Moisture Barrier Bag) stored at 30C and 70%RH or less at all times. * The sensor component should have a MET (Manufacturing Exposure Time) of 24 hours starting from the time of removal from the MBB to the soldering oven. * It should also be seal with a moisture absorbent material (Silica Gel) and an indicator card (Cobalt Chloride) to indicate the moisture within the bag. * If unused sensor component remain, it is recommended to store them back to the MBB. * If the indicator card has turned from blue to pink or it has exceeded the recommended MET (Manufacturing Exposure Time) of 24hrs, baking treatment should be performed using the following conditions before continue to IR reflow soldering. * Baking Treatment: 24 hours at 125C. Package Tape and Reel Dimensions Carrier Tape Dimensions 4.00 0.10 SEE NOTE #2 1.55 0.05 2.00 0.05 SEE NOTE #2 B R 0.50 TYP. 1.75 0.10 5.50 0.05 12.00 0.10 Bo A Ko A 8.00 0.10 B 1.50 (MIN.) SECTION B-B Ao 0.30 0.05 SECTION A-A NOTES: 1. Ao AND Bo MEASURED AT 0.3 mm ABOVE BASE OF POCKET. 2. 10 PITCHES CUMULATIVE TOLERANCE IS 0.2 mm. 3. DIMENSIONS ARE IN MILLIMETERS (mm). 15 Ao: Bo: Ko : PITCH: WIDTH: 5.30 5.30 2.20 8.00 12.00 Reel Dimensions 65 +1.5* 12.4 - 0.0 45 R10.65 R5.2 55.0 0.5 45 178.0 0.5 176.0 EMBOSSED RIBS RAISED: 0.25 mm WIDTH: 1.25 mm BACK VIEW 512 18.0 MAX.* NOTES: 1. *MEASURED AT HUB AREA. 2. ALL FLANGE EDGES TO BE ROUNDED. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright (c) 2006 Avago Technologies Pte. All rights reserved. 5989-4762EN - February 27, 2006