ADJD-S313-QR999 - Avago Technologies

ADJD-S313-QR999

Miniature Surface-Mount RGB Digital Color Sensor

Data Sheet

Description

The ADJD-S313-QR999 is a cost effective, CMOS

digital output RGB color sensor in miniature

surface-mount package with a mere size of

5x5x0.75mm. The IC comes with integrated RGB

filters, an analog-to-digital converter and a digital

core for communication and sensitivity control. The

output allows direct interface to micro-controller

or other logic control for further signal processing

without the need of any additional components.

This device is designed to cater for wide dynamic

range of illumination level and is ideal for

applications like portable or mobile devices which

demand higher integration, smaller size and low

power consumption. Sensitivity control is

performed by the serial interface and can be

optimized individually for the different color

channel. The sensor can also be used in conjunction

with a white LED for reflective color management.

General Specifications

Features

•Fully integrated RGB digital color sensor

•Digital I/O via 2-wire serial interface

•Industry’s smallest form factor – QFN 5x5x0.75mm

•Adjustable sensitivity for different levels of

illumination

•Uniformly distributed RGB photodiode array

•7 bit resolution per channel output

•Built in internal oscillator

•Sleep function when not in use

•No external components

•Low supply voltage (VDD) 2.6V

•0°C to 70°C operating temperature

•Lead free package

Applications

•General color detection and measurement

•Mobile appliances such as mobile phones, PDAs,

MP3 players,etc.

•Consumer appliances

•Portable medical equipments

•Portable color detector/reader

Feature Value

Interface 100kHz serial interface

Supply 2.6V digital (nominal), 2.6V analog (nominal)

Block Diagram

PHOTOCURRENT

TO VOLTAGE

CONVERSION

BLUE

SDASLV

SCLSLV

XRST RGB

PHOTOSENSOR

ARRAY

SLEEP

Gain

Selection

Control

Core

PHOTOCURRENT

TO VOLTAGE

CONVERSION

RED

PHOTOCURRENT

TO VOLTAGE

CONVERSION

GREEN

ANALOG TO

DIGITAL

CONVERSION

Powering the Device

tVDD_RAMP

VDDD / VDDA

No voltage must be applied to IO's during

power-up and power-down ramp time

ESD Protection Diode Turn-On During Power-Up and

Power-Down

A particular power-up and power-down sequence must

be used to prevent any ESD diode from turning on

inadvertently. The figure above describes the sequence.

In general, AVDD and DVDD should power-up and

powerdown together to prevent ESD diodes from

turning on inadvertently. During this period, no voltage

should be applied to the IO’s for the same reason.

Ground Connection

AGND and DGND must both be set to 0V and preferably

star-connected to a central power source as shown in

the application diagram. A potential difference between

AGND and DGND may cause the ESD diodes to turn on

inadvertently.

Electrical Specifications

Absolute Maximum Ratings (Notes 1 & 2)

Recommended Operating Conditions

DC Electrical Specifications

Over Recommended Operating Conditions (unless otherwise specified)

AC Electrical Specifications

Parameter Symbol Conditions Minimum

Typical

(Note 3) Maximum Units

Output voltage high level (Note 5) VOH IOH = 3mA VDDD-0.8 VDDD-0.4 V

Output voltage low level (Note 6) VOL IOL = 3mA 0.2 0.4 V

Dynamic supply current (Note 7,8) IDD_DYN (Note 9) 9.4 14 mA

Static supply current (Note 8) IDD_STATIC (Note 9) 2.7 mA

Sleep-mode supply current (Note 8) IDD_SLP (Note 9) 0.2 15 uA

Input leakage current ILEAK -10 10 uA

Parameter Symbol Minimum Maximum Units Notes

Storage temperature TSTG_ABS -40 85 °C

Digital supply voltage, DVDD to DVSS VDDD_ABS -0.5 3.7 V

Analog supply voltage, AVDD to AVSS VDDA_ABS -0.5 3.7 V

Input voltage VIN_ABS -0.5 VDDD+0.5 V All I/O pins

Solder Reflow Peak temperature TL_ABS 235 °C

Human Body Model ESD rating ESDHBM_ABS 2 kV All pins, human

body model per

JESD22-A114-B

Parameter Symbol Conditions Minimum

Typical

(Note 3) Maximum Units

Internal clock frequency fCLK 16 26 38 MHz

Parameter Symbol Minimum Typical Maximum Units

Free air operating temperature TA02570°C

Digital supply voltage, DVDD to DVSS VDDD 2.5 2.6 3.6 V

Analog supply voltage, AVDD to AVSS VDDA 2.5 2.6 3.6 V

Output current load high IOH 3mA

Output current load low IOL 3mA

Input voltage high level (Note 4) VIH 0.7 VDDD VDDD V

Input voltage low level (Note 4) VIL 00.3 V

DDD V

Maximum sensitivity

Minimum sensitivity

Maximum sensitivity

Parameter Symbol Conditions Minimum

Typical

(Note 3) Maximum Units

Irradiance Responsivity Re λP = 460 nm

Refer Note 10 B33 LSB /

(mW/cm2)

λP = 542 nm

Refer Note 11 G47

λP = 622 nm

Refer Note 12 R73

Parameter Symbol Conditions Minimum

Typical

(Note 3) Maximum Units

Irradiance Responsivity Re λP = 460 nm

Refer Note 10 B1104 LSB /

(mW/cm2)

λP = 542 nm

Refer Note 11 G1552

λP = 622 nm

Refer Note 12 R2210

Parameter Symbol Conditions Minimum

Typical

(Note 3) Maximum Units

Saturation Irradiance

(note 13)

λP = 460 nm

Refer Note 10 B4.59 mW/

cm2

λP = 542 nm

Refer Note 11 G3.18

λP = 622 nm

Refer Note 12 R2.05

Parameter Symbol Conditions Minimum

Typical

(Note 3) Maximum Units

Saturation Irradiance

(note 13)

λP = 460 nm

Refer Note 10 B0.14 mW/

cm2

λP = 542 nm

Refer Note 11 G0.10

λP = 622 nm

Refer Note 12 R0.07

Minimum sensitivity

Optical Specification

*code is from dark code to (dark code + 128LSB)

Parameter Symbol Conditions Minimum

Typical

(Note 3) Maximum Units

Dark offset* VDEe = 0 65 LSB

Spectral response

0.2

0.4

0.6

0.8

400 500 600 700

Wavelength (nm)

Relative sensitivity

Typical spectral response when the gains for all the

color channels are set at equal.

Serial Interface Timing Information

Figure 1. Serial Interface Bus Timing Waveforms

Parameter Symbol Minimum Maximum Units

SCL clock frequency f

scl

0 100 kHz

(Repeated) START condition hold time t

HD:STA

4µs

Data hold time t

HD:DAT

0 3.45 µs

SCL clock low period t

LOW

4.7 - µs

SCL clock high period t

HIGH

4.0 - µs

Repeated START condition setup time t

SU:STA

4.7 - µs

Data setup time t

SU:DAT

250 - ns

STOP condition setup time t

SU:STO

4.0 - µs

Bus free time between START and STOP conditions t

BUF

4.7 - µs

Notes:

1. The “Absolute Maximum Ratings” are those values beyond which

damage to the device may occur. The device should not be

operated at these limits. The parametric values defined in the

“Electrical Specifications” table are not guaranteed at the absolute

maximum ratings. The “Recommended Operating Conditions”

table will define the conditions for actual device operation.

2. Unless otherwise specified, all voltages are referenced to ground.

3. Specified at room temperature (25°C) and VDDD = VDDA = 2.6V.

4. Applies to all DI pins.

5. Applies to all DO pins. SDASLV go tri-state when output logic

high. Minimum VOH depends on the pull-up resistor value.

6. Applies to all DO and DIO pins.

7. Dynamic testing is performed with the IC operating in a mode

representative of typical operation.

8. Refers to total device current consumption.

9. Output and bidirectional pins are not loaded.

10. Test condition is blue light of peak wavelength (λP) 460 nm and

spectral half width (∆λ½) 25 nm.

11. Test condition is green light of peak wavelength (λP) 542 nm and

spectral half width (∆λ½) 35 nm

12. Test condition is red light of peak wavelength (λP) 622 nm and

spectral half width (∆λ½) 20 nm

13. Saturation irradiance = (MSB)/(Irradiance responsivity)

SDA

SCL

tHD:STA

tLOW

tHIGH tSU:DAT

tHD:DAT tSU:STO

tBUF

SPS

tSU:STA

tHD:STA

High Level Description

The sensor needs to be configured before it can be

used. The gain selection needs to be set for

optimum performance depending on light levels.

The flowcharts below describe the different

procedures required.

Sensor gain optimization flowchart

Sensor operation flowchart

SENSOR GAIN

OPTIMIZATION

Step 1

Hardware Reset

Step 2

Device Initialization

Step 3 - 4

Select sensor gain settings

Step 5

Acquire ADC readings

ADC readings

optimum?

STOP

YES

SENSOR

OPERATION

Step 1

Hardware Reset

Step 2

Device Initialization

Step 3 - 4

Select sensor gain settings

Step 5

Acquire dark offset and

store current offset values

Step 6

Acquire ADC readings

Step 7

Compute sensor values

STOP

* Please refer to application note for more detailed

information.

Detail Description

A hardware reset (by asserting XRST) should be

performed before starting any operation.

The user controls and configures the device by

programming a set of internal registers through a

serial interface. At the start of application, the

following setup data must be written to the setup

registers:

Address

(Hex) Register

Setup Data

(Hex)

03 SETUP0 01

04 SETUP1 01

0C SETUP2 01

0D SETUP3 01

0E SETUP4 01

Sensor Gain Settings

The sensor gain can be adjusted by varying the

photodiode size and integration time of the sensor

manually through the following registers.

Sensor Sensitivity ~ Photodiode Size x Integration

Time Slot

Setup Value for Photodiode Size

The following value can be written to each of the

photodiode size registers to adjust the gain of the

sensor. The default value after reset for these

registers is 07H.

Setup Value for Integration Time

The following value can be written to each of the

integration time registers to adjust the gain of the

sensor. The default value after reset for these

registers is 07H.

Sensor ADC Output Registers

To obtain sensor ADC value, ‘02’ Hex must be written

to ACQ register before reading the Sensor ADC Output

Registers.

Address

(Hex) Register Description

02 ACQ Acquire sensor analog to digital

converter (ADC) values when 02H

is written. Reset to 00H when

sensor acquisition is completed

44 ADCR Sensor Red channel ADC value

43 ADCG Sensor Green channel ADC value

42 ADCB Sensor Blue channel ADC value

Value (Hex) Photodiode Size

01 ¼

03 ½

07 ¾

0F Full

Value (Hex) Integration Time Slot

00 1

01 2

02 3

03 4

04 5

05 6

06 7

07 8

08 9

09 10

0A 11

0B 12

0C 13

0D 14

0E 15

0F 16

Address

(Hex) Register Description

0B PDASR Red Channel Photodiode Size

0A PDASG Green Channel Photodiode Size

09 PDASB Blue Channel Photodiode Size

11 TINTR Red Channel Integration Time

10 TINTG Green Channel Integration Time

0F TINTB Blue Channel Integration Time

Serial Interface Reference

Description

The programming interface to the ADJD-S313 is a

2-wire serial bus. The bus consists of a serial clock

(SCL) and a serial data (SDA) line. The SDA line is

bi-directional on ADJD-S313 and must be

connected through a pull-up resistor to the positive

power supply. When the bus is free, both lines are

HIGH.

The 2-wire serial bus on ADJD-S313 requires one

device to act as a master while all other devices

must be slaves. A master is a device that initiates a

data transfer on the bus, generates the clock signal

and terminates the data transfer while a device

addressed by the master is called a slave. Slaves

are identified by unique device addresses.

Both master and slave can act as a transmitter or a

receiver but the master controls the direction for

data transfer. A transmitter is a device that sends

data to the bus and a receiver is a device that

receives data from the bus.

The ADJD-S313 serial bus interface always operates

as a slave transceiver with a data transfer rate of

up to 100kbit/s.

Figure 1. START/STOP Condition

START condition

STOP condition

SDA

SCL

START/STOP Condition

The master initiates and terminates all serial data

transfers. To begin a serial data transfer, the master

must send a unique signal to the bus called a START

condition. This is defined as a HIGH to LOW

transition on the SDA line while SCL is HIGH.

The master terminates the serial data transfer by

sending another unique signal to the bus called a

STOP condition. This is defined as a LOW to HIGH

transition on the SDA line while SCL is HIGH.

The bus is considered to be busy after a START (S)

condition. It will be considered free a certain time

after the STOP (P) condition. The bus stays busy if

a repeated START (Sr) is sent instead of a STOP

condition.

The START and repeated START conditions are

functionally identical.

Data Transfer

The master initiates data transfer after a START

condition. Data is transferred in bits with the master

generating one clock pulse for each bit sent. For a

data bit to be valid, the SDA data line must be

stable during the HIGH period of the SCL clock line.

Only during the LOW period of the SCL clock line

can the SDA data line change state to either HIGH

or LOW.

SDA

SCL

Data valid Data change

Figure 2. Data Bit Transfer

The SCL clock line synchronizes the serial data

transmission on the SDA data line. It is always

generated by the master. The frequency of the SCL

clock line may vary throughout the transmission as

long as it still meets the minimum timing

requirements.

The master by default drives the SDA data line. The

slave drives the SDA data line only when sending

an acknowledge bit after the master writes data to

the slave or when the master requests the slave to

send data.

The SDA data line driven by the master may be

implemented on the negative edge of the SCL clock

line. The master may sample data driven by the

slave on the positive edge of the SCL clock line.

Figure shows an example of a master

implementation and how the SCL clock line and

SDA data line can be synchronized.

A complete data transfer is 8-bits long or 1-byte.

Each byte is sent most significant bit (MSB) first

followed by an acknowledge or not acknowledge

bit. Each data transfer can send an unlimited

number of bytes (depending on the data format).

Figure 3. Data Bit Synchronization

Figure 4. Data Byte Transfer

Figure 5. Slave-Receiver Acknowledge

Acknowledge/Not acknowledge

The receiver must always acknowledge each byte

sent in a data transfer. In the case of the slave-

receiver and master-transmitter, if the slave-

receiver does not send an acknowledge bit, the

master-transmitter can either STOP the transfer or

generate a repeated START to start a new transfer.

SDA

SCL

SDA data sampled on the

positive edge of SCL

SDA data driven on the

negative edge of SCL

SDA

SCL

MSB LSB

12 89

ACK

12 89

ACK

START or repeated

START condition

STOP or repeated

START condition

MSB LSB

SCL

(MASTER) 89

SDA

(SLAVE-RECEIVER)

SDA

(MASTER-TRANSMITTER) LSB

Acknowledge

clock pulse

SDA left HIGH

by transmitter

SDA pulled LOW

by receiver

Addressing

Each slave device on the serial bus needs to have a

unique address. This is the first byte that is sent by

the master-transmitter after the START condition.

The address is defined as the first seven bits of the

first byte.

The eighth bit or least significant bit (LSB)

determines the direction of data transfer. A ‘one’

in the LSB of the first byte indicates that the master

will read data from the addressed slave (master-

receiver and slave-transmitter). A ‘zero’ in this

position indicates that the master will write data

to the addressed slave (master-transmitter and

slave-receiver).

A device whose address matches the address sent

by the master will respond with an acknowledge

for the first byte and set itself up as a slave-

transmitter or slave-receiver depending on the LSB

of the first byte.

The slave address on ADJD-S313 is 0x58 (7-bits).

In the case of the master-receiver and slave-

transmitter, the master generates a not

acknowledge to signal the end of the data transfer

to the slave-transmitter. The master can then send

a STOP or repeated START condition to begin a new

data transfer.

In all cases, the master generates the acknowledge

or not acknowledge SCL clock pulse.

SCL

(MASTER) 89

SDA

(SLAVE-TRANSMITTER)

SDA

(MASTER-RECEIVER)

Acknowledge

clock pulse

LSB SDA left HIGH

by transmitter

Not

acknowledge

SDA left HIGH

by receiver

STOP or repeated

START condition

Figure 6. Master-Receiver Acknowledge

MSB LSB

R/W

A6 A5 A4 A3 A2 A0

Slave address

10 110

Figure 7. Slave Addressing

A6 A5 A4 A3 A2 A1 A0 W AS A PD7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Master sends

slave address

Master writes

Master will write dataStart condition Stop condition

Slave acknowledge

Slave acknowledgeSlave acknowledge

Data format

ADJD-S313 uses a register-based programming

architecture. Each register has a unique address and

controls a specific function inside the chip.

To write to a register, the master first generates a

START condition. Then it sends the slave address

for the device it wants to communicate with. The

least significant bit (LSB) of the slave address must

indicate that the master wants to write to the slave.

The addressed device will then acknowledge the

master.

The master writes the register address it wants to

access and waits for the slave to acknowledge. The

master then writes the new register data. Once the

slave acknowledges, the master generates a STOP

condition to end the data transfer.

Figure 8. Register Byte Write Protocol

A6 A5 A4 A3 A2 A1 A0 W AS D7 D6 D5 D4 D3 D2 D1 D0

Master will write dataStart condition

Slave acknowledge

A PD7 D6 D5 D4 D3 D2 D1 D0

Stop condition

A6 A5 A4 A3 A2 A1 A0 RSr

Master will read data

Repeated start

condition

Slave acknowledge

Master not

acknowledge

Slave acknowledge

Master sends

slave address

Master writes

Master sends

slave address

Master reads

To read from a register, the master first generates

a START condition. Then it sends the slave address

for the device it wants to communicate with. The

least significant bit (LSB) of the slave address must

indicate that the master wants to write to the slave.

The addressed device will then acknowledge the

master.

The master writes the register address it wants to

access and waits for the slave to acknowledge. The

master then generates a repeated START condition

and resends the slave address sent previously. The

least significant bit (LSB) of the slave address must

indicate that the master wants to read from the

slave. The addressed device will then acknowledge

the master.

The master reads the register data sent by the slave

and sends a no acknowledge signal to stop reading.

The master then generates a STOP condition to end

the data transfer.

Figure 9. Register Byte Read Protocol

Powering the Device

Ground Connection

AGND and DGND must both be set to 0V and

preferably star-connected to a central power source

as shown in the application diagram. A potential

difference between AGND and DGND may cause the

ESD diodes to turn on inadvertently.

Pin Information

AVDD DGND DVDDAGND

XRST

SDASLV

SCLSLV

Voltage

Regulator

Voltage

Regulator

HOST

SYSTEM

XRST

SDA

SCL

19 8, 16,

17, 18

5, 6 7

Star-connected ground

SLEEP

10k

HOST

SYSTEM

10k

DVDD

PIN NAME TYPE DESCRIPTION

1 NC No connect No connect. Leave floating.

2 NC No connect No connect. Leave floating.

3 NC No connect No connect. Leave floating.

4 NC No connect No connect. Leave floating.

5 DGND Ground Tie to digital ground.

6 DGND Ground Tie to digital ground.

7 DVDD Power Digital power pin.

8 AGND Ground Tie to analog ground.

9 NC No connect No connect. Leave floating.

10 XRST Input Global, asynchronous, active-low system reset. When asserted low, XRST

resets all registers. Minimum reset pulse low is 10 µs and must be provided by

external circuitry.

11 SCLSLV Input SDASLV and SCLSLV are the serial interface communications pins. SDASLV is

the bidirectional data pin and SCLSLV is the interface clock. A pull-up resistor

should be tied to SDASLV because it goes tri-state to output logic 1.

12 SDASLV Input/Output

(tri-state high)

13 NC No connect No connect. Leave floating.

14 NC No connect No connect. Leave floating.

15 SLEEP Input When SLEEP=1, the device goes into sleep mode. In sleep mode, all analog

circuits are powered down and the clock signal is gated away from the core

logic resulting in very low current consumption.

16 AGND Ground Tie to analog ground.

17 AGND Ground Tie to analog ground.

18 AGND Ground Tie to analog ground.

19 AVDD Power Analog power pin.

20 NC No connect No connect. Leave floating.

Application Diagrams

Package Dimensions

Bottom View

NOTE: DIMENSIONS ARE IN MILIMETERS (MM)

Recommended Reflow Profile

It is recommended that Henkel Pb-free solder paste

LF310 be used for soldering ADJD-S313. Below is

the recommended soldering profile.

20 Lead QFN Recommended Stencil Design

A stencil thickness of 2.18mm (6 mils) for this QFN

package is recommended.

3.19 mm

0.8 mm

0.4 mm

5.5 mm

3.9 mm

2.18mm

0.8 mm

0.4 mm

20 Lead QFN Recommended PCB Land Pad Design

IPC-SM-782 is used as the standard for the PCB land

pad design. Recommended PCB finishing is OSP.

DELTA-FLUX = 2 ˚C/sec. max.

DELTA-COOLING = 2 ˚C/sec. max.

T-min.

T-max.

T-reflow

T-peak

t-peakt-pre

40-60 sec. max. 20-40 sec. max.

120˚C

160 ˚C

218 ˚C/sec.

230 ± 5˚C/sec.

TIME

TEMPERATURE

DELTA-RAMP =

1˚C/sec. max.

Package Tape and Reel Dimensions

Carrier Tape Dimensions

Recommendations for Handling and Storage of

ADJD-S313

Before Opening the MBB (Moisture Barrier Bag)

•The sensor component must be kept sealed in a

MBB (Moisture Barrier Bag) stored at 30°C and

70%RH or less at all times.

•It should also be seal with a moisture absorbent

material (Silica Gel) and an indicator card (Cobalt

Chloride) to indicate the moisture within the bag.

After Opening the MBB (Moisture Barrier Bag)

•The sensor component must be kept at 30°C and

60%RH or less

•The sensor component should have a MET

(Manufacturing Exposure Time) of 24 hours starting

from the time of removal from the MBB to the

soldering oven.

•If unused sensor component remain, it is

recommended to store them back to the MBB.

•If the indicator card has turned from blue to pink or

it has exceeded the recommended MET

(Manufacturing Exposure Time) of 24hrs, baking

treatment should be performed using the following

conditions before continue to IR reflow soldering.

•Baking Treatment: 24 hours at 125°C.

SECTION B-B

SECTION A-A

0.30 ± 0.05

1.75 ± 0.10

5.50 ± 0.05

12.00 ± 0.10

R 0.50 TYP.

1.55 ± 0.05

8.00 ± 0.10 1.50 (MIN.)

4.00 ± 0.10

SEE NOTE #2

2.00 ± 0.05

SEE NOTE #2

Ao:

Bo:

Ko:

PITCH:

WIDTH:

5.30

2.20

8.00

12.00

NOTES:

1. Ao AND Bo MEASURED AT 0.3 mm ABOVE BASE OF POCKET.

2. 10 PITCHES CUMULATIVE TOLERANCE IS ± 0.2 mm.

3. DIMENSIONS ARE IN MILLIMETERS (mm).

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.

5989-4762EN - February 27, 2006

Reel Dimensions

18.0 MAX.*

178.0

0.5

12.4

R10.65

R5.2

+1.5*

- 0.0

55.0

0.5

176.0

512

EMBOSSED RIBS

RAISED: 0.25 mm

WIDTH: 1.25 mm BACK VIEW

NOTES:

1. *MEASURED AT HUB AREA.

2. ALL FLANGE EDGES TO BE ROUNDED.