TPS43337QDAPRQ1 - Texas Instruments

TPS43337-Q1

VBuckA

VBuckB

VBAT

2 V

V BAT

CV BUC K A

VBUCKB

TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

LOW I

, SINGLE-BOOST, FIXED-VOLTAGE DUAL SYNCHRONOUS BUCK CONTROLLER

Check for Samples: TPS43337-Q1

1FEATURES • Peak Gate Drive Current 1.5 A

• Thermally Enhanced 38-Pin HTSSOP (DAP)

2• Qualified for Automotive Applications PowerPAD™ Package

• AEC-Q100 Qualified With the Following

Results: APPLICATIONS

– Device Temperature Grade 1: –40°C to • Automotive Start-Stop, Infotainment,

+125°C Ambient Operating Temperature Navigation Instrument Cluster Systems

– Device HBM ESD Classification Level H2 • Industrial and Automotive Multi-Rail DC

– Device CDM ESD Classification Level C2 Power-Distribution Systems and Electronic

• Two Synchronous Buck Controllers Control Units

• BuckA: Fixed Output Voltage of 3.4 V

• BuckB: Fixed Output Voltage of 1.235 V DESCRIPTION

The TPS43337-Q1 includes two current-mode

• One Pre-Boost Controller synchronous buck controllers and a voltage-mode

• Input Range up to 40 V, (Transients up to 60 boost controller. The device is ideally suited as a pre-

V), Operation Down to 2 V When Boost Is regulator stage with low IQrequirements and for

Enabled systems that must survive supply drops due to

• Low-Power Mode IQ: 34 µA (One Buck On), 43 cranking events. The integrated boost controller

µA (Two Bucks On) allows the device to operate down to 2 V at the input

without seeing a drop on the buck regulator output

• Low Shutdown Current Ish < 4 µA stages. At light loads, the buck controllers enable to

• Boost Output Selectable: 7 V, 8.85 V, or 10 V operate automatically in low power-mode, consuming

• Programmable Frequency and External just 34 µA of quiescent current.

Synchronization Range: 150 to 600 kHz The buck controllers have independent soft-start

• Separate Enable Inputs (ENA, ENB, ENC) capability and power-good indicators. Current

foldback in the buck controllers and cycle-by-cycle

• Selectable Forced Continuous Mode or current limitation in the boost controller provide

Automatic Low-Power Mode at Light Loads external MOSFET protection. The switching

• Sense Resistor or Inductor DCR Sensing for frequency is programable over 150 to 600 kHz or is

Buck Controllers synchronized to an external clock in the same range

• Out-of-Phase Switching Between Buck

Channels

Figure 1. Typical Application Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

space

ABSOLUTE MAXIMUM RATINGS(1)

MIN MAX UNIT

Voltage Input voltage: VIN, VBAT –0.3 60 V

Enable inputs: ENA, ENB –0.3 60 V

Bootstrap inputs: CBA, CBB –0.3 68 V

Phase inputs: PHA, PHB –0.7 60 V

Phase inputs: PHA, PHB (for 150 ns) –1 V

Feedback inputs: FBA, FBB –0.3 13 V

Error amplifier outputs: COMPA, COMPB –0.3 13 V

Voltage High-side MOSFET driver: GA1–PHA, GB1–PHB –0.3 8.8 V

(buck function: Low-side MOSFET drivers: GA2, GB2 –0.3 8.8 V

BuckA and BuckB) Current-sense voltage: SA1, SA2, SB1, SB2 –0.3 13 V

Soft start: SSA, SSB –0.3 13 V

Power-good output: PGA, PGB –0.3 13 V

Power-good delay: DLYAB –0.3 13 V

Switching-frequency timing resistor: RT –0.3 13 V

SYNC, EXTSUP –0.3 13 V

Low-side MOSFET driver: GC1 –0.3 8.8 V

Error amplifier output: COMPC –0.3 13 V

Voltage Enable input: ENC –0.3 13 V

(boost function) Current-limit sense: DS –0.3 60 V

Output-voltage select: DIV –0.3 8.8 V

P-channel MOSFET driver: GC2 –0.3 60 V

Voltage

(PMOS driver) P-channel MOSFET driver: VIN–GC2 –0.3 8.8 V

Gate-driver supply: VREG –0.3 8.8 V

Junction temperature: TJ–40 150 °C

Temperature Operating temperature: TA–40 125 °C

Storage temperature: TS–55 165 °C

Human-body model (HBM) AEC-Q100 ±2 kV

Classification Level H2

VBAT, ENC, SYNC, VIN ±750

Charged-device model (CDM) AEC-Q100

Electrostatic Classification Level C2

discharge ratings All other pins ±500 V

PGA, PGB ±150

Machine model (MM) All other pins ±200

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to GND.

Product Folder Links: TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

THERMAL INFORMATION TPS43337-Q1

THERMAL METRIC(1) HTSSOP-DAP UNIT

38 PINS

θJA Junction-to-ambient thermal resistance(2) 27.3 °C/W

θJCtop Junction-to-case (top) thermal resistance(3) 19.6 °C/W

θJB Junction-to-board thermal resistance(4) 15.9 °C/W

ψJT Junction-to-top characterization parameter(5) 0.24 °C/W

ψJB Junction-to-board characterization parameter(6) 6.6 °C/W

θJCbot Junction-to-case (bottom) thermal resistance(7) 1.2 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT

Input voltage: VIN, VBAT 4 40

Enable inputs: ENA, ENB 0 40

Boot inputs: CBA, CBB 4 48

Buck function:

BuckA and BuckB Phase inputs: PHA, PHB –0.6 40 V

voltage Current-sense voltage: SA1, SA2, SB1, SB2 0 11

Power-good output: PGA, PGB 0 11

SYNC, EXTSUP 0 9

Enable input: ENC 0 9

Boost function Voltage sense: DS 40 V

DIV 0 VREG

Operating Temperature: TA–40 125 °C

Product Folder Links: TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

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DC ELECTRICAL CHARACTERISTICS

VIN = 8 to 18 V, TJ= –40°C to +150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1.0 Input Supply

Boost controller enabled, after initial start-up

1.1 VBAT Supply voltage 2 40 V

condition is satisfied

Input voltage required for device 6.5 40

on initial start-up

1.2 VIN V

Buck regulator operating range 4 40

after initial start-up

VIN falling. After a reset, initial start-up conditions 3.5 3.6 3.8 V

may apply.(1)

1.3 VIN UV Buck undervoltage lockout VIN rising. After a reset, initial start-up conditions 3.8 4 V

may apply.(1)

1.4 VBOOST_UNLOCK Boost unlock threshold VBAT rising 8.2 8.5 8.8 V

VIN = 13 V, BuckA: LPM, BuckB: off, TA= 25°C 34 46 µA

LPM quiescent current:

1.5 IQ_LPM VIN = 13 V, BuckB: LPM, BuckA: off, TA= 25°C

(2)

VIN = 13 V, BuckA, B: LPM, TA= 25°C 43 57 µA

VIN = 13 V, BuckA: LPM, BuckB: off, TA= 125°C 44 56 µA

LPM quiescent current:

1.6 IQ_LPM VIN = 13 V, BuckB: LPM, BuckA: off, TA= 125°C

(2)

VIN = 13 V, BuckA and BuckB: LPM, TA= 125°C 53 67 µA

SYNC = 5 V, TA= 25°C

VIN = 13 V, BuckA: CCM, BuckB: off, TA= 25°C 4.85 5.3

Quiescent current:

1.7 IQ_NRM mA

normal (PWM) mode(2) VIN = 13 V, BuckB: CCM, BuckA: off, TA= 25°C

VIN = 13 V, BuckA and BuckB: CCM, TA= 25°C 7 7.6

SYNC = 5 V, TA= 125°C

VIN = 13 V, BuckA: CCM, BuckB: off, TA= 125°C 5 5.5

Quiescent current:

1.8 IQ_NRM mA

normal (PWM) mode(2) VIN = 13 V, BuckB: CCM, BuckA: off, TA= 125°C

VIN = 13 V, BuckA, B: CCM, TA= 125°C 7.5 8

1.9 Ibat_sh Shutdown current BuckA and BuckB: off, VBat = 13 V , TA= 25°C 2.5 4 µA

1.10 Ibat_sh Shutdown current BuckA and BuckB: off, VBat = 13 V, TA= 125°C 3 5 µA

1.11 VINLPMexit VIN level to exit LPM VIN falling 7.7 8 8.3 V

1.12 VINLPMentry VIN level to enable entering LPM VIN rising 8.2 8.5 8.8 V

1.13 VINLPMhys Hysteresis VIN rising or falling 0.4 0.5 0.6 V

2.0 Input Voltage VBAT - Undervoltage Lockout

VBAT falling. After a reset, initial start-up conditions 1.8 1.9 2 V

may apply.(1)

2.1 VBATUV Boost-input undervoltage VBAT rising. After a reset, initial start-up conditions 2.4 2.5 2.6 V

may apply.(1)

2.2 UVLOHys Hysteresis 500 600 700 mV

2.3 UVLOfilter Filter time 5 µs

3.0 Input Voltage VIN - Overvoltage Lockout

VIN rising 45 46 47

3.1 VOVLO Overvoltage shutdown V

VIN falling 43 44 45

3.2 OVLOHys Hysteresis 1 2 3 V

3.3 OVLOfilter Filter time 5 µs

(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.

(2) Quiescent current specification includes the current in the internal-feedback resistor divider.

Product Folder Links: TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 to 18 V, TJ= –40°C to +150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

4.0 Boost Controller

4.1 Vboost7-VIN Boost VOUT = 7 V DIV = low, VBAT = 2 to 7 V 6.8 7 7.3 V

Boost-enable threshold Boost VOUT = 7 V, VBAT falling 7.5 8 8.5

4.2 Vboost7-th Boost-disable threshold Boost VOUT = 7 V, VBAT rising 8 8.5 9 V

Boost hysteresis Boost VOUT = 7 V, VBAT rising or falling 0.4 0.5 0.6

4.3 Vboost10-VIN Boost VOUT = 10 V DIV = open, VBAT = 2 to 10 V 9.7 10 10.4 V

Boost-enable threshold Boost VOUT = 10 V, VBAT falling 10.5 11 11.5

4.4 Vboost10-th Boost-disable threshold Boost VOUT = 10 V, VBAT rising 11 11.5 12 V

Boost hysteresis Boost VOUT = 10 V, VBAT rising or falling 0.4 0.5 0.6

4.5 Vboost8.85-VIN Boost VOUT = 8.85 V DIV = VREG, VBAT = 2 to 8.85 V 8.35 8.85 9.35 V

Boost-enable threshold Boost VOUT = 8.85 V, VBAT falling 9.15 9.85 10.45

4.6 Vboost8.85-th Boost-disable threshold Boost VOUT = 8.85 V, VBAT rising 9.65 10.35 10.85 V

Boost hysteresis Boost VOUT = 8.85 V, VBAT rising or falling 0.4 0.5 0.6

Boost-Switch Current Limit

4.7 VDS Current-limit sensing DS input with respect to PGNDA 0.175 0.2 0.225 V

4.8 tDS Leading-edge blanking 200 ns

Gate Driver for Boost Controller

4.9 IGC1 Peak Gate-driver peak current 1.5 A

4.10 rDS(on) Source and sink driver VREG = 5.8 V, IGC1 current = 200 mA 2 Ω

Gate Driver for PMOS

4.11 rDS(on) PMOS OFF 10 20 Ω

4.12 IPMOS_ON Gate current VIN = 13.5 V, Vgs = –5 V 10 mA

4.13 tdelay_ON Turnon delay C = 10 nF 5 10 µs

Boost-Controller Switching Frequency

4.14 fsw-Boost Boost switching frequency fSW_Buck / 2 kHz

4.15 DBoost Boost duty cycle 90%

Error Amplifier (OTA) for Boost Converters

VBAT = 12 V 0.8 1.35

4.16 GmBOOST Forward transconductance mS

VBAT = 5 V 0.35 0.65

5.0 Buck Controllers

Fixed output voltage in normal

5.1a VBuckA_NRM 3.345 3.396 3.447

Included resistor-feedback-divider, measured at

mode V

FBA pin

5.1b VBuckA_LPM Fixed output in low-power mode 3.311 3.396 3.481

Fixed output voltage in normal

5.2a VBuckB_NRM 1.216 1.235 1.253

mode Included resistor-feedback-divider, measured at V

FBB pin

Fixed output voltage in low-

5.2b VBuckB_LPM 1.204 1.235 1.266

power mode

V sense for forward-current limit Measured across Sx1 and Sx2, FBx at 94% of

5.4 60 75 90 mV

in CCM typical value (low duty-cycle)

Vsense V sense for reverse-current limit Measured across Sx1 and Sx2, FBx at 125% of

5.5 –65 –37.5 –23 mV

in CCM typical value

5.6 VI-Foldback V sense for output short Measured across Sx1 and Sx2, FBx = 0 V 17 32.5 48 mV

Shoot-through delay, blanking

5.7 tdead 20 ns

time

High-side minimum on-time 100 ns

5.8 DCNRM Maximum duty cycle (digitally 98.75%

controlled)

5.9 DCLPM Duty cycle, LPM 80%

Product Folder Links: TPS43337-Q1

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DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 to 18 V, TJ= –40°C to +150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LPM entry-threshold load current

ILPM_Entry as fraction of maximum set load 1% .(3)

current

5.10 LPM exit-threshold load current

ILPM_Exit as fraction of maximum set load (3) 10%

current

High-Side External NMOS Gate Drivers for Buck Controller

5.11 IGX1_peak Gate-driver peak current 1.5 A

5.12 rDS(on) Source and sink driver VREG = 5.8 V, IGX1 current = 200 mA 2 Ω

Low-Side NMOS Gate Drivers for Buck Controller

5.13 IGX2_peak Gate driver peak current 1.5 A

5.14 RDS ON Source and sink driver VREG = 5.8 V, IGX2 current = 200 mA 2 Ω

Error Amplifier (OTA) for Buck Converters

COMPA, COMPB = 0.8 V,

5.15 GmBUCK Transconductance 0.72 1 1.35 mS

source/sink = 5 µA, test in feedback loop

6.0 Digital Inputs: ENA, ENB, ENC, SYNC

6.1 VIH Higher threshold VIN = 13 V 1.7 V

6.2 VIL Lower threshold VIN = 13 V 0.7 V

6.3 RIH_SYNC Pulldown resistance on SYNC VSYNC = 5 V 500 kΩ

6.4 RIL_ENC Pulldown resistance on ENC VENC = 5 V 500 kΩ

Pullup current source on ENA,

6.5 IIL_ENx VENx = 0 V 0.5 2 µA

ENB

7.0 Boost Output Voltage: DIV

7.1 VIH_DIV Higher threshold VREG = 5.8 V Vreg – 0.2 V

7.2 VIL_DIV Lower threshold 0.2 V

7.3 Voz_DIV Voltage on DIV if unconnected Voltage on DIV if unconnected Vreg / 2 V

8.0 Switching Parameter – Buck DC-DC Controllers

8.1 fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz

8.2 fSW_Buck Buck switching frequency RT pin: 60-kΩexternal resistor 360 400 440 kHz

Buck adjustable range with

8.3 fSW_adj RT pin: external resistor 150 600 kHz

external resistor

8.4 fSYNC Buck synchronization range External clock input 150 600 kHz

9.0 Internal Gate-Driver Supply

Internal regulated supply VIN = 8 to 18 V, VEXTSUP = 0 V, SYNC = high 5.5 5.8 6.1 V

9.1 VREG IVREG = 0 to 100 mA, VEXTSUP = 0 V,

Load regulation 0.2% 1%

SYNC = high

Internal regulated supply VEXTSUP = 8.5 V 7.2 7.5 7.8 V

9.2 VREG(EXTSUP) IEXTSUP = 0 to 125 mA, SYNC = High

Load regulation 0.2% 1%

VEXTSUP = 8.5 to 13 V

EXTSUP switch-over voltage IVREG = 0 to 100 mA,

9.3 VEXTSUP-th 4.4 4.6 4.8 V

threshold VEXTSUP ramping positive

9.4 VEXTSUP-Hys EXTSUP switch-over hysteresis 150 250 mV

9.5 IREG-Limit Current limit on VREG VEXTSUP = 0 V, normal mode as well as LPM 100 400 mA

Current limit on VREG when IVREG = 0 to 100 mA,

9.6 IREG_EXTSUP-Limit 125 400 mA

using EXTSUP VEXTSUP = 8.5 V, SYNC = High

10.0 Soft Start

10.1 ISSx Soft-start source current VSSA and VSSB = 0 V 40 50 60 µA

11.0 Oscillator (RT)

11.1 VRT Oscillator reference voltage 1.2 V

(3) The exit threshold specification must always higher than the entry threshold.

Product Folder Links: TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 to 18 V, TJ= –40°C to +150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

12.0 Power Good / Delay

12.1a PGthA FBA falling 3.09 3.158 3.226

Power-good threshold V

12.1b PGthB FBB falling 1.124 1.148 1.173

12.2 PGhys Hysteresis 2%

12.3 PGdrop Voltage drop IPGA = 5 mA 450 mV

12.4 IPGA = 1 mA 100 mV

12.5 PGleak Power-good leakage Sx2 = PGx = 13 V 1 µA

12.6 tdeglitch Power-good deglitch time 2 16 µs

External capacitor = 1 nF

12.7 tdelay Reset delay 1 ms

VBUCKx < PGthx

12.8 tdelay_fix Fixed reset delay No external capacitor, pin open 20 50 µs

Activate current source (current

12.9 IOH 30 40 50 µA

to charge external capacitor)

Activate current sink (current to

12.10 IIL 30 40 50 µA

discharge external capacitor)

13.0 Overtemperature Protection

Junction-temperature shutdown

13.1 Tshutdown 150 165 °C

threshold

13.2 Thys Junction-temperature hysteresis 15 °C

Product Folder Links: TPS43337-Q1

19 20

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

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DEVICE INFORMATION

DAP PACKAGE

(TOP VIEW)

PIN FUNCTIONS

NAME NO. I/O DESCRIPTION

AGND 23 O Analog ground reference

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck

CBA 5 I controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the

high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck

CBB 34 I controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the

high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.

Error-amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the

COMPA 13 O target for the peak current through the inductor of BuckA. Clamping this voltage on the upper and lower ends

provides current-limit protection for the external MOSFETs.

Error-amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the

COMPB 26 O target for the peak current through the inductor of BuckB. Clamping this voltage on the upper and lower ends

provides current-limit protection for the external MOSFETs.

COMPC 18 O Error-amplifier output and loop-compensation node of the boost regulator

The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter

DIV 36 I at 8.85 V, a low input sets the value at 7 V, and a floating pin sets 10 V.

The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-

DLYAB 21 O good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 μs, typical.

This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An

DS 2 I alternative connection for better noise immunity is to place a sense resistor between the source of the low-side

MOSFET and ground via a filter network.

Enable inputs for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V

ENA 16 I enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and

ENB are low, the device shuts down and consumes less than 4 µA of current.

Product Folder Links: TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

PIN FUNCTIONS (continued)

NAME NO. I/O DESCRIPTION

Enable inputs for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V

ENB 17 I enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and

ENB are low, the device shuts down and consumes less than 4 µA of current.

This input enables and disables the boost regulator. An input voltage higher than 1.5 V enables the controller.

ENC 19 I Voltages lower than 0.7 V disable the controller. When enabled, the controller starts switching as soon as VBAT

falls below the boost threshold, depending upon the programmed output voltage.

One uses EXTSUP to supply the VREG regulator from one of the TPS43337-Q1 buck regulator rails to reduce

EXTSUP 37 I power dissipation in cases where there is an expectation of high VIN. When EXTSUP is open or lower than 4.6 V,

the regulator power comes from VIN.

Feedback voltage pin for BuckA. The buck controller regulates this feedback voltage to 3.4 V through the internal

FBA 12 I resistor-divider network. Connect FBA to the output voltage of BuckA.

Feedback voltage pin for BuckB. The buck controller regulates this feedback voltage to 1.235 V through the

FBB 27 I internal resistor-divider network. Connect FBB to the output voltage of BuckB.

This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high

GA1 6 O peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has

a voltage swing provided by CBA.

This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high

GA2 8 O peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.

This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high

GB1 33 O peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHB that has

a voltage swing provided by CBB.

This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high

GB2 31 O peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.

This output drives an external low-side N-channel MOSFET for the boost regulator. This output provides high

GC1 3 O peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.

This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET

GC2 4 O bypasses the boost rectifier diode or a reverse-protection diode when the boost status is non-switching or

disabled, and thus reduces power losses.

Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the

PGA 15 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or

VBAT drops below the respective undervoltage threshold.

Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the

PGB 24 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or

VBAT drops below the respective undervoltage threshold.

PGNDA 9 O Power-ground connection to the source of the low-side N-channel MOSFETs of BuckA.

PGNDB 30 O Power-ground connection to the source of the low-side N-channel MOSFETs of BuckB.

Switching terminal of buck regulator BuckA; provides a floating ground reference for the high-side MOSFET gate-

PHA 7 O driver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired.

Switching terminal of buck regulator BuckB; provides a floating ground reference for the high-side MOSFET gate-

PHB 32 O driver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired.

Connecting a resistor to ground on this pin sets the operating switching frequency of the buck and boost

RT 22 O controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz

for the boost controller.

SA1 10 I High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for

each buck controller. Choose the current-sense element to set the maximum current through the inductor based

on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle

SA2 11 I and VIN. (SA1 positive node, SA2 negative node)

SB1 29 I High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for

each buck controller. Choose the current-sense element to set the maximum current through the inductor based

on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle

SB2 28 I and VIN. (SB1 positive node, SB2 negative node)

Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of

0.8 V or the SSA pin voltage. An internal pullup current source of 50 μA is present at the pin. Connect an

SSA 14 O appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another

supply to provide a tracking input to this pin.

Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBA voltage to the lower of

0.8 V or the SSA pin voltage. An internal pullup current source of 50 μA is present at the pin. Connect an

SSB 25 O appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another

supply to provide a tracking input to this pin.

Product Folder Links: TPS43337-Q1

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

PIN FUNCTIONS (continued)

NAME NO. I/O DESCRIPTION

If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock.

This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600

SYNC 20 I kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits

transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power

mode at light loads.

Battery input sense for the boost controller. With the boost controller enabled, if the voltage at VBAT falls below

VBAT 1 I the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed

boost output voltage.

Main input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, VIN

VIN 38 I powers the internal control circuits of the device.

This pin requires an external capacitor to provide a regulated supply for the gate drivers of the buck and boost

VREG 35 O controllers. TI recommends a capacitance on the order of 4.7 μF. Either VIN or EXTSUP can power the regulator.

This pin has current-limit protection, so do not use it to drive any other loads.

Product Folder Links: TPS43337-Q1

VIN 38 Internal ref

(Band gap)

EXTSUP

Gate Driver

Supply

VREG 35

RT 22

SYNC 20

Internal

Oscillator

SYNC and

LPM

180 deg

Source

and

Sink

Logic

GC2

ENC

SSA

50 µA

VIN

500 nA

ENA

SSB

50 µA

ENB

VIN

500 nA

ENB

COMPC

VBAT

DIV

DS OCP

0.2 V

GC1

ENC

AGND

PWM

Logic

Duplicate for second

Buck controller channel

VREG

5CBA

6GA1

7PHA

8GA2

9PGNDA

Slope

Comp Current sense

Amp

PWM

comp

OTA

10 SA1

FBA

11 SA2

SSA

PGA

FBA

Filter Timer

DLYAB

40 µA

CBB

GB1

PHB

GB2

PGNDB

SB1

SB2

FBB

COMPB

PGB

Second

Buck

Controller

Channel

COMPA

0.8 V

OTA

VIN

VboostxV Gm

Vboost7V-th

Vboost8.85V-th

Vboost10V-th

MUX

VREG

PGNDA

Ramp

PWM

comp

PWM

Logic

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Figure 2. Functional Block Diagram

Product Folder Links: TPS43337-Q1

50 mV / DIV

IIND

0.2 A / DIV

100 s / DIV

VOUT BuckB - AC Coupled

50 mV / DIV

IIND

0.2 A / DIV

100 s / DIV

VOUT BuckB - AC Coupled

100 mV / DIV

IIND

1 A / DIV

1 ms / DIV

VOUT BuckB - AC Coupled

50 mV / DIV

IIND

1 A / DIV

1 ms / DIV

VOUT BuckA - AC Coupled

0.0001

0.001

0.01

0.1

100

1.00E-07 1.00E-05 1.00E-03 1.00E-01

Power Loss (W)

Efficiency (%)

I_Load (A)

Efficiency, SYNC=HIGH

Efficiency, SYNC=LOW

Power Loss, SYNC=HIGH

Power Loss, SYNC=LOW

C001

0.0001

0.001

0.01

0.1

100

1.00E-07 1.00E-05 1.00E-03 1.00E-01

Power Loss (W)

Efficiency (%)

I_Load (A)

Efficiency, SYNC=HIGH

Efficiency, SYNC=LOW

Power Loss, SYNC=HIGH

Power Loss, SYNC=LOW

C002

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

TYPICAL CHARACTERISTICS

BuckA EFFICIENCY AND POWER LOSSES BuckB EFFICIENCY AND POWER LOSSES

VIN = 12 V, Inductor = 10 µH, Rsense = 20 mΩ, Switching VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, Switching

Frequency = 400 kHz, EXTSUP open Frequency = 400 kHz, EXTSUP open

Figure 3. Figure 4.

BuckA LOAD STEP 1 A - 2 A BuckB LOAD STEP 1 A - 2 A

VIN = 12 V, Inductor = 10 µH, Rsense = 20 mΩ, COUT = 100 µF, VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, COUT = 320 µF,

Switching Frequency = 400 kHz Switching Frequency = 400 kHz

Figure 5. Figure 6.

BuckB LOAD STEP UP 0 A - 1 A BuckB LOAD STEP DOWN 1 A - 0 A

VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, COUT = 320 µF, VIN = 12 V, Inductor = 4.7 µH, Rsense = 10 mΩ, COUT = 320 µF,

Switching Frequency = 400 kHz Switching Frequency = 400 kHz

Figure 7. Figure 8.

Product Folder Links: TPS43337-Q1

0 A

0 V

20 ms/DIV

V (BOOST INPUT)

BAT

5 V/DIV

V (BOOST OUTPUT)

5 V/DIV

IIND

10 A/DIV

V (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,

BuckB = 3.3V AT 3.5A, SWITCHING FREQUENCY = 200 kHz,

INDUCTOR = 1 µH, R = 7.5 m , C = 440 µF, C = 660 µF

SENSE IN

WOUT

V (BOOST INPUT) = 5 V, V (BOOST OUTPUT) = 10 V,

SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,

R = 7.5 m , C = 440 µF, C = 660 µF

BAT IN

SENSE IN OUT

2 µs/DIV

3-A LOAD

5 A/DIV

100-mA LOAD

5 A/DIV

0 A

0 V

20 ms/DIV

V (BOOST INPUT)

BAT

5 V/DIV

V BuckA AC-COUPLED

OUT

200 mV/DIV

V BuckB AC-COUPLED

OUT

200 mV/DIV

IIND

10 A/DIV

V (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,

BuckB = 3.3 V AT 3.5 A, SWITCHING FREQUENCY = 200 kHz,

INDUCTOR = 1 µH, R = 7.5 m , C = 440 µF, C = 660 µF

SENSE IN OUT

2 ms/DIV

V (BOOST OUTPUT) AC-COUPLED

IIND

5 A/DIV

500 mV/DIV

V (BOOST INPUT) = 5 V, V (BOOST OUTPUT) = 10 V,

SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,

R = 7.5 m , C = 440 µF, C = 660 µF

BAT IN

SENSE IN OUT

Output Current (A)

Efficiency (%)

V (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz,

INDUCTOR = 1 µH, R = 7.5 m

SENSE W

0.01 110

100

V = 8 V

BAT

V = 5 V

BAT

V = 3 V

BAT

5 ms / DIV

VOUT BuckA, 1V / DIV

VOUT BuckB, 0.5 V / DIV

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

TYPICAL CHARACTERISTICS (continued)

SOFT-START OUTPUTS

BuckA and BuckB

Figure 9. Figure 10.

Figure 11. Figure 12.

Figure 13. Figure 14.

Product Folder Links: TPS43337-Q1

FOLDBACK CURRENT LIMIT (BUCK)

Normalized VOUT

Peak Current Sense Voltage (mV)

0 0.25 0.5 0.75 1

Duty Cycle (%)

Peak Current Sense Voltage (mV)

0 10 20 30 40 50 60 70 80 90 100

V = 8 V

V = 12 V

COMPx Voltage (V)

Peak Current Sense Voltage (mV)

SYNC = LOW

SYNC = HIGH

0.65 0.8 0.95 1.1 1.25 1.4 1.55

–37.5

–25

–12.5

12.5

37.5

62.5

Output Voltage (V)

Sense Current (µA)

01 2 34567 8 9 10 11 12

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

150°C

25°C

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Figure 15. Figure 16.

Figure 17. Figure 18.

Product Folder Links: TPS43337-Q1

I t

C (Farads)

´ D

f (X 24 k MHz)

f 24 RT

= = W ´

= ´

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

DETAILED DESCRIPTION

BUCK CONTROLLERS: NORMAL-MODE PWM OPERATION

Frequency Selection and External Synchronization

The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior

and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,

depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching

frequency to 400 kHz. the frequency is also set by a resistor at RT according to Equation 1.

(1)

For example,

600 kHz requires 40 kΩ.

150 kHz requires 160 kΩ.

Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 to 600 kHz is also

possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the

specified range. The device also detects a loss of clock at this pin, and on detecting this loss, the device sets the

switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies,

180 degrees out of phase.

Enable Inputs

Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,

with a threshold of 1.5 V for high level, and with direct connection directly to the battery for self-bias. The low

threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on

these pins enables the respective buck controllers. When both buck controllers are disabled, the device shuts

down and consumes a current less than 4 µA.

Feedback Inputs

An internal voltage divider presets the output voltage. Connect each FBx pin to the output of the respective

regulator of the pin.

Soft-Start Inputs

In order to avoid large inrush currents, each buck controller has an independent, programmable soft-start timer.

The voltage at the SSx pins acts as the soft-start reference voltage. A 50-µA pullup current available at the SSx

pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After

start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V; 0.8 V then

becomes the reference for the buck controllers. Equation 2 calculates the soft-start ramp time.

where,

• ISS = 50 µA (typical)

•∆V = 0.8 V

• CSS is the required capacitor for ∆t, the desired soft-start time. (2)

Alternatively, the soft-start pins are used as tracking inputs. In this case, connect these pins to the supply to be

tracked via a suitable resistor-divider network.

Product Folder Links: TPS43337-Q1

DCR

Inductor L

R11

C11

VBuckX

Sx2

Sx11

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

Current-Mode Operation

Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at the

set value. The error between the feedback voltage at FBx and the internal voltage divider produces a signal at

the output of the error amplifier (COMPx), which serves as the target for the peak inductor current. The device

senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares the voltage with this

target during each cycle. A fall or rise in load current produces a fall or rise in voltage at FBx, causing COMPx to

fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current

matches the load. This process maintains the output voltage in regulation.

The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current

reaches the peak value. When this MOSFET turns off, and after a small delay (shoot-through delay), the lower

N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET

stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the

bootstrap capacitor at CBx, which allows a maximum duty cycle of 98.75% for the buck regulators. During

dropout, the buck regulator switches at one-fourth of its normal frequency.

Current Sensing and Current Limit With Foldback

Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a

specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value

due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus

providing current foldback protection, which protects the high-side external MOSFET from excess current

(forward-direction current limit).

Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully

on, the COMPx node drops low. A clamp is on the lower end as well, in order to limit the maximum current in the

low-side MOSFET (reverse-direction current limit).

An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum

forward-peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified typical

value is for low duty cycles only. At typical duty-cycle conditions around 28% (assuming 3.4 V output and 12 V

input), 55 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics

(see Figure 18) provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range,

thus allowing DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 19 shows

DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter

components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,

it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.

Hence using the more-accurate sense resistor for current sensing is advantageous.

Figure 19. DCR Sensing Configuration

Product Folder Links: TPS43337-Q1

DELAY

DLYAB

t 1 msec

C 1 nF

L f

200

TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Slope Compensation

Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable

operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor

according to Equation 3.

where

• L is the buck regulator inductor in henries.

• RSis the sense resistor in ohms.

• fsw is the buck regulator switching frequency in hertz. (3)

Power-Good Outputs and Filter Delays

Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx

pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold

has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-

drain output at the PGx pins. Shutdown of a buck controller causes an internal pulldown of the power-good

indicator. Connecting the external pullup resistor to a rail other than the output of that particular buck channel

causes a constant current flow through the external resistor during a powered-down state of the buck controller.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the

device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value

after a long negative transient, assertiohn of the power-good indicator (release of the open-drain pin) occurs after

the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program

the delay of this circuit by using a suitable capacitor at the DLYAB pin according to Equation 4.

(4)

When the DLYAB pin is open, the delay is set to a default value of 20 µs (typical). The power-good delay timing

is common to both the buck rails, but the power-good comparators and indicators function independently.

Light-Load PFM Mode

An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks.

When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light

loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected.

In discontinuous mode, as the load decreases, the duration of the clock-period when both the high-side as well

the low-side MOSFET is turned-off, increases (deep discontinuous mode). In case the duration exceeds 60% of

the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design

ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have

been chosen appropriately as recommended in the Slope Compensation section.

In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8 V internal reference

voltage through the internal voltage divider. Whenever the FBx value falls below the internal threshold, the high-

side MOSFET is turned on for a pulse duration inversely proportional to the difference VIN – Sx2. At the end of

this on-time, the high-side MOSFET is turned off and the current in the inductor decays until it becomes zero.

The low-side MOSFET is not turned on. The next pulse occurs the next time FBx falls below the threshold value

which results in a constant volt-second ton hysteretic operation with a total-device quiescent-current consumption

of 34 µA when a single buck channel is active and 43 µA when both channels are active.

As the load increases, the pulses become more and more frequent and move closer to each other until the

current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency

current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher

than 80% duty cycle of the high-side MOSFET.

During low-power mode, the TPS43337-Q1 supports the full-current load until the transition to normal mode

takes place. The design ensures the low-power-mode exit occurs at 10% (typical) of full-load current if the

inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis

between the entry and exit thresholds to avoid oscillating between the two modes.

Product Folder Links: TPS43337-Q1

GC1

TPS43337-Q1

VIN

Vbat

RISEN

RIFLT

CIFLT

GC1

TPS43337-Q1

VIN

Vbat

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

In the event that both buck controllers are active, low-power mode is only possible when both buck controllers

have light loads that are low enough for entry into low-power mode. When the boost controller is enabled, low-

power mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set

to GND. If DIV is high (VREG), low-power mode is inhibited.

Boost Controller

The boost controller has a fixed-frequency voltage-mode architecture and includes a cycle-by-cycle current-limit

protection for the external N-channel MOSFET. The switching frequency is derived from and set to one-half of

the buck-controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an

internal resistor-divider network and is programmable to 7 V, 8.85 V, and 10 V based on the low, open, and high

status of the DIV pin, respectively. A change of the DIV setting is not recognized while the device is in low-power

mode.

The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin

has crossed the unlock threshold of 8.5 V at least once. After that, the boost controller is armed and starts

switching as soon as VIN falls below the value set by the DIV pin, and regulates the VIN voltage. Thus, the boost

regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking

pulse at VBAT.

Whenever the voltage at the DS pin exceeds 200 mV, the boost-external MOSFET is turned off by pulling the

CG1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET

source and ground, cycle-by-cycle overcurrent protection for the MOSFET can be achieved. The on-resistance of

the MOSFET or the value of the sense resistor must be chosen in such a way that the on-state voltage at DS

does not exceed 200 mV at the maximum load and minimum input-voltage conditions. When a sense resistor is

used, connecting a filter network between the DS pin and the sense resistor is recommended for better noise

immunity.

The boost output (VIN) is also used to supply other circuits in the system, however, they should be high-voltage

tolerant. The boost output is regulated to the programmed value only when VIN is low, and so VIN can reach

battery levels.

Figure 20. External Drain-Source Voltage Sensing

Figure 21. External Current Shunt Resistor

Product Folder Links: TPS43337-Q1

TPS43337-Q1

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SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Table 1. Mode Control

SYNC Comments

Terminal

External clock Device in forced into continuous mode, internal PLL locks into the external clock between 150 kHz and 600 kHz

Low or open Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions

High Device in forced into continuous mode

Table 2. Mode of Operation

ENABLE AND INHIBIT PINS DRIVER STATUS DEVICE STATUS QUIESCENT CURRENT

ENA ENB ENC SYNC BUCK CONTROLLERS BOOST CONTROLLER

Low Low Low X Shutdown Disabled Shutdown Approximately 4 µA

Low BuckB: LPM enabled Approximately 34 µA (light loads)

Low High Low BuckB running Disabled

High BuckB: LPM inhibited mA range

Low BuckA: LPM enabled Approximately 34 µA (light loads)

High Low Low BuckA running Disabled

High BuckA: LPM inhibited mA range

BuckA and BuckB: LPM

Low Approximately 43 µA (light loads)

enabled

BuckA and BuckB

High High Low Disabled

running BuckA and BuckB: LPM

High mA range

inhibited

Low Low Low X Shutdown Disabled Shutdown Approximately 4 µA

Approximately 54 µA (no boost,

Low BuckB: LPM enabled

Boost running for VIN < set light loads)

Low High High BuckB running boost output

High BuckB: LPM inhibited mA range

Approximately 54 µA (no boost,

Low BuckA: LPM enabled

Boost running for VIN < set light loads)

High Low High BuckA running boost output

High BuckA: LPM inhibited mA range

BuckA and BuckB: LPM Approximately 68 µA (no boost,

Low enabled light loads)

BuckA and BuckB Boost running for VIN < set

High High High running boost output BuckA and BuckB: LPM

High mA range

inhibited

Gate Driver Supply (VREG, EXTSUP)

The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output

(5.8 V, typical) is available at the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3

µF to 10 µF. This pin has internal current-limit protection and should not be used to power any other circuits.

The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V

(typical). In case VIN is expected to go to high levels, there can be excessive power dissipation in this regulator,

especially at high switching frequencies and when using large external MOSFETs. In this case, powering this

regulator from the EXTSUP pin is advantageous, which can be connected to a supply lower than VIN but high

enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear

regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are

possible when one of the switching regulator rails from the TPS43337-Q1 or any other voltage available in the

system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is 9 V.

Product Folder Links: TPS43337-Q1

C14

Fuse (S1)

C13

C15C17

C16

R10

TPS43337-Q1

GC2

VIN

GC1

COMPC

VBAT

Vbat

LDO

EXTSUP

LDO

VIN

VIN EXTSUP

VREG

typ 5.8 V typ 7.5 V

typ 4.6 V

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

Figure 22. Internal Gate-Driver Supply

Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous as it provides a large gate drive and

therefore better on-resistance of the external MOSFETs.

During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt

regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in

low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.

External P-Channel Drive (GC2) and Reverse Battery Protection

The TPS43337-Q1 includes a gate driver for an external P-channel MOSFET, which can be connected across

the rectifier diode of the boost regulator which is useful to reduce power losses when the boost controller is not

switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel

MOSFET. When VBAT falls below the boost enable threshold, the gate driver turns off the P-channel MOSFET,

and the diode is no longer bypassed.

The gate driver can also be used to bypass any additional protection diodes connected in series as shown in

Figure 23.Figure 24 also shows a different scheme of reverse battery protection which may require only a

smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching

cycle. Because the diode is not always in the series path, the system efficiency improves.

Figure 23. Reverse-Battery-Protection Option for Buck-Boost Configuration

Product Folder Links: TPS43337-Q1

TPS43337-Q1

GC2

VBAT

Fuse

VIN

GC1

COMPC

VBAT

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Figure 24. Reverse-Battery-Protection Option for Buck-Boost Configuration

Undervoltage Lockout and Overvoltage Protection

The TPS43337-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once

the has started up, it operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout

disables the device.

NOTE

If VIN drops, VREG drops as well, reducing the gate-drive voltage, while the digital logic

remains fully functional. Even if ENC is high, exceeding the boost-unlock voltage of

typically 8.5 V one time is required before boost activation takes place (see the Boost

Controller section).

A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent

transient spikes from shutting down the device, the undervoltage and overvoltage protection have filter times of 5

µs (typical).

When the voltages return to the normal-operating region, the enabled switching regulators start including a new

soft-start ramp for the buck regulators.

When the boost controller is enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage

lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN

falls at a rate dependent on the capacitor and load, eventually triggering VIN undervoltage. A short falling

transient at VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is

discharged to the undervoltage threshold.

Thermal Protection

The TPS43337-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die

temperature exceeds the thermal shutdown threshold of 165°C due to excessive power dissipation (for example,

due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned off, and

then restarted when the temperature has fallen by 15°C.

Product Folder Links: TPS43337-Q1

COMPx

VIN

VREF

8.85

10 V

C 1

C 2

RESR

OTA-gmEA

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

APPLICATION INFORMATION

The following example illustrates the design process and component selection for the TPS43337-Q1. The design

goal parameters are given in Table 3.

Table 3. Design Goal Parameters Example

PARAMETER VBUCKA VBUCKB BOOST

VIN 6 to 30 V VIN 6 to 30 V VBAT = 5 (cranking pulse

Input voltage 12 V - typical 12 V - typical input) to 30 V

Output voltage, VOUTx 3.396 V 1.235 V 10 V

Maximum output current, IOUTx 3 A 2 A 2.5 A

Load step output tolerance, ∆VOUT +±0.2 V ±0.12 V ±0.5 V

ΔVOUT(Ripple)

Current output load step, ∆IOUTx 0.1 to 3 A 0.1 to 2 A 0.1 to 2.5 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

This example is a starting point and theoretical representation of the values to be used for the application; further

optimization of the components derived may be required to improve the performance of the device.

Boost Component Selection

A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in the

transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to

the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the

bandwidth is too close to the RHP zero frequency, the regulator may become unstable.

Thus, for high-power systems with low input voltages, a low inductor value is chosen. This value increases the

amplitude of the ripple currents in the N-channel MOSFET, the inductor and the capacitors for the boost

regulator. They must be designed with the ripple/RHP zero trade-off in mind and considering the power

dissipation effects in the components due to parasitic series resistance.

A boost converter that operates in the discontinuous mode does not contain the RHP-zero in transfer function.

However, designing for the discontinuous mode demands an even lower inductor value that has high ripple

currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, the regulator

becomes unstable.

Figure 25. Boost Compensation Components

This design is done assuming continuous-conduction mode. During light load conditions, the boost converter

operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for

stability.

Product Folder Links: TPS43337-Q1

BAT min

RHP

In max

f 32 kHz

2 I L

= =

p ´ ´

SENSE

0.2 V

R 25 m

7.85 A

= = W

RIPPLE

PEAK INmax

I3.1 A

I I 6.3 A + 7.85 A

2 2

= + = =

BAT ON BAT

INripplemax INripple max SW

V t V5 V

L 4.9 H

I I 2 f 2.52 A 2 200 kHz

= = = m

´ ´ ´ ´

BAT

31.3 W

I (at V = 5 V) 6.3 A

INmax 5 V

= =

OUT

INmax

P25 W

P 31.3 W

Efficiency 0.8

= = =

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Boost Maximum Input Current IIN_MAX

The maximum input current is drawn at the minimum input voltage and maximum load. The efficiency for VBAT =

5 V at 2.3 A is 80%, based on the typical characteristics plot.

(5)

Hence,

(6)

Boost Inductor Selection, L

Allow input ripple current of 40% of IIN max at VBAT =5V

(7)

Choose a lower value of 3.9 µH in order to ensure a high RHP-zero frequency while making a compromise that

expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous

conduction mode, where it is easier to compensate.

The inductor saturation current must be higher than the peak inductor current and some percentage higher than

the maximum current-limit value set by the external resistive sensing element.

This rating should be determined at the minimum input voltage, maximum output current, and maximum core

temperature for the application.

Inductor Ripple Current, IRIPPLE

Based on an Inductor value of 3.9 µH, the ripple current is approximately 3.1 A.

Peak Current in Low-Side FET, IPEAK

(8)

Based on this peak current value (see Equation 8), the external current-sense resistor RSENSE is calculated in .

Select 20 mΩ, allowing for tolerance.

The filter component values RIFLT and CIFLT for current sense are 1.5 kΩand 1 nF, respectively, which allows for

good noise immunity.

Right Half-Plane Zero RHP Frequency, fRHP

(9)

Product Folder Links: TPS43337-Q1

ESR

ESR ESR

OUTx ESR

OUTx

f Hz, assume 40 m

2 C R

f 6 kHz

2 680 F 0.04

1 1

f 3.1 kHz

2 L C 2 4 H 680 F

R= = W

p ´ ´

= =

p ´ m ´

= = =

p ´ ´ p ´ m ´ m

RHP

BAT min

INmax

OUTx

INmax

OUTx

BAT min

OUTx min

2 I L

2 L C

C L 3.9 H

C 635 F

10 I 10 6.3 A

V 5 V

£p ´ ´

p ´ ´

³ ´ = ´ m

³ m

æ ö æ ö

ç ÷ ç ÷

è ø

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

Output Capacitor, CO

To ensure stability, the output capacitor COis chosen such that

(10)

Select COUTx = 680 µF.

This capacitor is usually aluminum electrolytic with ESR in the tens-of-milliohms which is good for loop stability,

because it provides a phase boost due to the ESR. The output filter components L and C create a double pole

(180 degree phase-shift) at a frequency fLC, and the ESR of the output capacitor RESR creates a zero for the

modulator at frequency fESR. These frequencies can be determined by Equation 11.

(11)

This satisfies fLC ≤0.1 fRHP.

Bandwidth of Boost Converter, fC

Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between

stability and transient response:

fLC < fESR< fC< fRHP Zero

fC< fRHP Zero / 3

fC< fSW / 6

fLC < fC/ 3

Product Folder Links: TPS43337-Q1

RIPPLE

SW IN

RIPPLE

SW C1

ESR RIPPLE ESR

V 10 mV

8 f C

C 194-μF

8 f V

V I R 40 mV

D = =

´ ´

= =

´ ´ D

D = ´ =

G/20

OUTx

R3 7.2 k

85 10 V

10 10

C1 22 nF

2 f R3 2 10 kHz 7.2 k

C1 22 nF

C2 223 pF choose 220 pF

2 7.2 k 22nF 1

2 R3 C1 1

A / V

f 200 kHz

= = W

´ ´

= = =

p ´ ´ p ´ ´ W

= = =

p ´ W ´ ´ -

p ´ ´ ´ -

æ ö æ ö

ç ÷

ç ÷ è ø

è ø

C C

LC ESR

f f

G 40 log 20 log

f f

10 kHz 10 kHz

G 40 log 20 log 15.9 dB

3.1kHz 6 kHz

= -

= - =

æ ö æ ö

ç ÷ ç ÷

è ø è ø

æ ö æ ö

ç ÷ ç ÷

è ø è ø

OUTx

OUTx ESR OUTx

V R I

4 C f

2.5 A

0.04 2.5 A 0.19 V

4 660 F 10 kHz

D = ´ D + ´ ´

= W ´ + =

´ m ´

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Output Ripple Voltage Due to Load Transients, ∆VO

Assume a bandwidth of fC= 10 kHz.

(12)

Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters

are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,

smaller component choices for the boost output may be used.

Selection of Components for Type II Compensation

The required loop gain for unity gain bandwidth (UGB) is shown in Equation 13.

(13)

The boost converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage which allows a

constant loop response across the input voltage range and makes it easier to compensate by removing the

dependency on VBAT.

(14)

Input Capacitor, CIN

The input ripple required is lower than 50 mV.

(15)

Therefore, TI recommends 220 µF with 10-mΩESR.

Product Folder Links: TPS43337-Q1

SENSE

55 mV

R 18 m

3 A

= = W

ON min

IN max SW

V3.4 V

t 283 ns

V f 30 V 400 kHz

= = =

´ ´

I Pk

BOOSTFET Pk DS(on) r f sw

I Pk

BOOSTFET

P (I ) r (1 TC) D (t t ) f

P (7.85 A) 0.02 (1 0.4) 0.53 (20 ns 20 ns) 200 kHz 1.07 W

V I

= ´ + ´ + ´ + ´

= ´ W ´ + ´ + ´ + ´ =

æ ö

ç ÷

è ø

æ ö

ç ÷

è ø

D D(PEAK ) F

INMIN

OUT F

P I V (1 D)

P 7.85 A 0.6 V (1 0.53) 2.2 W

V5V

D 1 1 0.53

V V 10V 0.6V

= ´ ´ -

= ´ ´ - =

= - = - =

+ +

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

Output Schottky Diode D1 Selection

A Schottky diode with low forward-conducting voltage VFover temperature and fast switching characteristics is

required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input

voltage, and the component should have low reverse-leakage current. Additionally, the peak forward current

should be higher than the peak inductor current. The power dissipation in the Schottky diode is given in

Equation 16.

(16)

Low-Side MOSFET (BOT_SW3)

(17)

The times trand tfdenote the rising and falling times of the switching node and are related to the gate-driver

strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction

losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the

transition losses which arise due to the full application of the input voltage across the drain-source of the

MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large

input peak current) and when the switching time is low.

NOTE: The on-resistance rDS(on) has a positive temperature coefficient, which produces the (TC = d × ΔT) term

that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from

MOSFET data sheets and can be assumed to be 0.005 / ºC as a starting value.)

BuckA Component Selection

Minimum ON Time, tON min

(18)

As shown in Equation 18, tON min is higher than the minimum duty cycle specified (100 ns, typical). Hence the

minimum duty cycle is achievable at this frequency.

Current-Sense Resistor RSENSE

Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 70

mV (at VIN = 12 V and duty cycle of 3.4 V / 12 V = 0.283). Allowing for tolerances and ripple currents, choose

VSENSE maximum of 55 mV.

Select 18 mΩ.

Product Folder Links: TPS43337-Q1

OUTA

OUTA OUTA

C OUTA

I2.9 A

V I ESR 2.9 A 10 m 174 mV

4 f C 4 50 kHz 100 F

D = + D ´ = + ´ W =

´ ´ ´ ´ m

OUTA(Ripple)

OUTA(Ripple) OUTA(Ripple)

SW OUTA

I1 A

V I ESR 1 A 10 m 13.1mV

8 f C 8 400 kHz 100 F

= + ´ = + ´ W =

´ ´ ´ ´ m

OUTA

SW OUTA

2 I 2 2.9 A

C 72.5 F

f V 400 kHz 0.2 V

´ D ´

» = = m

´ D ´

SENSE

FLR

R18 m

L K 200 9.2 H

f 400 kHz

= ´ = ´ = m

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Inductor Selection L

As explained in the description of the buck controllers (see Detailed Description), for optimal slope compensation

and loop response, the inductor should be chosen such that:

• KFLR = Coil selection constant = 200 (19)

Choose a standard value of 10 µH. For the buck converter, the inductor saturation currents and core should be

chosen to sustain the maximum currents.

Inductor Ripple Current IRIPPLE

At the nominal input voltage of 12 V, this gives a ripple current of 25% of IOUTmax ≈1 A.

Output Capacitor CO

Select an output capacitance COof 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈15 mV

and ∆V drop of ≈180 mV during a load step, which does not trigger the power-good comparator and is within the

required limits.

(20)

(21)

(22)

Bandwidth of Buck Converter fC

Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between

stability and transient response.

• Crossover frequency fCbetween fSW / 6 and fSW / 10. Assume fC= 50 kHz.

• Select the zero fz≈fC/ 10

• Make the second pole fP2 ≈fSW / 2

Product Folder Links: TPS43337-Q1

1 1

f2 R3 C2 2 18 k 47 pF 188 kHz=

p ´ ´ p ´ W ´

= =

1 1

2 R3 C1 2 18 k 1.8 nF

4.9 kHz=

p ´ ´ p ´ W ´

= =

BUCK CFB REF

OUTA OUT

Gm R3 K V

f2 C V

1mS 18 k 6.9 S 0.8 V

f 46.5 kHz

2 100 μF 3.4 V

´ ´

= ´

p ´

´ W ´ ´

= =

p ´ ´

C1 1.8 nF

C2 45 pF

2 18 k 1.8 nF 1

2 R3 C1 1

f 400 kHz

= = =

p ´ W ´ -

p ´ ´ -

æ ö æ ö

ç ÷

ç ÷ è ø

è ø

C OUTA OUTA

BUCK CFB REF BUCK CFB REF

2 f V C 2 50 kHz 3.4 V 100 F

R3 19 k

Gm K V Gm K V

p ´ ´ ´ p ´ ´ ´ m

= = = W

´ ´ ´ ´

VREF

RLCOMP

Type 2A

GmBUCK

RESR

VOUT

COUT

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

Selection of Components for Type II Compensation

Figure 26. Buck Compensation Components

Use standard value of R3 = 18 kΩ

where:

• VO= 3.4 V

• CO= 100 µF

• Gm = 1 mS

• VREF = 0.8 V

• KCFB = 0.125 / RSENSE = 6.9 (0.125 is an internal constant) (23)

(24)

Use standard value of 1.8 nF.

(25)

Use standard value of 47 pF.

The resulting bandwidth of buck converter fC

(26)

fCis close to the target bandwidth of 50 kHz.

The resulting zero frequency fZ1

(27)

fZ1 is close to the fC/ 10 guideline of 5 kHz

The second pole frequency fP2

(28)

Product Folder Links: TPS43337-Q1

BUCK CFB REF

OUTB

Gm R3 K V

2 C V

1 mS 12 k 4.16 0.8

f 51.5 kHz

2 100 F 1.235 V

´ ´

=p ´

´ W ´ ´

= =

p ´ m ´

2 R3 C1

2.7 nF 68 pF, choose 68 pF

2 12 k 2.7 nF

400 kHz 1

p ´ ´ ´

= =

p ´ W ´ ´

æ ö -

ç ÷

è ø

æ ö -

ç ÷

è ø

10 10

C1 2.7 nF, choose 2.7nF

2 R3 f 2 12 k 50 kHz

= = =

p ´ ´ p ´ W ´

C OUTB OUTB

BUCK CFB REF

2 f V C

Gm K V

2 50 kHz 1.235 V 100 F

1 mS 4.16S 0.8V

11.7 k

p ´ ´ ´

=´ ´

p ´ ´ ´ m

´ ´

= = W

OUTB

OUTB OUTB

C OUTB

I1.9 A

V I ESR 1.9 A 10 m 114 mV

4 f C 4 50 kHz 100 F

D = + D ´ = + ´ W =

´ ´ ´ ´ m

OUTB(Ripple)

OUTB(Ripple) OUTB(Ripple)

SW OUTB

I0.4 A

V I ESR 0.4 A 10 m 5.3 mV

8 f C 8 400 kHz 100 F

= + ´ = + ´ W =

´ ´ ´ ´ m

OUTB

SW OUTB

2 I 2 1.9 A

C 46 F

f V 400 kHz 0.12 V

´ D ´

» = = m

´ D ´

SENSE

60 mV

L 200

400 kHz

30 m

m15 H

= ´

= W

W= m

OUTB

ON min

IN max SW

V1.235 V

t 103 ns

V f 30 V 400 kHz

= = =

´ ´

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied.

BuckB Component Selection

Using the same method as VBUCKA, the following parameters and components are realized in Equation 29.

(29)

This tONmin is on the edge of the minimum duty cycle specified (100 ns, typical); expect pulse-skipping at high VIN.

choose 30 mΩ, 15 µH.

•∆Iripple current ≈0.4 A (approx. 20% of IO max)

Select an output capacitance COof 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(ripple) ≈7.5 mV

and ∆V drop of ≈120 mV during a load step.

Assume fC= 50 kHz.

(30)

(31)

(32)

(33)

Use standard value of R3 = 12 kΩ.

(34)

(35)

(36)

fCis close to the target bandwidth of 50 kHz.

Product Folder Links: TPS43337-Q1

BuckLOWERFET OUT DS(on) F OUT d SW

P (I ) r (1 TC) (1 D) V I (2 t ) f= ´ + ´ - + ´ ´ ´ ´

2IN OUT

BuckTOPFET OUT DS(on) r f SW

V I

P (I ) r (1 TC) D (t t ) f

æ ö

= ´ + ´ + ´ + ´

ç ÷

è ø

1 1

f2 R3 C2 2 12k 68 pF 195 kHz=

p ´ ´ p ´ W ´

= =

1 1

f 4.9 kHz

2 R3 C1 2 12 k 2.7 nF

= = =

p ´ ´ p ´ W ´

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

The resulting zero frequency fZ1

fZ1 is close to the fC/ 10 guideline of 5 kHz.

The second pole frequency fP2

(37)

fP2 is close to the fSW / 2 guideline of 200 kHz.

Hence, all requirements for a good loop response are satisfied.

BuckX High-Side and Low-Side N-Channel MOSFETs

The gate-drive supply for these MOSFETs is supplied by an internal supply which is 5.8 V (typical) under normal

operating conditions. The output is a totem pole, allowing full voltage drive of VREG to the gate with peak output

current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx) and the

low-side MOSFET is referenced to the power ground (PGx) terminal. For a particular application, these

MOSFETs should be selected with consideration for the following parameters: rds(on), gate charge Qg, drain-to-

source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.

The times trand tfdenote the rising and falling times of the switching node and are related to the gate-driver

strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction

losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the

transition losses, which arise due to the full application of the input voltage across the drain-source of the

MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.

(38)

(39)

In addition, during the dead time tdwhen both the MOSFETs are off, the body diode of the low-side MOSFET

conducts, increasing the losses which is denoted by the second term in the Equation 39. Using external Schottky

diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.

Note that rDS(on) has a positive temperature coefficient which is accounted for in the TC term for rDS(on), TC = d ×

ΔT[°C]. The temperature coefficient, d, is available as a normalized value from MOSFET data sheets and can be

assumed to be 0.005 / ºC as a starting value.

Product Folder Links: TPS43337-Q1

VBAT

TPS43337-Q1

5 V to 30 V

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

3.9 µH

0.1 µF

0.1µF

500 nF

1 nF

5k Ω5k Ω

100 µF

COUTB

15 µH

0.03 Ω V—1.235 V, 2 W

BuckB

10 µH

10µF 680 µF

COUT1

100µF

COUTA

V—3.4 V, 10.2 W

BuckA 0.018 Ω

7.2 kΩ

22 nF

220 pF

18 kΩ

1.8 nF

47 pF 12 kΩ 2.7 nF 68 pF

TOP-SW1

BOT-SW1 BOT-SW2

TOP-SW2

TOP-SW3

BOT-SW3

220 µF

1kΩ

L2 L3

0.025Ω

BOOST —10V, 25W

1.5 kΩ

1nF

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

Schematic

The following section summarizes the previously calculated example and gives a schematic and component

proposals.

Table 4. Application Example

PARAMETER VBUCKA VBUCKB BOOST

VIN = 6 to 30 V VIN = 6 to 30 V VBAT = 5 (cranking pulse

Input voltage 12 V - typical 12 V - typical input) to 30 V

Output voltage, VOUTx 3.396 V 1.235 V 10 V

Maximum output current, IOUTx 3 A 2 A 2.5 A

Load-step output tolerance, ∆VOUT +ΔVOUT(Ripple) ±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IOUTx 0.1 to 3 A 0.1 to 2 A 0.1 to 2.5 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

Figure 27. Schematic - Application Example

Table 5. Application Example - Component Proposals

Name Component Proposal Value

L1 MSS1278T-392NL (Coilcraft) 3.9 µH

L2 MSS1278T-103ML (Coilcraft) 10 µH

L3 MSS1278T-153ML (Coilcraft) 15 µH

D1 SK103 (Micro Commercial Components)

TOP_SW3 IRF7416 (International Rectifier)

TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW3 IRFR3504ZTRPBF (International Rectifier)

COUT1 EEVFK1J681M (Panasonic) 680 µF

COUTA, COUTB ECASD91A107M010K00 (Murata) 100 µF

CIN EEVFK1J221Q (Panasonic) 220 µF

Product Folder Links: TPS43337-Q1

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

Power Dissipation Derating Profile, 38-Pin HTTSOP Package With PowerPAD Package

Figure 28. Power Dissipation Derating Profile Based on High-K JEDEC PCB

PCB Layout Guidelines

Grounding and PCB Circuit Layout Considerations

Boost Converter

1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense

resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to

the Schottky diode D1 to the COUT1 capacitors. The negative terminal of the input capacitor and the

negative terminal of the sense resistor must be connected together with short trace lengths.

2. The overcurrent-sensing shunt resistor may require noise filtering, and this capacitor should be close to the

IC pin.

Buck Converter

1. Connect the drains of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor

COUT1. The trace length between these terminals should be short.

2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.

3. The Kelvin-current sensing traces for the shunt resistor should have minimum trace spacing and be routed

parallel to each other. Any filtering capacitors for noise should be placed near the IC pins.

4. Connect the positive terminal of the respective output capacitor COUTA or COUTB to the respective feedback

input FBA or FBB. Do not connect these traces near any switching nodes or high-current traces.

Other Considerations

1. PGNDx and AGND should be shorted to the thermal pad. Use a star-ground configuration if connecting to a

non-ground-plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and

voltage-sense-feedback ground networks to this star ground.

2. Connect a compensation network between the compensation pins and IC signal ground. Connect the

oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits

should not be located near nodes showing high dv/dt; these include the gate-drive outputs, phase pins, and

boost circuits (bootstrap).

3. Reduce the surface area of the high-current-carrying loops to a minimum, by ensuring optimal component

placement. Ensure the bypass capacitors are located as close as possible to their respective power and

ground pins.

Product Folder Links: TPS43337-Q1

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC

V IN

EXTSUP

D IV

VREG

CBB

GB1

PHB

GB2

PGNDB

SB1

SB2

FBB

COMPB

SSB

PGB

AGND

DLYAB

SYNC

VBUCKA

VBUCKB

POW ER

INPUT

VBOOST

Exposed Pad

connec ted to GND

P lane

M ic rocon tro lle r

Powe r L ines

Connec tion to GND P lane o fPCB th rough v ias

Connec tion to top /bo ttom o f PCB th rough v ias

Vo ltage R a ilO u tpu ts

TPS43337-Q1

www.ti.com

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

PCB Layout

Product Folder Links: TPS43337-Q1

TPS43337-Q1

SLVSBC2A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com

REVISION HISTORY

Changes from Original (August 2013) to Revision A Page

• Changed document status from Product Preview to Production Data ................................................................................. 1

Product Folder Links: TPS43337-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 10-Sep-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS43337QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS43337

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS43337QDAPRQ1 HTSSOP DAP 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Dec-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS43337QDAPRQ1 HTSSOP DAP 38 2000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Dec-2017

Pack Materials-Page 2

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TPS43337QDAPRQ1