wn ee microelectronics group Lucent Technologies Bell Labs Innovations DSP16210 Digital Signal Processor Mm The DSP16210 is the first DSP device based Fon the DSP16000 digital signal processing core. It is manufactured in a 0.35 um CMOS technology and offers a 10 ns instruction cycle time at 3 V operation. Designed specifically for applications requiring a large amount of memory, a flexible DMA-based H/O structure, and high cycle efficiency in digital cellular infrastructure systems, the DSP16210 is a sig- nal-coding device that can be programmed to perform a wide variety of fixed-point signal processing functions. The DSP 16210 includes a mix of peripherals specifically intended to support processing-intensive but cost-sensitive applications in the area of digital wireless communications. The large, on-chip RAM (60 Kwords of dual-port RAM) supports downloadable system designa must for wireless infrastructureto support field upgrades for evolving digital cellular standards. The DSP 16210 can address 60 Kwords of DPRAM and up to 512 Kwords of external storage in both its codelcoefficient memory address space and data memory address space. In addition, there are 8 Kwords of internal ROM (ITROM) which includes system boot code and hardware development system (HDS) code. The external memory interface (EMI) has both 16- and 32-bit data width capabilities and is designed to support both static RAMs and the new synchronous static RAMs. This device also contains a bit manipulation unit (BMU) and a 3-input, 40-bit arithmetic logic unit (ALU) with addicomparelselect (ACS) for enhanced signal coding efficiency and Viterbi acceleration. To optimize I/O throughput and reduce the I/O service routine burden on the DSP core, the DSP 16210 is equipped with two modular I!O units (MIOUs) which manage the simple serial I/O port (SSIO) and the 16-bit parallel host interface (PHIF 16) peripherals. The MIOUs optimize I/O throughput and reduce the I/O service routine burden on the core by providing transparent DMA transfers between the peripherals and the on-chip, duat-port RAM. The combination of large on-chip RAM, fast instruction cycle times, and efficient I/O management makes the DSP 16210 an ideal solution for supporting multiple channels of voice and data traffic in digital cellular infrastructure equipment. FEATURES @ Optimized for digital cellular infrastructure applications speech coding, speech compression, and channel coding Large, on-chip, dual-port RAM (G0 Kwords of DPRAM) eliminates need for fast external SRAM 3-input, 40-bit arithmetic logic unit (ALU) with add/compare/ select (ACS) for Viterbi acceleration DMA-based 1/Ominimizes DSP core overhead for [/O processing Bit manipulation unit for higher coding efficiency Flexible power management modes @ 10 ns instruction cycle time at 3 V @ Dual 16x 16-bit multiplication and 40-bit accumulation in one instruction cycle @ 31 instruction by 32-bit interruptible do-loop cache for high-speed, program- efficient, zero-overhead looping m Nested interrupts and three interrupt priority levels m 32-bit sequenced accesses to 512 Kword external instruction/coefficient space (X memory) and 512 Kwords external data space (Y memory) m 8 Kwords of on-chip ROM with hardware development system and boot code for flexible downloading @ 512 internal and 512 external memory- mapped I/O ports # On-chip, programmable, PLL clock synthesizer @ Enhanced serial I/O port designed to multiplex/demultiplex 64 Kbits/s, 32 Kbits/s, 16 Kbits/s, and 8 Kbits/s channels m Two dedicated DMA controllers (MIOUs) to off-load I/O processing from DSP core a 25 Mbits/s simple serial 1/O port (SSIO) coupled with MIOU1 to sup- port low overhead DMA-based I/O @ 16-bit parallel host interface (PHIF16) coupled with MIOUO to support low overhead DMA-based I/O Supports either 8- or 16-bit external bus configurations (8-bit external configuration supports either 8- or 16-bit logical transfers) Supports either Motorola* or Intel protocols m 8-bit control I/O interface m /EEEF P1149.1 test port TAG boundary scan) @ Full-speed in-circuit emulation hardware development system on-chip with eight address and two data watchpoint units DSP16210 Block Diagram Pt tt DB[15.0] AB[15.0] EXM EROM ERAMHI ERAM ERAMLO IO RWN READY | t m Supported by DSP16210 software and hardware development tools @ Pin and object-code compatible with the DSP1620 m@ 132-pin BOFP package and 144-pin TQFP package 4 i | loc EXTERNAL MEMORY INTERFACE | td + _. =") puat-rort Rom ff 7 RAM [aes |p eae YAB YDB XDB XAB JTAG BOUNDARY SCAN!) [nr tr TBO |. TO} cKl " CKO FP = = - TCK RSTB--_}.-__--__> JCON <-__-__--___--_}- _ Tws STOP--}-> 10" TRST TRAP }----__+ BYPASS" JiMERO | [. OSP16000 CORE |. | INT[3:0] -----+ aS Tt isck an ine I M XDB YDB YAB IDB TRACE" TIMER} opriav, ot} u 1 VEC) x tt | <> BIO Ly wee] E510 $OBIT[3:0] J- > (cut es | U IDMX EDI | | | x icsb | ElFS | icst <4 EIBC ! icvv Sst0 a | OMX. EDO py-L..| [sae | ocsb__ || Eors cK ' i PHIF16 ocst | ~ EOBC lp SSDK(ny" ORAM | [iORAMO ocr EOEB IBF 1K x16 IK x16 ocvw t-1--> EOBE po ssoxioury iif _ Lestat Jf + PB[15-0] ee | . OCK< > MIOUt MIOUO -~_ | PSTAT ou ros oe PosN DOEN | p Lppx(ouns }}~_ = pe, SYNC [more] morpo <- _____|. pips |__|. PIBE ----} + PoBE These registers are accessible through the attached MIOU only. These registers are accessible through the pins only. * Motorola is @ registered trademark of Motorala, Inc. Tt Intel is @ registered trademark of Intel Corp. + IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers. For additional information, contact your Microelectronics Group Account Manager or the following: Microelectronics, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) INTERNET: http:/Avww.lucent.com/micro E-MAIL: docmaster @ micro.lucent.com U.S.A.: ASIA PACIFIC: Tel. (65) 778-8833, FAX (65) 777-7495 JAPAN: Tel. (81) 3-5421-1600, FAX (81) 3-5421-1700 EUROPE: Microelectronics Asia/Pacific, Lucent Technologies Inc., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Microelectronics, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan For data requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 For technical inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (388) 9 4354 2800 (Helsinki), ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) aor information. Copyright 1997 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. August 1997 OT97-347WDSP &% Printed On Recycled Paper microelectronics group Lucent Technologies Bell Labs Innovations