© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 2
1Publication Order Number:
NLSV2T244/D
NLSV2T244
2-Bit Dual-Supply
Non-Inverting Level
Translator
The NLSV2T244 is a 2−bit configurable dual−supply voltage level
translator. The input An and output Bn ports are designed to track two
different power supply rails, VCCA and VCCB respectively. Both
supply rails are configurable from 0.9 V to 4.5 V allowing universal
low−voltage translation from the input An to the output Bn port.
Features
•Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V
•High−Speed w/ Balanced Propagation Delay
•Inputs and Outputs have OVT Protection to 4.5 V
•Non−preferential VCCA and VCCB Sequencing
•Outputs at 3−State until Active VCC is Reached
•Power−Off Protection
•Outputs Switch to 3−State with VCCB at GND
•Small Packaging: UDFN8, SO−8, Micro8
•This is a Pb−Free Device
Typical Applications
•Mobile Phones, PDAs, Other Portable Devices
Important Information
•ESD Protection for All Pins:
HBM (Human Body Model) > 5000 V
UDFN8
MU SUFFIX
CASE 517AJ
MARKING
DIAGRAMS
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Device Package Shipping†
ORDERING INFORMATION
NLSV2T244MUTAG UDFN8
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
8
UP = Specific Device Code
M = Date Code
G= Pb−Free Package
UPM
G
1
8
SO−8
D SUFFIX
CASE 751
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
2T244
ALYW G
G
1
8
Micro8
DM SUFFIX
CASE 846A
1
244
AYW G
G
1
8
NLSV2T244DR2G SO−8
(Pb−Free)
2500/Tape & Reel
NLSV2T244DMR2G Micro8
(Pb−Free)
4000/Tape & Reel
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
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2
Figure 1. Logic Diagram
VCCA VCCB
B1
B2
OE
A2
A1
PIN ASSIGNMENTS
UDFN8
(Top View)
VCCB
B1
B2
GND
VCCA
A1
A2
OE
8
7
6
5
1
2
3
4
Micro8
(Top View)
1
2
3
4
8
7
6
5
1 8
2
3
4
7
6
5
SOIC−8
(Top View)
VCCB
B1
B2
GND
VCCA
A1
A2
OE
VCCB
B1
B2
GND
VCCA
A1
A2
OE
PIN ASSIGNMENT
PIN FUNCTION
VCCA Input Port DC Power Supply
VCCB Output Port DC Power Supply
GND Ground
AnInput Port
BnOutput Port
OE Output Enable
Inputs Outputs
OE AnBn
TRUTH TABLE
LLL
LHH
HX3−State
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3
MAXIMUM RATINGS
Symbol Rating Value Condition Unit
VCCA, VCCB DC Supply Voltage −0.5 to +5.5 V
VIDC Input Voltage An−0.5 to +5.5 V
VCControl Input OE −0.5 to +5.5 V
VODC Output Voltage (Power Down) Bn−0.5 to +5.5 VCCA = VCCB = 0 V
(Active Mode) Bn−0.5 to +5.5 V
(Tri−State Mode) Bn−0.5 to +5.5 V
IIK DC Input Diode Current −20 VI < GND mA
IOK DC Output Diode Current −50 VO < GND mA
IODC Output Source/Sink Current ±50 mA
ICCA, ICCB DC Supply Current Per Supply Pin ±100 mA
IGND DC Ground Current per Ground Pin ±100 mA
TSTG Storage Temperature −65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCCA, VCCB Positive DC Supply Voltage 0.9 4.5 V
VIBus Input Voltage GND 4.5 V
VCControl Input OE GND 4.5 V
VIO Bus Output Voltage (Power Down Mode) BnGND 4.5 V
(Active Mode) BnGND VCCB V
(Tri−State Mode) BnGND 4.5 V
TAOperating Temperature Range −40 +85 °C
Dt / DVInput Transition Rise or Rate
VI, from 30% to 70% of VCC; VCC = 3.3 V ±0.3 V
0 10 nS
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DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions VCCA (V) VCCB (V)
−405C to +855C
Unit
Min Max
VIH Input HIGH Voltage
(An, OE)
3.6 – 4.5 0.9 – 4.5 2.2 −V
2.7 – 3.6 2.0 −
2.3 – 2.7 1.6 −
1.4 − 2.3 0.65 * VCCA −
0.9 – 1.4 0.9 * VCCA −
VIL Input LOW Voltage
(An, OE)
3.6 – 4.5 0.9 – 4.5 −0.8 V
2.7 – 3.6 −0.8
2.3 – 2.7 −0.7
1.4 − 2.3 −0.35 * VCCA
0.9 – 1.4 −0.1 * VCCA
VOH Output HIGH Voltage IOH = −100 mA; VI = VIH 0.9 – 4.5 0.9 – 4.5 VCCB – 0.2 −V
IOH = −0.5 mA; VI = VIH 0.9 0.9 0.75 * VCCB −
IOH = −2 mA; VI = VIH 1.4 1.4 1.05 −
IOH = −6 mA; VI = VIH 1.65 1.65 1.25 −
2.3 2.3 2.0 −
IOH = −12 mA; VI = VIH 2.3 2.3 1.8 −
2.7 2.7 2.2 −
IOH = −18 mA; VI = VIH 2.3 2.3 1.7 −
3.0 3.0 2.4 −
IOH = −24 mA; VI = VIH 3.0 3.0 2.2 −
VOL Output LOW Voltage IOL = 100 mA; VI = VIL 0.9 – 4.5 0.9 – 4.5 −0.2 V
IOL = 0.5 mA; VI = VIL 1.1 1.1 −0.3
IOL = 2 mA; VI = VIL 1.4 1.4 −0.35
IOL = 6 mA; VI = VIL 1.65 1.65 −0.3
IOL = 12 mA; VI = VIL 2.3 2.3 −0.4
2.7 2.7 −0.4
IOL = 18 mA; VI = VIL 2.3 2.3 −0.6
3.0 3.0 −0.4
IOL = 24 mA; VI = VIL 3.0 3.0 −0.55
IIInput Leakage Current VI = VCCA or GND 0.9 – 4.5 0.9 – 4.5 −1.0 1.0 mA
IOFF Power−Off Leakage Current OE = 0 V 0
0.9 – 4.5
0.9 – 4.5
0
−1.0
−1.0
1.0
1.0
mA
ICCA Quiescent Supply Current VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5 0.9 − 4.5 −1.0 mA
ICCB Quiescent Supply Current VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5 0.9 − 4.5 −1.0 mA
ICCA + ICCB Quiescent Supply Current VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5 0.9 – 4.5 −2.0 mA
DICCA Increase in ICC per Input Voltage,
Other Inputs at VCCA or GND
VI = VCCA – 0.6 V;
VI = VCCA or GND
4.5
3.6
4.5
3.6
−10
5.0
mA
DICCB Increase in ICC per Input Voltage,
Other Inputs at VCCA or GND
VI = VCCA – 0.6 V;
VI = VCCA or GND
4.5
3.6
4.5
3.6
−10
5.0
mA
IOZ I/O Tri−State Output Leakage
Current
TA = 25°C, OE = 0 V 0.9 – 4.5 0.9 – 4.5 −1.0 1.0 mA
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5
TOTAL STATIC POWER CONSUMPTION (ICCA + ICCB)
−405C to +855C
VCCB (V)
4.5 3.3 2.8 1.8 0.9
VCCA (V) Min Max Min Max Min Max Min Max Min Max Unit
4.5 2 2 2 2 < 1.5 μA
3.3 2 2 2 2 < 1.5 μA
2.8 < 2 < 1 < 1 < 0.5 < 0.5 μA
1.8 < 1 < 1 < 0.5 < 0.5 < 0.5 μA
0.9 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 μA
NOTE: Connect ground before applying supply voltage VCCA or VCCB. This device is designed with the feature that the power−up sequence
of VCCA and VCCB will not damage the IC.
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter VCCA (V)
−405C to +855C
Unit
VCCB (V)
4.5 3.3 2.8 1.8 1.2
Min Max Min Max Min Max Min Max Min Max
tPLH,
tPHL
(Note 1)
Propagation
Delay,
An to Bn
4.5 1.6 1.8 2.0 2.1 2.3 nS
3.3 1.7 1.9 2.1 2.3 2.6
2.8 1.9 2.1 2.3 2.5 2.8
1.8 2.1 2.4 2.5 2.7 3.0
1.2 2.4 2.7 2.8 3.0 3.3
tPZH,
tPZL
(Note 1)
Output
Enable,
OE to Bn
4.5 2.6 3.8 4.0 4.1 4.3 nS
3.3 3.7 3.9 4.1 4.3 4.6
2.5 3.9 4.1 4.3 4.5 4.8
1.8 4.1 4.4 4.5 4.7 5.0
1.2 4.4 4.7 4.8 5.0 5.3
tPHZ,
tPLZ
(Note 1)
Output
Disable,
OE to Bn
4.5 2.6 3.8 4.0 4.1 4.3 nS
3.3 3.7 3.9 4.1 4.3 4.6
2.5 3.9 4.1 4.3 4.5 4.8
1.8 4.1 4.4 4.5 4.7 5.0
1.2 4.4 4.7 4.8 5.0 5.3
tOSHL,
tOSLH
(Note 1)
Output to
Output
Skew,
Time
4.5 0.15 0.15 0.15 0.15 0.15 nS
3.3 0.15 0.15 0.15 0.15 0.15
2.5 0.15 0.15 0.15 0.15 0.15
1.8 0.15 0.15 0.15 0.15 0.15
1.2 0.15 0.15 0.15 0.15 0.15
1. Propagation delays defined per Figure 2.
CAPACITANCE
Symbol Parameter Test Conditions Typ (Note 2) Unit
CIN Control Pin Input Capacitance VCCA = VCCB = 3.3 V, VI = 0 V or VCCA/B 3.5 pF
CI/O I/O Pin Input Capacitance VCCA = VCCB = 3.3 V, VI = 0 V or VCCA/B 5.0 pF
CPD Power Dissipation Capacitance VCCA = VCCB = 3.3 V, VI = 0 V or VCCA, f = 10 MHz 20 pF
2. Typical values are at TA = +25°C.
3. CPD is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
ICC(operating) ^ CPD x VCC x fIN x NSW where ICC = ICCA + ICCB and NSW = total number of outputs switching.
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6
Figure 2. AC (Propagation Delay) Test Circuit
DUT
Pulse
Generator
VCC
CLRL
RL
VCCO x 2
OPEN
GND
Test Switch
tPLH, tPHL OPEN
tPLZ, tPZL VCCO x 2
tPHZ, tPZH GND
CL = 15 pF or equivalent (includes probe and jig capacitance)
RL = 2 kW or equivalent
ZOUT of pulse generator = 50 W
Figure 3. AC (Propagation Delay) Test Circuit Waveforms
Input (An)
Output (Bn)
OEnVm Vm
Vm
Vm
Vm Vm
Vm
Vm
tPLH tPHL
VIH
0 V
VOH
VOL
VIH
0 V
VOH
VY
VOL
VX
tPZH
tPZL
tPHZ
tPLZ
≈0 V
≈ VCC
Waveform 1 − Propagation Delays
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Waveform 2 − Output Enable and Disable Times
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Output (Bn)
Output (Bn)
Symbol
VCC
3.0 V – 4.5 V 2.3 V − 2.7 V 1.65 V − 1.95 V 1.4 V − 1.6 V 0.9 V − 1.3 V
VmA VCCA/2 VCCA/2 VCCA/2 VCCA/2 VCCA/2
VmB VCCB/2 VCCB/2 VCCB/2 VCCB/2 VCCB/2
VXVOL x 0.1 VOL x 0.1 VOL x 0.1 VOL x 0.1 VOL x 0.1
VYVOH x 0.9 VOH x 0.9 VOH x 0.9 VOH x 0.9 VOH x 0.9
NLSV2T244
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7
PACKAGE DIMENSIONS
UDFN8 1.8 x 1.2, 0.4P
CASE 517AJ
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH MAY
NOT EXCEED 0.03 ONTO BOTTOM
SURFACE OF TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
ÉÉ
ÉÉ
A B
E
D
BOTTOM VIEW
b
e
8X
BAC
CNOTE 3
0.10 C
PIN ONE
REFERENCE
TOP VIEW
0.10 C
A
A1
(A3)
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
L
8X
14
58
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b0.15 0.25
D1.80 BSC
E1.20 BSC
e0.40 BSC
L0.45 0.55
e/2
b2 0.30 REF
L1 0.00 0.03
L2 0.40 REF
DETAIL A
(L2)
(b2)
NOTE 5
L1
DETAIL A
M
0.10
M
0.05 0.22
0.32
8X
1.50
0.40 PITCH
0.66
DIMENSIONS: MILLIMETERS
MOUNTING FOOTPRINT
7X
1
SOLDERMASK DEFINED
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8
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NLSV2T244
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9
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE H
S
B
M
0.08 (0.003) A S
T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
b
e
PIN 1 ID
8 PL
0.038 (0.0015)
−T−
SEATING
PLANE
A
A1 cL
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8X 8X
6X ǒmm
inchesǓ
SCALE 8:1
1.04
0.041
0.38
0.015
5.28
0.208
4.24
0.167
3.20
0.126
0.65
0.0256
DIM
A
MIN NOM MAX MIN
MILLIMETERS
−− −− 1.10 −−
INCHES
A1 0.05 0.08 0.15 0.002
b0.25 0.33 0.40 0.010
c0.13 0.18 0.23 0.005
D2.90 3.00 3.10 0.114
E2.90 3.00 3.10 0.114
e0.65 BSC
L0.40 0.55 0.70 0.016
−− 0.043
0.003 0.006
0.013 0.016
0.007 0.009
0.118 0.122
0.118 0.122
0.026 BSC
0.021 0.028
NOM MAX
4.75 4.90 5.05 0.187 0.193 0.199
HE
HE
DD
E
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NLSV2T244/D
PUBLICATION ORDERING INFORMATION
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USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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