Silicon Video Inc. P.O. Box 4902, Ithaca, NY 14852-4902, .TEL: 607.756.5200, FAX: 607.756.5319 www.siliconvideo.biz , sales@siliconvideo.biz ELIS-1024 Enhanced High Performance Linear CMOS Image Sensor The ELIS-1024 image sensor is a high performance, very low noise linear image sensor designed for a wide variety of applications including: P/N: ELIS-1024A-LG 16-pin LCC package * * * * * * * * Spectroscopy Bar Code Reading Edge Detection Contact Scanning Optical Character Recognition Encoding Position Detection And more....... Description The ELIS-1024 Linear Image Sensor consists of an array of high performance, low dark current photodiode pixels. The sensor features sample and hold capability, selectable resolution and advanced power management. The device can operate at voltages as low as 2.8V making it ideal for portable applications. A key feature over traditional CCD technology is that the device can be read and reread Non-Destructively, allowing the user to maximize signal to noise and dynamic range. Internal logic automatically reduces power consumption when lower resolution settings are selected. A low power standby mode is also available to reduce system power consumption when the imager is not in use. Key Features * * * * * * * * * * Low Cost Single Voltage Operation, Wide Operating Range Selectable Resolutions of 1024, 512, 256 and 128 pixels Very Low Power via Intelligent Power Management and Low-Power Standby Mode Sample and Hold Full Frame Shutter and Dynamic Pixel Reset (DPR) Modes High Sensitivity High Signal to Noise, very low dark current Non-Destructive Read mode, extremely low noise capable via signal averaging Completely Integrated Timing and Control PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 1 of 10 FUNCTIONAL BLOCK DIAGAM PIN DESCRIPTION - 16-Pin LCC Package 1, 12 2, 11 3 4 5 AGND AVDD DATA RST M0 6 7 8, 9 10 13 14 15 16 M1 SHT N/C VOUT RM DVDD DGND CLK PDS0004 Rev. A Input Input Input Input Input Output Input Input Analog Ground Analog Power Start Readout Reset Bin Select Bit 0 Bin Select Bit 1 Shutter No Connection Analog Video Output (requires external pull-up resistor) Reset Mode: RM = 0 for frame mode, RM = 1 for DPR mode Digital Power Digital Ground Master Clock (@ pixel rate) Silicon Video, Inc. 2003 Subject to change without notice. Page 2 of 10 Electro-Optical Characteristics Specs given at 24oC, 5.0V, 1MHz clock with 50% duty cycle and a 3200K light source unless otherwise noted. Parameter Min Typical Max Units Supply Voltage 2.80 5.0 5.5 V Supply Current (see Note 1): Res = 1024 20.0 Res = 512 11.0 mA Res = 256 6.5 Res = 128 4.0 Standby Current 25 A V -0.6V Input High Logic Level DD V Input Low Logic Level 0.6 V Clock Frequency/Pixel Read Rate (see Note 1.0 1000 30,000 kHz 3) External Pull- up Load 5000 Output Voltage at Saturation (see Note 4) 4.8 V Output Voltage at Dark 2.1 V Conversion Gain: Res = 1024 0.83 V/eRes = 512 0.98 Res = 256 1.18 Res = 128 1.51 Full Well:(note 7) Res = 1024 3.26 MeRes = 512 2.77 Res = 256 2.28 Res = 128 1.79 Dynamic Range (note 7) 71 dB Pixel Non-Uniformity Dark 0.5 %Sat Linearity (see Note 2) 0.8 % Output due to Dark Current (note 6) 8 mV/s Fill Factor 100 %Area Absolute QE at peak (675nm) 60 % Read Noise (see Note 5) 0.8 mVrms Notes 1. Includes 5k load resistor and measured at dark. Increased speed increases power consumption. 2. 3. 4. 5. 6. 7. Pixel average from 5% - 75% saturation. Specs given at pixel read rates of 1 MHz at 24o C. At greater read rates MTF and Dynamic Range begin to degrade. Higher speeds may not be possible at lower supply voltages. At supply voltages less than saturation voltage, Vout is clipped by supply, no load applied. Temporal rms noise @ 1 MHz pixel rate and 500kHz video bandwidth filter applied, values are typical and may vary. Higher Dynamic Range is possible with lower pixel rates and bandwidths. Output due to dark current changes approximately 1.4mV/o C. Values are internally limited. PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 3 of 10 Absolute maximum ratings, TA = 25C unless otherwise noted, see Note 1, below. Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -16 mA to 16 mA Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 50C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20C to 85C Humidity range, RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-100%, non-condensing Lead temperature 1.5 mm (0.06 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235C Exceeding the ranges specified under "absolute maximum ratings" can damage the device. The values given are for stress ratings only. Operation of the device at conditions other than those indicated under "recommended operating conditions" is not implied. Exposing the device to absolute maximum rated conditions for extended periods may affect device reliability and performance. NOTES: 1. Voltage values are with respect to the device GND terminal. 2. Case temperature is defined as the surface temperature of the package measured directly over the integrated circuit. QE RESPONSE 1.2000 Normalized 1.0000 0.8000 0.6000 0.4000 0.2000 50 10 5 97 0 90 5 82 0 75 5 67 0 60 5 52 0 45 5 37 30 0 0.0000 Wavelength Note: Data below 350nm not measured, but device is sensitive to 200 nm. The QE peaks at 675nm. Shown for un-filtered and un-covered device. PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 4 of 10 Resolution Selection By setting the M0 and M1 inputs as indicated in Table 1, several effective resolutions can be realized. The effective imager length is 7.987mm regardless of the selected resolution. Internally, the device has 1024 pixels. As the resolution decreases the effective pixel area increases as in Table 1. When the resolution is set to 512, the photodiodes of pixels 1 and 2 are averaged and output as a single value, pixels 3 and 4 are averaged and output as a single value, and so on. If set to 256 resolution, then pixels 1 through 4 are averaged and output as a single value, 5 through 8 are averaged and output as a single value, and so on. The internal control logic determines the resolution and always outputs a valid pixel per clock cycle. For example, if the imager is selected for 256-pixel resolution, then only 256 clock cycles are needed to read out the imager once DATA is set. Thus, for lower resolutions higher frame rates are possible as indicated in Table 1. M1 M0 0 0 1 1 0 1 0 1 Table 1: Resolution Select. Resolution Effective Pixel Size 1024 512 256 128 7.8 x 125m 15.6 x 125m 31.2 x 125m 64.4 x 125m Frame Rate @ 1MHz Clock (frames/s) 976 1953 3906 7812 Power Management and Standby Mode This device incorporates internally controlled power management features and an externally controlled low-power Standby Mode. When resolutions lower than 1024-pixels are selected, internal logic disables the unused amplifiers reducing the power consumption. Utilizing the existing external signals RST and DATA a low-power Standby Mode is possible. When RST and DATA are simultaneously held high the entire imager is put into Standby Mode. In this mode all internal amplifiers are disabled, the internal clocks are stopped and the output amplifier is also disabled. The clock can be held low or high or remain running while the imager is held in standby. PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 5 of 10 Frame Mode Timing (RM = 0) In Frame Mode three signals are required for operation not including resolution selection and CLK. These being reset (RST), shutter (SHT) and start data readout (DATA). Both RST and SHT are asynchronous to the system clock, which allows unlimited reset and integration timing resolution. Standard Timing The timing relations for Standard Timing are shown in Figure 1 and detailed descriptions are given below. In the VIDEO waveform the `X Clock Cycles' is determined by the resolution selected. The clock should be 50% duty cycle. CLK t RST RST t int SHT DATA Video_Out VIDEO X Clock Cycles Figure 1: Start of Frame Timing Diagram. Device Reset: The pixels are simultaneously reset while the RST and SHT inputs are both held high for at least 200ns, as indicated by tRST . The imager can be held in reset indefinitely by keeping both inputs high. When RST is high the internal clocks to the shift register are disabled and the shift register is held in reset. Once RST goes low the shift register comes out of reset and the clocks begin running. Integration: Once RST goes low (while SHT is high), the pixels begin to integrate. Integration continues until SHT goes low as indicated by tint. Readout: Readout will begin on the first rising edge of CLK after the DATA input is set high. DATA must be brought low prior to the next rising edge of CLK, otherwise pixel 1 is again output along with pixel 2. See Figure 2 for details. The RST pulse always resets the internal shift register, thus the next pixel to be readout after the first rising edge of CLK when DATA is asserted is the first pixel. The timing details of the DATA pulse are shown below, tD = 10ns. CLK tD tD tD tD DATA PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 6 of 10 Figure 2: Detailed DATA Pulse Timing Diagram. Non-Destructive Readout (NDRO) NDRO mode is similar to the standard mode of operation except that the pixels are readout multiple times for a single integration time. The required signal timings are shown in Figure 3. CLK tRST RST t int1 SHT DATA VIDEO Video_Out1 Video_Out1 X Clock Cycles X Clock Cycles Figure 3: Non-Destructive Readout Timing Diagram. Dynamic Pixel Reset (DPR) Mode Timing (RM = 1) In DPR mode the pixels are reset by internal signals, which eliminates the need for using the external reset pin. When operating in DPR mode RST must be held low otherwise the internal logic will be held in reset. However, RST does NOT reset the pixels in DPR mode. Since the pixels are continuously integrating (except the one clock cycle they are being reset) the SHT pin should always be held high. The first frame readout will be invalid because the pixels will have been integrating for an unknown period of time. Valid video will be generated during the second frame. The required signal timings are illustrated in Figure 4. Pixel1_Readout Pixel1_Readout Pixel1_Reset Pixel1_Reset tCLK CLK RST SHT tDATA DATA Pixel1_t int Frame1 VIDEO X Clock Cycles Frame2 X Clock Cycles Figure 4: DPR Mode Timing Diagram. Pixel 1 was used as an example to show the key timing situations. During the first clock cycle after DATA is high pixel 1 is readout. Then while pixel 2 is being readout during the second clock cycle PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 7 of 10 pixel one is being reset. The integration time for pixel 1 then becomes the time between the rising edge of the third clock pulse of Frame 1 to the rising edge of the second clock of Frame 2. In general the integration time is the period of DATA less one clock cycle (tint = tDATA - tCLK). In reality the integration time ends when the signal is sampled by the external circuitry. A one-clock cycle delay between the end of Frame 1 and start of Frame 2 is shown in Figure 4. This delay can be as low as zero clock cycles and as high as desired. There is no restriction to the delay between frames but at very long integration times dark current may become an issue. Typical Application Circuit AVDD DVDD From Regulator Ferrite 1 16 AGND 10uF 0.1uF CLK from ASIC CLK 0.01uF 2 15 AVDD DGND 3 DATA 4 RST from ASIC RST 5 M0 from ASIC M1 from ASIC M0 6 M1 ELIS-1024 0.1uF DATA from ASIC 14 DVDD 13 RM from ASIC RM 12 AGND 0.01uF 0.1uF 11 AVDD AVDD 5k 7 SHT from ASIC 8 PDS0004 Rev. A 10 SHT Vout N/C N/C To A/D Converter 9 Silicon Video, Inc. 2003 Subject to change without notice. Page 8 of 10 LCC Package Mechanical Information PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 9 of 10 ORDERING INFORMATION These devices are offered in a Leadless Chip Carrier package. ELIS-1024A-LG Leadless Chip Carrier (LCC) Contact Silicon Video, Inc. or your local authorized representative for availability. NOTICE Silicon Video, Inc. (hereinafter SVI) reserves the right to make product modifications or discontinue products or services without notice. Customers are advised to obtain latest written specifications or other relevant information prior to ordering products or services. Information provided SVI is believed to be accurate at time of publication release. SVI shall not be held liable for any damages, consequential or inconsequential resulting from errors or omissions of documentation, or use of our products. Product sales are subject to the SVI Terms and Conditions of Sale in force at the time of order acknowledgement. SVI assumes no liability for customer products or designs. SVI does not warrant or represent that any license, either expressed or implied, is granted under any patent, copyright, or any other intellectual property right of SVI for any product or process for which SVI products or services are used. SVI does not endorse, warrant, or approve any third party's products or service information that may be published by SVI. SVI's products are not designed, authorized, or warranted for use in life support devices or systems, or any other critical application which may involve death, injury, property or environmental damages. Using SVI's products for any critical application is fully at the risk of the customer and their end users and assigns. PDS0004 Rev. A Silicon Video, Inc. 2003 Subject to change without notice. Page 10 of 10