© 2008 Microchip Technology Inc. DS21202J-page 1
24C02C
Features:
Single-Supply with Operation from 4.5V to 5.5V
Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby cur rent 5 μA, max.
2-Wire Serial Inte rfac e, I2C™ Compatible
Cascadable up to Eight Devices
Schmitt Trigger Inputs for Noise Suppression
Output Slop e C o ntro l t o El im ina te Gro und Bounce
100 kHz and 400 kHz Clock Compatibility
Fast Page or Byte Write Time 1 ms, typical
Self-Timed Erase/Write Cycle
16-Byte Page Write Buffer
Hardware Write-Protect for Upper Half of the
Array (80h-FFh)
ESD Protection >4,000V
More than 1 Million Erase/Write Cycles
Data Retention >200 Years
Factory Programming Available
Packages Include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and MSOP
Pb-Free and RoHS Compliant
Temperature ranges:
Description:
The Microchip Technology Inc. 24C02C is a 2K bit
Serial Electrically Erasable PROM with a voltage range
of 4.5V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial
interface. Low-current design permits operation with
max. standby and active currents of only 5 μA and 1
mA, resp ec tive l y. The device ha s a p a ge w rite capabil-
ity for up to 16 bytes of data and has fast write cycle
times of only 1 ms for both byte and page writes.
Functional address lines allow the connection of up to
eight 24C02C devices on the same bus for up to 16K
bits of contiguous EEPROM memory. The device is
available in the standard 8-pin PDIP, 8-pin SOIC (3.90
mm), 8-pin 2x3 DFN and TDFN, 8-pin MSOP and
TSSOP packages.
Block Diagram
Package Types
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
I/O
Control
Logic
Memory
Control
Logic XDEC
HV Generator
EEPROM
Array
Write-Protect
Circuitry
YDEC
Vcc
Vss
Sense Amp.
R/W Control
SDA SCL
A0 A1 A2 WP
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP, MSOP SOIC, TSSOP
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
DFN/TDFN
A0
A1
A2
VSS
WP
SCL
SDA
VCC
8
7
6
5
1
2
3
4
2K 5.0V I2C Serial EEPROM
24C02C
DS21202J-page 2 © 2008 Microchip Technology Inc.
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This i s a stres s ratin g only and functio nal operati on of the devic e at thes e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS Electrical Characteristics:
Industri al (I): VCC = +4.5V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +4.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
D1 A0, A1, A2, SCL, SDA
and WP pins: ——
D2 VIH High-level input voltage 0.7 VCC —V
D3 VIL Low-level input voltage 0.3 VCC V—
D4 VHYS Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC —V(Note)
D5 VOL Low-level output voltage 0.40 V IOL = 3.0 ma @ VCC = 4.5V
D6 ILI Input leakage current ±1 μAVIN = VSS or VCC, WP = VSS
D7 ILO Output leaka ge curre nt ±1 μAVOUT = VSS or VCC
D8 CIN,
COUT Pin capacitance
(all inputs/outpu ts) —10pFVCC = 5.0V (Note)
TA = 25°C, f = 1 MHz
D9 ICC Read Operating current 1 mA VCC = 5.5V, SCL = 400 kHz
ICC Write 3 mA VCC = 5.5V
D10 ICCS Standby current 5 μAVCC = 5.5VSCL = SDA = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
© 2008 Microchip Technology Inc. DS21202J-page 3
24C02C
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Electric al Char ac teristi cs:
Industrial (I): VCC = +4.5V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +4.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency
100
400 kHz
(I-temp)
2T
HIGH Clock high time 4000
600
ns
(I-temp)
3T
LOW Clock low ti me 4700
1300
ns
(I-temp)
4T
RSDA and SCL rise time
(Note 1)
1000
300 ns
(I-temp)
5T
FSDA and SCL fall time
(Note 1) 300 ns
(I-temp)
6T
HD:STA Start condi tion hold tim e 4000
600
ns
(I-temp)
7T
SU:STA Start condition setu p time 4700
600
ns
(I-temp)
8T
HD:DAT Data input hold time 0 ns (Note 2)
9TSU:DAT Data input setup time 250
100
ns
(I-temp)
10 TSU:STO Stop condition setup time 4000
600
ns
(I-temp)
11 TAA Output valid from clock
(Note 2)
3500
900 ns
(I-temp)
12 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
ns
(I-temp)
13 TOF Output fall time from VIH
minimum to VIL maximum
CB 100 pF
10 + 0.1CB 250 ns (Note 1)
14 TSP Input filter spike suppre ssion
(SDA and SCL pins) —50ns(Note 3)
15 TWC Write cycle time (byte or
page) —1.5
1ms
(I-temp)
16 Endurance 1,000,000 cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide
improved noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tes ted but ensured by characterization. For end urance estimates in a specif ic
applic ation, ple ase con sult the Total Enduran ce™ Model, w hich c an be ob tained from Micr ochip’ s web site
at www.microchip.com.
24C02C
DS21202J-page 4 © 2008 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
SCL
SDA
IN
SDA
OUT
5
7
6
14
3
2
89
11
D4 4
10
12
© 2008 Microchip Technology Inc. DS21202J-page 5
24C02C
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal; therefore, the SDA bus requires a pull-
up resistor to VCC (typ ical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For norma l data trans fer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for i ndicating the Start and Stop conditions.
2.2 SCL Serial Clock
This i nput is u sed t o sy nchron ize the d ata trans fer fro m
and to the device.
2.3 A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. T hese i nput s mu st be c onnec ted to e ither VCC or
VSS.
2.4 WP
This is the hardware write-p rotect pin. It must be tie d to
VCC or VSS. If tied to Vcc, the ha rdware write protectio n
is enabled. If the WP pin is tied to VSS the hardware
write protection is disabled.
2.5 Noise Protection
The 24C02C employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Name PDIP SOIC TSSOP DFN/TDFN MSOP Function
A0 1 1 1 1 1 Address Pin A0
A1 2 2 2 2 2 Address Pin A1
A2 3 3 3 3 3 Address Pin A2
VSS 44444Ground
SDA 5 5 5 5 5 Serial Address/Data I/O
SCL 6 6 6 6 6 Serial Clock
WP 7 7 7 7 7 Write-Protect Input
VCC 8 8 8 8 8 +4.5 V to 5.5 V Power Supply
24C02C
DS21202J-page 6 © 2008 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTIONS
The 24C02C supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receivi ng dat a as receiver. The bus has to be controlle d
by a master device that generates the Serial Clock
(SCL), contro ls the bus access, and generates the S tart
and Stop conditi ons, while the 24C02C wor ks as slave.
Both master and slave can operate as transmitter or
rece iver b ut the ma ster de vice det ermine s whic h mod e
is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figur e 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 S top Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera-
tions must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwri te does occur it will replace da ta in a firs t-in first-
out fashion.
4.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. Th e mast er device mus t ge nera te a n ex tra c lock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line du ring the Acknow ledge cl ock pulse in s uch a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by no t g ene rati ng an Acknow led ge bi t o n t he las t
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the maste r to gen erat e the Stop condition (Figur e 4-2 ).
Note: The 24C02C does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
© 2008 Microchip Technology Inc. DS21202J-page 7
24C02C
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
(A) (B) (C) (D) (A)(C)
SCL
SDA
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL 987654321123
T r ans mitter mu s t rele a s e th e SDA l in e at t his po int
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter Data from transmitter
SDA
Acknowledge
Bit
24C02C
DS21202J-page 8 © 2008 Microchip Technology Inc.
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The con tr ol by te cons ists of a fou r-bi t co ntro l code ; for
the 24C02C this is set as ‘1010’ binary for read and
write op erat ion s. Th e ne xt three bits of th e co ntrol byte
are t he C hip Sele ct b its (A 2, A1 , A0) . Th e C hip S ele ct
bits allo w th e us e of up to eigh t 2 4C02C dev ices on th e
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
corresp ond to the logic lev els on the corresp onding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. Following the Start condition, the 24C02C
monitors the SDA bus checking the control byte being
transmitted. Upon receiving a ‘1010’ code and appro-
priate Chip Select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24C02C will select a read or
write operation.
FIGURE 5-1: CONTROL BYTE FORMAT
5.1 Contiguous Addressing Across
Multi ple Devices
The Chip Select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 16K bits by
adding up to eight 24C02C devices on the same bus.
In this case, software can use A0 of the control byte
as address bit A9, A1 as address bit A10, and A2 as
address bit A1 1. It is not possible to write or read across
device boundaries.
1 0 1 0 A2 A1 A0SACKR/W
Control Code Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
© 2008 Microchip Technology Inc. DS21202J-page 9
24C02C
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code (4 bits), the Chip Select bits (3 bits) and the R/W
bit, which i s a logi c low, is pl aced on to the bu s by the
master transmitter. The device will acknowledge this
control by te during the ninth clock pulse. The ne xt byte
tran smit ted by the ma ster is the word add res s and wi ll
be written into the Address Pointer of the 24C02C.
After receiving another Acknowledge signal from the
24C02C the master device will transmit the data word
to be written into the addressed memory location. The
24C02C acknowledges again and the master gener-
ates a Stop condition. This initiates the internal write
cycle, and during this time the 24C02C will not gener-
ate Acknowledge signals (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
6.2 Page Write
The write control byte, word address and the first data
byte are tr ansmitted to the 24 C02C in the same way a s
in a byte write. But instead of generating a Stop
conditi on, th e mas ter tran smit s u p to 15 addi tional dat a
bytes to the 24C02C which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a Stop
conditi on. Af ter the rec eipt of ea ch wor d, the four lo wer
order Address Pointer bits are internally incremented
by o ne. T h e hi ghe r o rde r f o ur bi ts of th e w ord a d dr ess
remains constant. If the master should transmit more
than 1 6 bytes p rior to gen erating the S top cond ition, the
address counter will roll over and the previously
received data will be overwritten.
As with the byte write operation, once the Stop
condition is received an internal write cycle will begin
(Figure 6-2). If an attempt is made to write to the
protected portion of the array when the hardware write
protection has been enabled, the device will acknowl-
edge the command, but no data will be written. The
write cycle time must be observed even if the write
protection is enabled.
6.3 Write Protection
The WP pin must be tied to VCC or VSS. If tied to VCC,
the upper half of the array (080-0FF) will be write-
protected. If the WP pin is tied to VSS, then write
operations t o all address locat ions a re allowed.
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’ ) and end at address es that a re
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to the next pa ge as mi ght be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
S P
Bus Activit y
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte Word
Address (n) Data n Data n + 15
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data n +1
24C02C
DS21202J-page 10 © 2008 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no AC K is retu rned, then the S t art b it and cont rol byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condit ion to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
© 2008 Microchip Technology Inc. DS21202J-page 11
24C02C
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There a re three ba sic types
of read operat ions: curren t address read, ra ndom rea d,
and sequential read.
8.1 Current Address Read
The 24C02C contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operatio n wou ld acc ess dat a f rom add ress n + 1. U pon
receipt of the slav e address w ith the R/W b it set to one,
the 24C02C issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer , but does generate a S top condition and the
24C02 C disc onti nue s transmissi on (Figu r e 8-1).
FIGURE 8-1: CURRENT ADDRESS
READ
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad o peration, first the word ad dres s m us t
be set. This is done b y sending the word address to the
24C02C as part of a write operation. After the word
address is sent, the master generat es a Start condi tion
following the acknowledge. This terminates the write
operatio n, but not before the internal Address Pointer is
set. Then t he ma ster issu es the cont rol byte ag ain but
with the R/W bit set to a one. The 24C02C will then
issue an acknowledge and transmits the eight bit data
word. Th e master wil l not a cknowl edge th e transfer b ut
does generate a Stop condition and the 24C02C
discontinues transmission (Figure 8-2). After this
command, the i nterna l address counte r will po int to th e
address location following the one that was just read.
8.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random read except that after the 24C02C transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24C02C to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24C02C contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation. The internal Address
Pointer will automatically roll over from address FF to
address 00.
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
Bus Activi ty
Master
SDA line
Bus Activi ty
P
S
S
T
O
P
Control
Byte
S
T
A
R
TData
A
C
K
N
O
A
C
K
S P
S
S
T
A
R
T
S
T
O
P
Control
Byte
A
C
K
Word
Address (n) Control
Byte
S
T
A
R
TData (n)
A
C
K
A
C
K
N
O
A
C
K
Bus Activity
Master
SDA line
Bus Activity
Control
Byte Data n Data n + 1 Data n + 2 Data n + X
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
Bus Activit y
Master
SDA line
Bus Activit y
24C02C
DS21202J-page 12 © 2008 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP Example:
24C02C
I/P 13F
0527
24C02CI
SN 0527
13F
8-Lead MSOP Example:
XXXX
TYWW
NNN
4C2C
I527
13F
XXXXT
YWWNNN
3
e
3
e
8-Lead 2x3 DFN
XXX
YWW
NN
2P7
527
13
Example:
4C2CI
52713F
8-Lead 2x3 TDFN
XXX
YWW
NN
AP7
527
13
Example:
© 2008 Microchip Technology Inc. DS21202J-page 13
24C02C
Part Number
1st Line Marking Codes
TSSOP MSOP DFN TDFN
I Temp. E Temp. I Temp. E Temp.
24C02C 4C2C 4C2CT 2P7 2P8 AP7 AP8
Note: T = Temperature grade (I, E)
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the ev ent the fu ll Micr ochip part nu mber ca nnot be m arked o n one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
24C02C
DS21202J-page 14 © 2008 Microchip Technology Inc.


  !"#$%&"' ()"&'"!&)&#*&&&#
 +%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#
 '!#&.0
1,21!'!&$& "!**&"&&!
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 7,8.
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
&& = = 
##44!!   - 
1!&&   = =
"#&"#>#& .  - -
##4>#& .   <
: 9& -< -? 
&& 9  - 
9#4!! <  
69#>#& )  ? 
9*9#>#& )  < 
: *+ 1 = = -
N
E1
NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
  * ,<1
© 2008 Microchip Technology Inc. DS21202J-page 15
24C02C
 ! ""#$%& !'

  !"#$%&"' ()"&'"!&)&#*&&&#
 +%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
 '!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
: 8& = = 
##44!!   = =
&#%%+  = 
: >#& . ?1,
##4>#& . -1,
: 9& 1,
,'%@&A  = 
3&9& 9  = 
3&& 9 .3
3& IB = <B
9#4!!  = 
9#>#& ) - = 
#%& DB = B
#%&1&&' EB = B
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
  * ,1
24C02C
DS21202J-page 16 © 2008 Microchip Technology Inc.
 ! ""#$%& !'
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
© 2008 Microchip Technology Inc. DS21202J-page 17
24C02C
() )"* ! (+%+( !

  !"#$%&"' ()"&'"!&)&#*&&&#
 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
- '!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& ?1,
: 8& = = 
##44!!  <  
&#%%   = 
: >#& . ?1,
##4>#& . -  
##49&  - -
3&9& 9  ? 
3&& 9 .3
3& IB = <B
9#4!!  = 
9#>#& )  = -
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
  * ,<?1
24C02C
DS21202J-page 18 © 2008 Microchip Technology Inc.
," !*-, , !

  !"#$%&"' ()"&'"!&)&#*&&&#
 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
- '!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& ?1,
: 8& = = 
##44!!   < 
&#%%   = 
: >#& . 1,
##4>#& . -1,
: 9& -1,
3&9& 9  ? <
3&& 9 .3
3& B = <B
9#4!! < = -
9#>#& )  = 
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2
c
L1 L
φ
  * ,1
© 2008 Microchip Technology Inc. DS21202J-page 19
24C02C
.$*-,'/00%&.

  !"#$%&"' ()"&'"!&)&#*&&&#
 4' '$!#&)!&#!
- 4!!*!"&#
 '!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
: 8& <  
&#%%    
,&&4!! - .3
: 9& 1,
: >#& . -1,
.$!##9&  - = 
.$!##>#& .  = 
,&&>#& )   -
,&&9& 9 -  
,&&&.$!## C  = =
D
N
E
NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3 A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
  * ,-,
24C02C
DS21202J-page 20 © 2008 Microchip Technology Inc.
.$*-,'/00%&.
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
© 2008 Microchip Technology Inc. DS21202J-page 21
24C02C
.$*-,/00%12(.
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
24C02C
DS21202J-page 22 © 2008 Microchip Technology Inc.
.$*-,/00%12(.
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
© 2008 Microchip Technology Inc. DS21202J-page 23
24C02C
APPENDIX A: REVISION HISTORY
Revision D
Corrections to Section 1.0, Electrical Characteristics.
Revision E
Added DFN package.
Revision F (02/2007)
Revised Features section; Section 1.0 revised Ambient
temperature; Revised Tables 1-1, 1-2, (removed com-
mercial temp); Revised Table 2-1; Replaced On-line
Support page; Replaced Package Drawings; Revised
Product ID section.
Revision G (03/2007)
Replaced Package Drawings (Rev. AM).
Revision H (04/2008)
Replaced Package Drawings; Added TDFN package;
Revised Product ID section.
Revision J (08/2008)
Corrections to Table 1-1, DC Characteristics; Updated
Table 1-2, AC Characteristics; Revised Figure 1-1;
Updated Package Drawings.
24C02C
DS21202J-page 24 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21202J-page 25
24C02C
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24C02C
DS21202J-page 26 © 2008 Microchip Technology Inc.
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DS21202J24C02C
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© 2008 Microchip Technology Inc. DS21202J-page 27
24C02C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24C02C: 2K I2C™ Serial EEPROM
24C02CT: 2K I2C™ Serial EEPROM (Tape and Reel)
Temperature
Range: I= -40°C to +85°C
E= -40°C to +125°C
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC, (3.90 mm Body), 8-lead
ST = TSSOP (4.4 mm Body), 8-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
MC = Plastic Dual Flat (DFN), No lead package,
2x3 mm body, 8-lead
MNY(1) = Plastic Dual Flat (TDFN), No lead package,
2x3 mm bod y, 8-lead
Examples:
a) 24C02C-I/P: Industrial Temperature,
PDIP Package
b) 24C02C-E/SN: Extended Temperature,
SOIC Package
c) 24C02C-I/MNY: Industrial Temperature,
2x3 TDFN Package
Note 1: Y” indicates a Nickel, Palladium, Gold (NiPdAu) finish.
24C02C
DS21202J-page 28 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21202J-page 29
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC and SmartShunt are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Prog ra m ming , IC SP, ICE P I C , Mi n d i , M iW i , MPASM, MP L AB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporat ed in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and ds PIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21202J-page 30 © 2008 Microchip Technology Inc.
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