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  
FEATURES APPLICATIONS
DESCRIPTION
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
SINGLE-ENDED ANALOG-INPUT24-BIT, 96-kHz STEREO A/D CONVERTER
•AV Amplifier Receiver•24-Bit Delta-Sigma Stereo A/D Converter
•MD Player•Single-Ended Voltage Input: 3 V p-p
•CD Recorder•Antialiasing Filter Included
•Multitrack Receiver•Oversampling Decimation Filter
•Electric Musical Instrument– Oversampling Frequency: ×64, ×128– Pass-Band Ripple: ±0.05 dB– Stop-Band Attenuation: –65 dB
The PCM1802 is a high-performance, low-cost,– On-Chip High-Pass Filter (HPF): 0.84 Hz
single-chip stereo analog-to-digital converter with(44.1 kHz)
single-ended analog voltage input. The PCM1802uses a delta-sigma modulator with 64- or 128-times•High Performance
oversampling, and includes a digital decimation filter– THD+N: 96 dB (Typical)
and high-pass filter (HPF), which removes the dc– SNR: 105 dB (Typical)
component of the input signal. For various appli-– Dynamic Range: 105 dB (Typical)
cations, the PCM1802 supports master and slavemodes and four data formats in serial interface. The•PCM Audio Interface
PCM1802 is suitable for a wide variety of cost-– Master/Slave Mode Selectable
sensitive consumer applications where good perform-– Data Formats: 24-Bit Left-Justified; 24-Bit
ance, 5-V analog supply, and 3.3-V digital supplyI
2
S; 20-, 24-Bit Right-Justified operation is required. The PCM1802 is fabricatedusing a highly advanced CMOS process and is•Sampling Rate: 16 kHz to 96 kHz
available in the DB 20-pin SSOP package.•System Clock: 256 f
S
, 384 f
S
, 512 f
S
, 768 f
S•Dual Power Supplies: 5 V for Analog, 3.3 V forDigital
•Package: 20-Pin SSOP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VINL
VINR
VREF1
VREF2
VCC
AGND
PDWN
BYPAS
FSYNC
LRCK
MODE1
MODE0
FMT1
FMT0
OSR
SCKI
VDD
DGND
DOUT
BCK
PCM1802
(TOP VIEW)
P0009-02
Single-End
/Differential
Converter
BCK
VINL
Reference
Single-End
/Differential
Converter
VREF1
VREF2
VINR
5th Order
Delta-Sigma
Modulator
5th Order
Delta-Sigma
Modulator
×1/64 (×1/128)
Decimation
Filter
with
High-Pass Filter
Power Supply
AGNDVCC VDD
DGND
Clock and Timing Control
Serial
Interface
Mode/
Format
Control
LRCK
FSYNC
DOUT
FMT0
FMT1
MODE0
MODE1
BYPAS
OSR
PDWN
SCKI
B0004-07
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
This device contains circuits to protect its inputs and outputs against damage due to high static voltagesor electrostatic fields. These circuits have been qualified to protect this device against electrostaticdischarges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised thatprecautions be taken to avoid application of any voltage higher than maximum-rated voltages to thesehigh-impedance circuits. During storage or handling, the device leads should be shorted together or thedevice should be placed in conductive foam. In a circuit, unused inputs should always be connected toan appropriated logic voltage level, preferably either V
CC
or ground. Specific guidelines for handlingdevices of this type are contained in the publication Electrostatic Discharge (ESD) (SSYA010 ) availablefrom Texas Instruments.
BLOCK DIAGRAM
2
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ABSOLUTE MAXIMUM RATINGS
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
Terminal Functions
TERMINAL
I/O DESCRIPTIONSNAME PIN
AGND 6 – Analog GNDBCK 11 I/O Bit clock input/output
(1)
BYPAS 8 I HPF bypass control. Low: normal mode (dc cut); High: bypass mode (through)
(2)
DGND 13 – Digital GNDDOUT 12 O Audio data outputFMT0 17 I Audio data format select 0. See data format
(2)
FMT1 18 I Audio data format select 1. See data format
(2)
FSYNC 9 I/O Frame synchronous clock input/output
(1)
LRCK 10 I/O Sampling clock input/output
(1)
MODE0 19 I Mode select 0. See interface mode
(2)
MODE1 20 I Mode select 1. See interface mode
(2)
OSR 16 I Oversampling ratio select. Low: ×64 f
S
; High: ×128 f
S
(2)
PDWN 7 I Power-down control, active-low
(2)
SCKI 15 I System clock input; 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
(3)
V
CC
5 – Analog power supply, 5 VV
DD
14 – Digital power supply, 3.3 VV
IN
L 1 I Analog input, L-channelV
IN
R 2 I Analog input, R-channelV
REF
1 3 – Reference-1 decoupling capacitorV
REF
2 4 – Reference-2 voltage input, normally connected to V
CC
(1) Schmitt-trigger input(2) Schmitt-trigger input with internal pulldown (50 k Ωtypically), 5-V tolerant(3) Schmitt-trigger input, 5-V tolerant
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage V
CC
6.5 VV
DD
4 VGround voltage differences AGND, DGND ±0.1 VSupply voltage difference V
CC
, V
DD
V
CC
– V
DD
< 3.0 VDigital input voltage FSYNC, LRCK, BCK, DOUT –0.3 V to (V
DD
+ 0.3 V)PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 –0.3 V to 6.5 VAnalog input voltage V
IN
L, V
IN
R, V
REF
1, V
REF
2 –0.3 V to (V
CC
+ 0.3 V)Input current (any pins except supplies) ±10 mAAmbient temperature under bias –40 °C to 125 °CStorage temperature –55 °C to 150 °CJunction temperature 150 °CLead temperature (soldering) 260 °C, 5 sPackage temperature (IR reflow, peak) 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
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ELECTRICAL CHARACTERISTICS
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
all specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
, oversampling ratio=×128, 24-bit data (unless otherwise noted)
PCM1802DBTEST CONDITIONS UNITMIN TYP MAX
Resolution 24 Bits
DATA FORMAT
Left-justified, I
2
S,Audio data interface format
right-justifiedAudio data bit length 20, 24 BitsAudio data format MSB first, 2s complementf
S
Sampling frequency 16 44.1 96 kHz256 f
S
4.096 11.2896 24.576384 f
S
6.144 16.9344 36.864System clock frequency MHz512 f
S
8.192 22.5792 49.152768 f
S
12.288 33.8688
(1)
INPUT LOGIC
V
IH
(2)
2 V
DD
V
IL
(2)
0 0.8Input logic level VDCV
IH
(3)
2 5.5V
IL
(3)
0 0.8I
IH
(4)
V
IN
= V
DD
±10I
IL
(4)
V
IN
= 0 V ±10Input logic current µAI
IH
(5)
V
IN
= V
DD
65 100I
IL
(5)
V
IN
= 0 V ±10
OUTPUT LOGIC
V
OH
(6)
I
OUT
= –1 mA 2.8Output logic level VDCV
OL
(6)
I
OUT
= 1 mA 0.5
DC ACCURACY
Gain mismatch, channel-to-channel ±1±4 %FSRGain error ±2±6 %FSRBipolar zero error HPF bypassed
(7)
±2 %FSR
DYNAMIC PERFORMANCE
(8)
f
S
= 44.1 kHz, V
IN
= –0.5 dB 0.0015% 0.003%f
S
= 96 kHz, V
IN
= –0.5 dB
(9)
0.0025%THD+N Total harmonic distortion + noise
f
S
= 44.1 kHz, V
IN
= –60 dB 0.7%f
S
= 96 kHz, V
IN
= –60 dB
(9)
1.2%f
S
= 44.1 kHz, A-weighted 100 105Dynamic range dBf
S
= 96 kHz, A-weighted
(9)
103f
S
= 44.1 kHz, A-weighted 100 105S/N ratio dBf
S
= 96 kHz, A-weighted
(9)
103
(1) Maximum system clock frequency is not applicable at 768 f
S
, f
S
= 96 kHz. See the System Clock section of this data sheet.(2) Pins 9–11: FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode)(3) Pins 7–8, 15–20: PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, 5-V tolerant)(4) Pins 9–11, 15: FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode), SCKI (Schmitt-trigger input)(5) Pins 7–8, 16–20: PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-k Ωtypical pulldown resistor)(6) Pins 9–12: FSYNC, LRCK, BCK (in master mode), DOUT(7) High-pass filter(8) Analog performance specifications are tested with System Two™ audio measurement system by Audio Precision™, using 400-Hz HPF,20-kHz LPF for 44.1-kHz operation, 40-kHz LPF for 96-kHz operation in RMS mode.(9) f
S
= 96 kHz, system clock = 256 f
S
, oversampling ratio = ×64.
4
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PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS (continued)all specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
, oversampling ratio=×128, 24-bit data (unless otherwise noted)
PCM1802DBTEST CONDITIONS UNITMIN TYP MAX
f
S
= 44.1 kHz 96 103Channel separation dBf
S
= 96 kHz
(9)
98
ANALOG INPUT
Input voltage 0.6 V
CC
Vp-pCenter voltage (V
REF
1) 0.5 V
CC
VInput impedance 20 k ΩAntialiasing filter frequency response –3 dB 300 kHz
DIGITAL FILTER PERFORMANCE
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ±0.05 dBStop-band attenuation –65 dBDelay time 17.4/f
S
sHPF frequency response –3 dB 0.019 f
S
mHz
POWER SUPPLY REQUIREMENTS
V
CC
4.5 5 5.5Voltage range VDCV
DD
2.7 3.3 3.6I
CC
V
CC
= 5 V, V
DD
= 3.3 V 24 30Supply current
(10)
f
S
= 44.1 kHz V
CC
= 5 V, V
DD
= 3.3 V 8.3 10 mAI
DD
f
S
= 96 kHz, V
CC
= 5 V, V
DD
= 3.3 V
(8)
17f
S
= 44.1 kHz, V
CC
= 5 V, V
DD
= 3.3 V 147 183Power dissipation; operation mWP
D
f
S
= 96 kHz, V
CC
= 5 V, V
DD
= 3.3 V
(8)
176Power dissipation; power down V
CC
= 5 V, V
DD
= 3.3 V 0.5 mW
TEMPERATURE RANGE
Operation temperature –40 85 °CThermal resistance ( θ
JA
) 20-pin SSOP 115 °C/W
(10) Minimum load on DOUT (pin 12), BCK (pin 11), LRCK (pin 10), FSYNC (pin 9)
5
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
Digital Filter—Decimation Filter Frequency Response
Frequency [× fS]
−200
−150
−100
−50
0
50
0 8 16 24 32 40 48 56 64
Oversampling Ratio = 128
Amplitude − dB
G001
Frequency [× fS]
−200
−150
−100
−50
0
50
0 8 16 24 32
Amplitude − dB
Oversampling Ratio = 64
G002
Frequency [× fS]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.00 0.25 0.50 0.75 1.00
Amplitude − dB
Oversampling
Ratio = 128 and 64
G003
Frequency [× fS]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Amplitude − dB
Oversampling
Ratio = 128 and 64
G004
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 1. Overall Characteristics Figure 2. Overall Characteristics
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 3. Stop-Band Attenuation Characteristics Figure 4. Pass-Band Ripple Characteristics
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
,oversampling ratio = ×128, 24-bit data, unless otherwise noted.
6
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HPF (High-Pass Filter) Frequency Response
Frequency [× fS/1000]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0 1 2 3 4
Amplitude − dB
G006
Frequency [× fS/1000]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.0 0.1 0.2 0.3 0.4
Amplitude − dB
G005
Analog Filter—Antialiasing Filter Frequence Response
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
f − Frequency − Hz
Amplitude − dB
110 100 100k1k 10k
G008
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
f − Frequency − Hz
Amplitude − dB
100 1k 10k 10M100k 1M
G007
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 5. HPF Stop-Band Characteristics Figure 6. HPF Pass-Band Characteristics
AMPLITUDE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 7. Antialias Filter Stop-Band Characteristics Figure 8. Antialias Filter Pass-Band Characteristics
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
,oversampling ratio = ×128, 24-bit data, unless otherwise noted.
7
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TYPICAL PERFORMANCE CURVES
100
101
102
103
104
105
106
107
108
109
110
−50 −25 0 25 50 75 100
TA − Free-Air Temperature − °C
Dynamic Range and SNR − dB
SNR
Dynamic Range
G010
0.001
0.002
0.003
0.004
−50 −25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harmonic Distortion + Noise − %
G009
100
101
102
103
104
105
106
107
108
109
110
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
Dynamic Range and SNR − dB
SNR
Dynamic Range
G012
0.001
0.002
0.003
0.004
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
THD+N − Total Harmonic Distortion + Noise − %
G011
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE and SNRvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 9. Figure 10.
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE and SNRvs vsSUPPLY VOLTAGE SUPPY VOLTAGE
Figure 11. Figure 12.
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
,oversampling ratio = ×128, 24-bit data, unless otherwise noted.
8
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100
101
102
103
104
105
106
107
108
109
110
0 10 20 30 40
Dynamic Range and SNR − dB
44.1 96‡
48†
SNR
Dynamic Range
fSAMPLE Condition − kHz
†fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
‡fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
G014
0.001
0.002
0.003
0.004
0 10 20 30 40
fSAMPLE Condition − kHz
THD+N − Total Harmonic Distortion + Noise − %
44.1 96‡
48†
†fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
‡fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
G013
Output Spectrum
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Amplitude − dB
Input Level = −60 dB
Data Points = 8192
G016
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Input Level = −0.5 dB
Data Points = 8192
Amplitude − dB
G015
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
TYPICAL PERFORMANCE CURVES (continued)
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE and SNRvs vsf
SAMPLE
CONDITION f
SAMPLE
CONDITION
Figure 13. Figure 14.
AMPLITUE AMPLITUDEvs vsFREQUENCY FREQUENCY
Figure 15. Figure 16.
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
,oversampling ratio = ×128, 24-bit data, unless otherwise noted.
9
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−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
Signal Level − dB
THD+N − Total Harmonic Distortion + Noise − %
100
1
0.1
0.01
0.001
10
G017
Supply Current
0
5
10
15
20
25
30
0 10 20 30 40
ICC and IDD − Supply Current − mA
44.1 96‡
48†
ICC
fSAMPLE Condition − kHz
IDD
†fS = 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
‡fS = 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
G018
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
TYPICAL PERFORMANCE CURVES (continued)
TOTAL HARMONIC DISTORTION + NOISEvsSIGNAL LEVEL
Figure 17.
SUPPLY CURRENT
vsf
SAMPLE
CONDITION
Figure 18.
All specifications at T
A
= 25 °C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
,oversampling ratio = ×128, 24-bit data, unless otherwise noted.
10
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PRINCIPLES OF OPERATION
Single-End
/Differential
Converter
BCK
VINL
Reference
Single-End
/Differential
Converter
VREF1
VREF2
VINR
5th Order
Delta-Sigma
Modulator
5th Order
Delta-Sigma
Modulator
×1/64 (×1/128)
Decimation
Filter
with
High-Pass Filter
Power Supply
AGNDVCC VDD
DGND
Clock and Timing Control
Serial
Interface
Mode/
Format
Control
LRCK
FSYNC
DOUT
FMT0
FMT1
MODE0
MODE1
BYPAS
OSR
PDWN
SCKI
B0004-07
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
The PCM1802 consists of a reference circuit, two channels of single-ended-to-differential converter, a fifth-orderdelta-sigma modulator with full differential architecture, a decimation filter with high-pass filter, and a serialinterface circuit. Figure 19 illustrates the total architecture of the PCM1802, Figure 20 illustrates the architectureof single-ended-to-differential converter and antialiasing filter, and Figure 21 is the block diagram of the fifth-orderdelta-sigma modulator and transfer function. An on-chip high-precision reference with one external capacitorprovides all reference voltages that are needed in the PCM1802 and defines the full-scale voltage range for bothchannels. On-chip single-ended-to-differential signal converters save the design, space, and extra parts cost forexternal signal converters. Full-differential architecture provides a wide dynamic range and excellentpower-supply rejection performance. The input signal is sampled at a ×64 or ×128 oversampling rate, thuseliminating an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of fiveintegrators using the switched capacitor technique and a comparator, shapes the quantization noise generatedby the comparator and 1-bit DAC outside of the audio signal band. The high-order delta-sigma modulationrandomizes the modulator outputs and reduces the idle tone level. The 64-f
S
or 128-f
S
, 1-bit stream from thedelta-sigma modulator is converted to a 1-f
S
, 24-bit or 20-bit digital signal by removing high-frequency noisecomponents with a decimation filter. The dc component of the signal is removed by the HPF, and the HPF outputis converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial formats.
Figure 19. Block Diagram
11
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VINL
1
3
4
VREF1
VREF2
0.1 µF
+
1 µF20 kΩ
+
−
+
−
Delta-Sigma
Modulator
(+)
(−)
Reference
5VCC
+
10 µF
S0011-05
1st
SW-CAP
Integrator
Analog
In
X(z) +
−
+−2nd
SW-CAP
Integrator
3rd
SW-CAP
Integrator
+−4th
SW-CAP
Integrator
++++
++++
5th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function B0005-02
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
PRINCIPLES OF OPERATION (continued)
Figure 20. Analog Front End (Left Channel)
Figure 21. Block Diagram of Fifth-Order Delta-Sigma Modulator
12
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System Clock
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
PRINCIPLES OF OPERATION (continued)
The PCM1802 supports 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
as the system clock, where f
S
is the audio samplingfrequency. The system clock must be supplied on SCKI (pin 15).
The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
in slave mode. In master mode, the system clock frequency must be selected byMODE0 (pin 19) and MODE1 (pin 20), and 768 f
S
is not available. For system clock inputs of 384 f
S
, 512 f
S
, and768 f
S
, the system clock is divided to 256 f
S
automatically, and the 256 f
S
clock is used to operate thedelta-sigma modulator and the digital filter.
Table 1 shows the relationship of typical sampling frequencies and system clock frequencies, and Figure 22shows system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING RATE SYSTEM CLOCK FREQUENCY (MHz)FREQUENCY
256 f
S
384 f
S
512 f
S
768 f
S(kHz)
32 8.192 12.288 16.384 24.57644.1 11.2896 16.9344 22.5792 33.868848 12.288 18.432 24.576 36.86464 16.384 24.576 32.768 49.15288.2 22.5792 33.8688 45.1584 —96 24.576 36.864 49.152 —
PARAMETER MIN MAX UNIT
t
(SCKH)
System clock-pulse duration, high 7 nst
(SCKL)
System clock-pulse duration, low 7 ns
Figure 22. System Clock Timing
13
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Power-On Reset Sequence
System Clock
2.6 V
2.2 V
1.8 V
Internal Reset
DOUT Zero Data Normal Data
Reset
VDD
Reset Removal
1024 System Clocks 4480 / fS
T0014-05
Serial Audio Data Interface
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
The PCM1802 has an internal power-on reset circuit, and initialization (reset) is performed automatically whenthe power supply (V
DD
) exceeds 2.2 V (typical). While V
DD
< 2.2 V (typical), and for 1024 system-clock countsafter V
DD
> 2.2 V (typical), the PCM1802 stays in the reset state and the digital output is forced to zero. Thedigital output is valid after the reset state is released and the time of 4480/f
S
has passed. Figure 23 illustrates theinternal power-on reset timing and the digital output for power-on reset.
Figure 23. Internal Power-On Reset Timing
The PCM1802 interfaces with the audio system through BCK (pin 11), LRCK (pin 10), FSYNC (pin 9), and DOUT(pin 12).
14
www.ti.com
Interface Mode
Master mode
Slave mode
Data Format
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1(pin 20) and MODE0 (pin 19) as shown in Table 2 .
In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for datatransfer from an external controller.
Table 2. Interface Mode
MODE1 MODE0 INTERFACE MODE
0 0 Slave mode (256 f
S
, 384 f
S
, 512 f
S
, 768 f
S
)0 1 Master mode (512 f
S
)1 0 Master mode (384 f
S
)1 1 Master mode (256 f
S
)
In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which isgenerated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802.The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of thissignal indicates the ending point of the data. The frequency of this signal is fixed at 2 ×LRCK. The duty cycleratio depends on data bit length. The frequency of BCK is fixed at 64 ×LRCK. The 768 f
S
system clock is notavailable in master mode.
In slave mode, BCK, LRCK, and FSYNC work as input pins. FSYNC is used to enable the BCK signal, and thePCM1802 can shift out the converted data while FSYNC is HIGH. The PCM1802 accepts either the64 BCK/LRCK or the 48 BCK/LRCK format. The delay of FSYNC from the LRCK transition must be within16 BCKs for the 64 BCK/LRCK format and within 12 BCKs for the 48 BCK/LRCK format.
The PCM1802 supports four audio data formats in both master and slave modes, and they are selected by FMT1(pin 18) and FMT0 (pin 17) as shown in Table 3 . Figure 24 and Figure 26 illustrate the data formats in slavemode and master mode, respectively.
Table 3. Data Format
FORMAT# FMT1 FMT0 FORMAT
0 0 0 Left-justified, 24-bit1 0 1 I
2
S, 24-bit2 1 0 Right-justified, 24-bit3 1 1 Right-justified, 20-bit
15
www.ti.com
Interface Timing
FORMAT 0: FMT[1:0] = 00
FORMAT 1: FMT[1:0] = 01
FORMAT 2: FMT[1:0] = 10
FORMAT 3: FMT[1:0] = 11
24-Bit, MSB-First, Left-Justified
BCK
LRCK Right-ChannelLeft-Channel
DOUT 122 23 24321
MSB LSB
22 23 24321
MSB LSB
FSYNC
24-Bit, MSB-First, I2S
LRCK Right-ChannelLeft-Channel
BCK
DOUT 22 23 24321
MSB LSB
22 23 24321
MSB LSB
FSYNC
24-Bit, MSB-First, Right-Justified
LRCK Right-ChannelLeft-Channel
BCK
DOUT 24 22 23 24321
MSB LSB
22 23 24321
MSB LSB
FSYNC
20-Bit, MSB-First, Right-Justified
LRCK Right-ChannelLeft-Channel
BCK
DOUT 20 18 19 20321
MSB LSB
18 19 20321
MSB LSB
FSYNC
T0016-12
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
Figure 25 and Figure 27 illustrate the interface timing in slave mode and master mode, respectively.
Figure 24. Audio Data Format (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)
16
www.ti.com
BCK
FSYNC
LRCK
DOUT
t(FSSU)
t(BCKH)
t(BCKL)
t(LRHD)
t(FSHD)
t(LRCP)
t(LRSU)
t(BCKP) t(CKDO) t(LRDO)
1.4 V
1.4 V
1.4 V
0.5 VDD
T0017-01
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 150 nst
(BCKH)
BCK pulse duration, high 60 nst
(BCKL)
BCK pulse duration, low 60 nst
(LRSU)
LRCK setup time to BCK rising edge 40 nst
(LRHD)
LRCK hold time to BCK rising edge 20 nst
(LRCP)
LRCK period 10 µst
(FSSU)
FSYNC setup time to BCK rising edge 20 nst
(FSHD)
FSYNC hold time to BCK rising edge 20 nst
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 20 nst
(LRDO)
Delay time, LRCK edge to DOUT valid –10 20 nst
r
Rise time of all signals 10 nst
f
Fall time of all signals 10 ns
NOTE: Timing measurement reference level is (V
IH
+ V
IL
)/2. Rise and fall times are measured from 10% to 90% of IN/OUTsignal swing. Load capacitance of DOUT is 20 pF.
Figure 25. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)
17
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20-Bit, MSB-First, Right-Justified
LRCK Right-ChannelLeft-Channel
BCK
DOUT 20 18 19 20321
MSB LSB
18 19 20321
MSB LSB
FSYNC
24-Bit, MSB-First, Right-Justified
LRCK Right-ChannelLeft-Channel
BCK
DOUT 24 22 23 24321
MSB LSB
22 23 24321
MSB LSB
FSYNC
24-Bit, MSB-First, I2S
LRCK Right-ChannelLeft-Channel
BCK
DOUT 22 23 24321
MSB LSB
22 23 24321
MSB LSB
FSYNC
24-Bit, MSB-First, Left-Justified
BCK
LRCK Right-ChannelLeft-Channel
DOUT 122 23 24321
MSB LSB
22 23 24321
MSB LSB
FSYNC
FORMAT 0: FMT[1:0] = 00
FORMAT 1: FMT[1:0] = 01
FORMAT 2: FMT[1:0] = 10
FORMAT 3: FMT[1:0] = 11
T0016-13
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
Figure 26. Audio Data Format (Master Mode: FSYNC, LRCK, and BCK Work as Outputs)
18
www.ti.com
BCK
FSYNC
LRCK
DOUT
t(CKFS)
t(BCKH)
t(BCKL)
t(CKLR)
t(LRCP)
t(BCKP) t(CKDO) t(LRDO)
0.5 VDD
0.5 VDD
0.5 VDD
0.5 VDD
t(FSYP)
T0018-01
Synchronization With Digital Audio System
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 150 1/(64 f
S
) 1200 nst
(BCKH)
BCK pulse duration, high 75 600 nst
(BCKL)
BCK pulse duration, low 75 600 nst
(CKLR)
Delay time, BCK falling edge to LRCK valid –10 20 nst
(LRCP)
LRCK period 10 1/f
S
80 µst
(CKFS)
Delay time, BCK falling edge to FSYNC valid –10 20 nst
(FSYP)
FSYNC period 5 1/(2 f
S
) 40 µst
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 20 nst
(LRDO)
Delay time, LRCK edge to DOUT valid –10 20 nst
r
Rise time of all signals 10 nst
f
Fall time of all signals 10 ns
NOTE: Timing measurement reference level is (V
IH
+ V
IL
) / 2. Rise and fall times are measured from 10% to 90% of IN/OUTsignal swing. Load capacitance of all signals is 20 pF.
Figure 27. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK Work as Outputs)
In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 doesnot need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCKand SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame ( ±5 BCKs for48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within1/f
S
and digital output is forced into BPZ code until resynchronization between LRCK and SCKI is completed.
In the case of changes less than ±5 BCKs for 64 BCK/frame ( ±4 BCKs for 48 BCK/frame), resynchronizationdoes not occur.
Figure 28 illustrates the digital output response for loss of synchronization and resynchronization. Duringundefined data, some noise might be generated in the audio signal. Also, the transition of normal to undefineddata and undefined or zero data to normal creates a data discontinuity in the digital output, which can generatesome noise in the audio signal.
19
www.ti.com
1/fS32/fS
NORMAL DATAZERO DATA
UNDEFINED
DATA
NORMAL DATA
SYNCHRONOUSASYNCHRONOUSSYNCHRONOUS
Resynchronization
Synchronization Lost
DOUT
State of Synchronization
T0020-05
Power Down, HPF Bypass, Oversampling Control
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
It is recommended to set PDWN low to get stable analog performance when the sampling rate, interface mode,data format, or oversampling control is changed.
Figure 28. ADC Digital Output for Loss of Synchronization and Resynchronization
PDWN (pin 7) controls the entire ADC operation. During power-down mode, both the supply current for theanalog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized.Also, DOUT (pin 12) is disabled and no system clock is accepted during power-down mode.
Power-Down Control
PDWN MODE
LOW Power-down modeHIGH Normal operation mode
The built-in function for dc component rejection can be bypassed using the BYPAS (pin 8) control. In bypassmode, the dc components of the analog input signal, internal dc offset, etc., are also converted and included inthe digital output data.
HPF Bypass Control
BYPAS HPF (HIGH-PASS FILTER) MODE
LOW Normal (no dc component on DOUT) modeHIGH Bypass (dc component on DOUT) mode
OSR (pin 16) controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode isavailable for f
S
< 50 kHz, and must be used carefully as performance is affected by the duty cycle of the 384 f
Ssystem clock.
Oversampling Control
OSR OVERSAMPLING RATIO
LOW ×64HIGH ×128 (f
S
< 50 kHz)
20
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APPLICATION INFORMATION
Typical Circuit Connection Diagram
VINL20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
PCM1802
VINR
VREF1
VREF2
VCC
AGND
PDWN
BYPAS
FSYNC
LRCK
MODE1
DGND
MODE0
FMT1
FMT0
OSR
DOUT
BCK
VDD
SCKI
+Oversampling
System Clock
L-Ch IN
R-Ch IN
0 V
5 V C4(2)
C5(3)
Power Down
LCF Bypass
Control +C3(2)
L/R Clock
Frame Sync.
Audio Data
Processor
Mode [1:0]
Format [1:0]
3.3 V
0 V
Data Clock
Data Out
C1(1)
C2(1)
Control
C6(4)
R1(5)
S0026-02
+
+
+
+
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
Figure 29 illustrates a typical circuit connection diagram in which the cutoff frequency of the input HPF is about8 Hz.
(1) C
1
, C
2
: A 1- µF capacitor gives 8-Hz ( τ= 1 µF×20 k Ω) cutoff frequency for input HPF in normal operation andrequires a power-on settling time with a 20-ms time constant during the power-on initialization period.(2) C
3
, C
4
: Bypass capacitors, 0.1- µF ceramic and 10- µF tantalum, depending on layout and power supply(3) C
5
: 0.1- µF ceramic and 10- µF tantalum capacitors are recommended.(4) C
6
: 0.1- µF ceramic and 10- µF tantalum capacitors are recommended when using a noisy analog power supply. Thesecapacitor are not required for a clean analog supply.(5) R
1
: A 1-k Ωresistor is recommended when using a noisy analog power supply. This resistor is shorted for a cleananalog supply.
Figure 29. Typical Circuit Connection
21
www.ti.com
Board Design and Layout Considerations
V
CC
, V
DD
Pins
AGND, DGND Pins
V
IN
Pins
V
REF
1 Pin
V
REF
2 Pin
DOUT Pin
System Clock
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
The digital and analog power supply lines to the PCM1802 should be bypassed to the corresponding ground pinswith 0.1- µF ceramic and 10- µF tantalum capacitors as close to the pins as possible to maximize the dynamicperformance of the ADC.
To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connectedinternally. These grounds should have low impedance to avoid digital noise feeding back into the analog ground.They should be connected directly to each other under the parts to reduce the potential noise problem.
A 1- µF capacitor is recommended as an ac-coupling capacitor, which gives an 8-Hz cutoff frequency. If a higherfull-scale input voltage is required, it can be accommodated by adding only one series resistor to each V
IN
pin.
A ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF are recommended between V
REF
1 andAGND to ensure low source impedance for the ADC references. These capacitors should be located as close aspossible to the V
REF
1 pin to reduce dynamic errors on the ADC references.
The differential voltage between V
REF
2 and AGND sets the analog input full-scale range. A ceramic capacitor of0.1 µF and an electrolytic capacitor of 10 µF are recommended between V
REF
2 and AGND with the insertion of a1-k Ωresistor between V
CC
and V
REF
2 when using a noisy analog power supply. These capacitors and resistorare not required for a clean analog supply. These capacitors should be located as close as possible to the V
REF
2pin to reduce dynamic errors on the ADC references. Full-scale input level is affected by this 1-k Ωresistor,decreasing by 3%.
The DOUT pin has enough load drive capability, but locating a buffer near the PCM1802 and minimizing loadcapacitance is recommended if the DOUT line is long, in order to minimize the digital-analog crosstalk andmaximize the dynamic performance of the ADC.
The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on thesystem clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the timedifference between the system clock transition and the BCK or LRCK transition.
22
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jun-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1802DB ACTIVE SSOP DB 20 65 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCM1802DBG4 ACTIVE SSOP DB 20 65 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCM1802DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCM1802DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCM1802S1DB OBSOLETE SSOP DB 20 TBD Call TI Call TI Samples Not Available
PCM1802S1DBG4 OBSOLETE SSOP DB 20 TBD Call TI Call TI Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jun-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1802DBR SSOP DB 20 2000 330.0 17.4 8.5 7.6 2.4 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1802DBR SSOP DB 20 2000 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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