General Information - Lattice Semiconductor

Lattice Semiconductor Corporation • March 2003 • Volume 8, Number 3

In This Issue

Lattice Offers Broadest

Range of sysHSI™

SERDES Devices

ispGAL®22V10A: World’s

Fastest and Smallest PLD

PAC-Designer® v.2.0

Released

ispLEVER™ v.3.0

Maximizes Design

Efficiency

Advances in ispVM™

System Programming

Technology

New USB-Compatible

ispDOWNLOAD® Cable

Application Example:

Lattice Non-volatile

Technology Supports

Hot Socketing

New Flash Demos on

Lattice Web Site

Lattice Listens

Lattice Literature

Electronics Design and

Solution Fair 2003

Lattice Blasts Into Portable Market

with ispMACH 4000Z Family

Industry’s Lowest Power CPLD Family Ideal for Battery-

Based Products, Portable and Handheld Electronics

(Please See Page 2)

(Please See Page 5)

The ispMACH 4000Z ’s power consumption

is just 20% of today’s low power CPLDs!

Lattice recently announced the immediate

availability of the first member of its 1.8V

ispMACH 4000Z CPLD. This family sets a

new standard for the industry’s lowest static

power consumption. The ispMACH 4032Z

device is the first of three initial ispMACH

4000Z devices which span logic capacities

from 32 to 128 macrocells. These break-

through devices provide extremely low static

current consumption (20 microamps, maxi-

mum for a 32-macrocell device) and cost

effective logic implementation demanded by

handheld and portable applications. By

reducing static power consumption to only

20% of previous devices, the new family

dramatically expands the application scope

of programmable logic in the portable and

handheld arenas and provides new program-

mable solutions within the $6.9 billion

portable consumer semiconductor market as

well as other power-conscious segments.

These ultra-low power features are also

coupled with high-speed operation: the

ispMACH 4032Z device provides 3.5ns pin-

to-pin delay (tPD), 3.0ns clock-to-output

delay (tCO), 2.2ns setup time (tS), and

265MHz operating frequencies (fMAX).

Lattice has launched a revolutionary new

family of ispPAC® devices for power man-

agement. These are the industry’s first

mixed-signal PLDs. Featuring in-system

programmable analog and logic blocks, the

new devices provide optimized power supply

management functions critical to the opera-

tion of today’s multiple power supply elec-

tronic systems and provide unique program-

mable control solutions within the $12 billion

power semiconductor market. Through a

combination of programmable logic, voltage

comparators, references, and high voltage

Lattice Launches First Mixed-Signal PLDs, Opening

Power Management Market

FET drivers, the devices support single-chip

programmable power supply sequencing

and monitoring.

Many advanced integrated circuits such as

microprocessors, DSPs, FPGAs and ASICs

employ multiple power supply voltages to

maximize performance while minimizing

power consumption. These voltages must be

applied to the devices and removed in pre-

defined sequences to avoid damaging the

devices. The first device in this new ispPAC

family, the ispPAC-POWR1208, integrates

Lattice’s industry-leading ispMACH CPLD

March 2003/Page 2 Bringing the Best Together www.latticesemi.com

(ispMACH 4000Z, Continued From Page 1)

Industry’s Lowest Static Power

Consumption / Fastest Performance

Standby time is a key design

requirement for portable and handheld

equipment. Designers want to mini-

mize the standby or static power

associated with logic within their

designs to maximize the interval

between battery charges or replace-

ment. In designing the ispMACH

4000Z, Lattice took its popular

ispMACH 4000 architecture, re-

optimized its non-volatile E2CMOS®

process technology and redesigned

key circuit elements to reduce static

power by more than a factor of 50. As

a result, the maximum static current

consumption for devices in the family

ranges from 20 to 30 µA over the

commercial operating temperature

range, while still maintaining the

industry’s fastest performance for a

low-power CPLD solution.

Power Supply and I/O Standard

Support

The ispMACH 4000Z operates from

a nominal 1.8V power supply with

operation extended down to 1.5V,

accommodating the end of battery life

voltage of certain systems. The

ispMACH 4000Z devices have two I/O

banks, each with their own power

supply voltage that can be set at the

appropriate voltage to support LVTTL

and LVCMOS 3.3, 2.5, and 1.8V

outputs. The device input buffers have

programmable thresholds that support

the above standards independent of

the I/O bank voltage. Extended range

3.3V I/O are supported instead of the

more common narrow range version of

the standard, again accommodating

the end of battery life voltages associ-

ated with certain systems. The I/Os on

the ispMACH 4000Z are also 5V

tolerant to facilitate connection to

legacy chips and interfaces

All ispMACH 4000Z devices are

Boundary Scan testable and in-system

programmable through an IEEE 1532-

compliant JTAG boundary scan (IEEE

1149.1) interface.

Design Tools

The ispMACH 4000 product line is

supported by Lattice’s new ispLEVER

design tools. The ispLEVER tools,

Lattice’s platform for next-generation

logic design, provide designers with

rapid access to the performance of the

ispMACH 4000Z devices while maxi-

mizing resource utilization. This is

achieved through timing-driven

placement and routing coupled with

optimized synthesis support from

vendors such as Exemplar and

Synplicity. Additional third-party EDA

tool support is provided through

industry standard EDIF netlist import

and export. The ispLEVER software is

available in PC as well as UNIX

workstation versions.

Availability

The ispMACH 4032Z is available

now in 48-pin TQFP and space-saving

0.8 millimeter ball pitch 49-ball chip

array Ball Grid Array (caBGA) pack-

ages in commercial, industrial and

automotive temperature options.

These small PCB-footprint packages,

with body sizes only 7 millimeters

square, are supported to satisfy the

tight space constraints often found

with portable and handheld equip-

ment. The ispMACH 4000Z family also

supports system designers’ needs for

density migration within a common

package/pinout footprint. ispMACH

4000Z devices are also pin-compatible

with ispMACH 4000C devices in

corresponding packages. The balance

of the ispMACH 4000Z devices are

expected to be released mid-2003.

Macrocells

User I/O Options

tPD (ns)

tS (ns)

tCO (ns)

fMAX (Toggle)

VCC (V)

Max. Standby Current (µA)

Packages

Feature

ispMACH

4032ZC

ispMACH

4064ZC

ispMACH

4128ZC

3.5

3.0

2.2

265

1.8

49 caBGA

48 TQFP

1. Preliminary information.

2. Advance information.

32/64

4.0

3.4

2.5

232

1.8

49 caBGA

48 TQFP

100 TQFP

128

64/92

4.5

3.9

2.8

206

1.8

100 TQFP

128 TQFP

150

Competitive

1.8V Device

Lattice 1.8V

ispMACH 4032Z

100

200

40µW

Static Power (µW)

< 190µW

Static Power:

5x Lattice Device

Spring 1999 / Page 3

www.latticesemi.com Bringing the Best Together March 2003/Page 3

Lattice Offers Leading Performance Programmable sysHSI SERDES in its

FPSC, FPGA and Digital Crosspoint Switch Devices

Lattice has implemented advanced

sysHSI SERDES technologies in a

broad portfolio of programmable

devices. High performance SERDES

are integrated into Lattice’s innovative

Field Programmable System Chip

(FPSC) devices. A cost-optimized

SERDES is included in Lattice’s

ispGDX2™ and ispXPGA families.

Lattice’s ORCA® FPSCs offer the

industry’s widest range of SERDES

capabilities along with hundreds of

thousands of programmable gates.

The ORT8850 offers eight SERDES

channels operating from 126-850Mbps

on each channel along with embedded

pseudo-SONET framing, TOH inser-

tion/extraction and multi-channel

alignment.

The ORSO82G5 has eight SERDES

channels, each operating from

600Mbps to 2.7Gbps along with

embedded pseudo-SONET framing,

TOH insertion/extraction, multi-

channel alignment, and payload

processing.

The flagship of Lattice’s FPSC

offering is the ORT82G5, featuring

eight SERDES channels each operat-

ing from 600Mbps to 3.7Gbps along

with 8b/10b encoding XAUI and Fibre

Channel link state machines and multi-

channel alignment.

The range of operating speeds

available means Lattice offers the

widest selection of programmable

solutions for sysHSI SERDES-based

applications.

The SERDES in the ORSO82G5

and ORT82G5 recently was rated to

run at 600Mbps which allows these

devices to interoperate with a wide

variety of legacy SERDES devices to

implement high-speed backplanes. By

using ORCA FPSCs, users can be

assured that their backplane invest-

Bandwidth

per Channel

Aggregate Bandwidth

per Device

Programmable

Digital Interconnect

+ SERDES

FPGA + SERDES FPGA +

Embedded Interface

Cores + SERDES

World’s largest selection of

programmable SERDES!

850Mbps

2.7Gbps

3.7Gbps

15G

30G

ispGDX2

256

ispGDX2

128

ispGDX2

Channel

ispXPGA

500

Channel

ispXPGA

1200

Channel

ispXPGA

200

ispXPGA

125

Channel

ORCA

ORT8850

Channel

ORCA

ORT82G5

ORCA

ORSO

82G5

Channel

ment will be secure for existing and

future-generation systems.

The ispGDX2 family is Lattice’s next

generation In-System Programmable

(ISP™) high performance digital

crosspoint switch for high-speed bus

switching and interfacing with band-

width of up to 38Gbps. This family

offers built-in 850Mbps SERDES

channels ranging from 4-16 channels.

The ispXPGA™ family is the world’s

first non-volatile and infinitely

reconfigurable FPGA that offers up to

20 sysHSI SERDES channels running

at 850Mbps.

For further information about these

device families, visit the Lattice web

site at www.latticesemi.com or contact

your local Lattice sales representative.

OC-3

OC-12

OC-48

Fibre Channel (1Gb)

Fibre Channel (2Gb)

Gigabit Ethernet

XAUI

Cost-optimized SERDES

(400 to 850Mbps)

Standards Supported ORT8850 ORT82G5 ORSO82G5 ispXPGA ispGDX2

March 2003/Page 4 Bringing the Best Together www.latticesemi.com

Lattice has announced the immediate

availability of its ispGAL22V10A high

performance in-system programmable

(ISP) E2CMOS simple PLD (SPLD)

family. The ispGAL22V10A family of

devices couples industry-leading

performance of up to 455MHz operat-

ing frequencies (fMAX), 2.3ns pin-to-pin

delays (tPD) and low standby power

(<300µW) while supporting I/O stan-

dards of 3.3, 2.5 and 1.8 volts. The

ispGAL22V10A family is offered in the

32-pin QFN (Quad Flat-pack No-lead)

package along with a traditional 28-pin

plastic leaded chip carrier (PLCC)

version. The 32-pin QFN is 84%

smaller (5mm x 5mm) than traditional

packaging, which makes it ideal for

high-density PCBs used in small-scale

electronic applications such as cellular

phones, pagers and PDAs.

The ispGAL22V10AC is the

industry’s first 1.8V in-system pro-

grammable SPLD. The family is also

offered in 2.5V and 3.3V power supply

versions, designated as the

ispGAL22V10AB and

ispGAL22V10AV, respectively. The

ispGAL22V10A family provides

enhanced I/O support including

LVCMOS 3.3V, 2.5V and 1.8V. For

devices in the QFN package, output

voltage is independent of core supply

voltage through the use of a separate

VCCO connection. The I/Os on the

ispGAL22V10A family are 5V tolerant

to facilitate connection to legacy chips

and interfaces.

The ispGAL22V10A family of

devices delivers high speed perfor-

mance and low standby current in

space-saving 32-pin QFN packaging.

With advanced E2 low-power cell and

full CMOS design approach, the

ispGAL22V10A family offers the

highest-performance, while simulta-

neously delivering low standby power.

Highest Performance

In the 32-pin QFN package, the

ispGAL22V10A provides 2.3ns pin-to-

pin delay (tPD), 2.0ns clock-to-output

delay (tCO), 1.3ns set-up time (tSU)

and 455MHz operating frequencies

Lattice Releases ispGAL22V10A: World’s Fastest and Smallest PLD

The industry’s first low power, 1.8V in-system programmable simple PLD

is available in the space-saving 32-Pin QFN package.

(fMAX). Lattice’s previous generation of

GAL22LV10s were the fastest low

voltage 22V10s in the market at 4ns

tPD. The new ispGALV22V10A family

at 2.3ns is 43% faster than the earlier

GAL22LV10 and 77% faster than

available competitive devices.

Space-Saving QFN Package

The ispGAL22V10A family is offered

in the space-saving 32-pin QFN (Quad

Flat-pack No-lead) package, a tech-

nology based on chip scale packaging.

The 32-pin QFN is 84% smaller (5mm

x 5mm), 80% thinner (0.9mm) and

95% lighter (0.06 grams) and offers

significantly better electrical packaging

parasitics than the 28-pin PLCC

package.

Software Support

The ispGAL22V10A family is

supported by Lattice’s new software

platform ispLEVER v.3.0. Program-

ming support is available through

Lattice’s ispVM v.13.0 software, which

may be downloaded from the Lattice

web site at www.latticesemi.com.

Availability

The ispGAL22V10A family of

devices is available now in the 28-pin

PLCC package as well as the space

saving 32-pin QFN package.

Length/Width (mm)

Thickness (mm)

Weight (g)

Thermal Resistance, Junction to Ambient (θ

)

Thermal Resistance, Junction to Board (θ

)

Inductance (nH)

Resistance (MΩ)

Capacitance (pF)

Lead/Pad Pitch (mm)

28-Pin PLCC 32-Pin QFN

12.45

4.37

1.13

56°C/W

28°C/W

0.70

1.27

0.90

0.06

35°C/W

13.4°C/W

1.15

0.25

0.50

1. When die paddle is soldered to PCB.

2. On a per-pin basis.

QFN Package Comparison

Spring 1999 / Page 5

www.latticesemi.com Bringing the Best Together March 2003/Page 5

and ispPAC programmable analog

technologies, resulting in a single chip

that implements a flexible, cost

effective, and convenient solution for

this problem. With a “supply-rugge-

dized” ispMACH PLD at its core, the

ispPAC-POWR1208 device features

12 precision analog threshold com-

parators with on-chip voltage refer-

ences for supply monitoring, four

noise-immune digital inputs and four

open-drain digital outputs for system

control interfacing, four programmable

(both maximum voltage and ramp

rate) high voltage FET drivers for

supply control and four programmable

timers with an on-chip 250kHz oscilla-

tor for delay control. The device has

been ruggedized to operate in noisy

power supply environments from

2.25V to 5.5V and is packaged in a

44-pin Thin Quad Flat Pack (TQFP)

package.

“Controlling multiple supply voltages

as required by most advanced inte-

grated circuits today is complicated

and a burden for today’s designers,”

said Stan Kopec, vice president of

corporate marketing for Lattice. “The

ispPAC-POWR1208 single-chip

programmable solution provides

unprecedented convenience for power

supply management on any circuit

board and expands the programmable

market into a major, untapped seg-

ment. Our PAC-Designer PC-based

software makes using this

incredible capability a snap.”

ispPAC-POWR1208

Applications

The ispPAC-POWR1208

features make it ideal for

controlling multiple power

supplies. As such, its applica-

tions span all types of electronic

equipment, including telecom

and networking systems,

storage systems, servers, test

equipment and automotive

electronics. Used in conjunction

with N-channel switching FETs

and/or LDO (Low Drop Out)

regulators, the ispPAC-

POWR1208 provides a compact

power supply control solution. It

easily replaces current solutions

using multiple analog and digital

integrated circuits as well as

numerous resistors and capaci-

tors, reducing cost while in-

creasing reliability and flexibility.

Software Support

Power supply sequencing and

monitoring designs can be

implemented on the ispPAC-

POWR1208 device using

Lattice’s popular PAC-Designer

version 2.0 software. The PAC-

Designer software is an intuitive

schematic design entry and simulation

tool. The user can design complex

sequencing and monitoring functional-

ity easily using PAC-Designer’s

newest feature, Logi-

Builder™, which provides

a series of easy-to-use

pull-down menus. Designs

can be completely verified

using the tool’s built-in

waveform simulator. The

free PAC-Designer

software is available for

download from

www.latticesemi.com.

PAC-System

Development Kits

The PACsystem-

POWR1208 is a low cost

development tool de-

signed to enable design-

ers to build quick proto-

types of their circuit implementation

and to check its functionality. The

design implemented using PAC-

Designer is downloaded into the

device through the ispDOWNLOAD

cable that connects to the PC’s

parallel port.

The PACsystemPOWR1208 con-

tains an evaluation board for the

ispPAC-POWR1208, an ispDOWN-

LOAD cable, and PAC-Designer v.2.0

software.

Availability

Samples of the ispPAC-POWR1208

in a 44-pin TQFP package (industrial

temperature grade, -40°C to +85°C)

are available immediately. The order-

ing part number is ispPAC-

POWR1208-01T44I.

PACsystemPOWR1208 evaluation

kits are also available through autho-

rized Lattice distributors or on the

Lattice web site at a suggested retail

price of $149.

The first programmable analog + digital solution!

CAM

(128*48 bit)

CAM

(128*48 bit)

BRICK

LDO

Other

Board

Circuitry

I/P Voltage

Monitoring Sequencing Load Voltage

Monitoring

V1 V2 V3

Power1208

Application

Reset_In CPU_Reset

Brown_Out_NMI

Power_Good

Manual_Shut-Down

Input

Power

Supply

FPGA_Load_Complete

Programmable

Power Supply

Monitor

Digital Signal

Monitor

CPLD

High Voltage

FET Driver/

Digital Output

Programmable

Function

Digital Output

Internal Oscillator & Timers

Power1208 devices sequence

and monitor power supply voltages

and generate supervisory signals

(ispPAC, Continued From Page 1)

March 2003/Page 6 Bringing the Best Together www.latticesemi.com

Lattice’s new PAC-Designer version

2.0 software supports the recently

announced ispPAC Power Manager

series of devices. New features added

to this version, including the Logi-

Builder design entry and Waveform

Simulator modules, greatly simplify the

implementation of power supply

management functions on a printed

circuit board when using the ispPAC

Power1208 and ispPAC Power604

mixed-signal power management

devices.

PAC-Designer’s new LogiBuilder

feature enables the design engineer to

completely define the circuit board’s

power management requirements

(power supply sequencing, monitoring,

and generation of supervisory signals)

using five basic intuitive point-and-

click instructions. The resulting easy-

to-understand program is then com-

piled for the CPLD section of the

ispPAC device. Design engineers can

then quickly verify the LogiBuilder

program using the digital Waveform

Simulator. In-system programming of

the ispPAC device via its boundary

scan port is supported to complete the

concept-to-silicon cycle quickly and

efficiently.

The hierarchical GUI of the PAC-

Designer provides pull-down menus in

the analog interfacing section that

control power supply monitoring

functions as well as the turn-on ramp-

rate of the power FET output drivers.

The software allows the user to

specify analog input thresholds from

1V to 5.75V for each of the ispPAC

device’s analog inputs by selecting

one of 192 levels from a pull-down

menu. Similarly, the analog FET driver

outputs can have their maximum

output voltage (from 8V to 12V) and

gate charging ramp rate specified from

another menu.

“Lattice continues to bring the best

programmable solutions to the mar-

ket,” said Stan Kopec, vice president

of corporate marketing for Lattice. “For

Lattice Announces Design Tool Support for Revolutionary ispPAC Power

Manager Device Family

the first time, complex power manage-

ment challenges precipitated by

modern multi-voltage components can

be addressed easily in software and

silicon with confidence. The flexibility

provided by the integration and

programmability of the ispPAC devices

supports an easy-to-use, standard

approach for the design of power

management functions for any printed

circuit board or system.”

Lattice’s ispPAC Power Manager

devices, the industry’s first mixed-

signal programmable logic devices

(PLDs), were introduced in January,

2003. Featuring in-system program-

mable analog and logic blocks, the

new devices provide optimized power

supply management functions critical

to the operation of today’s multiple

power supply electronic systems and

provide unique programmable control

solutions within the $12 billion power

semiconductor market. Through a

combination of programmable logic,

voltage comparators, references, and

high voltage FET drivers, the devices

support single-chip programmable

power supply sequencing and monitor-

ing.

Lattice’s PAC-Designer version 2.0

software for the PC is available for

download from the Lattice web site at

www.latticesemi.com. In addition to

supporting the newest Power1208 and

Power604 devices, it also supports

Lattice’s five other production ispPAC

devices. Users can get a free six-

month license for PAC-Designer

evaluation.

PAC-Designer’s intuitive design and verification environment

greatly reduces circuit board power supply management design time.

Spring 1999 / Page 7

www.latticesemi.com Bringing the Best Together March 2003/Page 7

The latest release of Lattice’s isp-

LEVER design tools (version 3.0)

includes a number of new enhance-

ments to help improve your efficiency

and design performance.

Revision Control

Large FPGA designs can quickly get

complicated, and the best approach is

not always obvious or definite. There

may be a dozen ways to get optimal

performance out of your design – the

trick is to find one option that works.

The ispLEVER v.3.0 software includes

an integrated revision control system

to help you complete this task.

When you toggle-on the revision

control system, all process tasks are

saved and displayed in a revision

control tree. For example, if you open

a new FPGA project (ispXPGA or

ORCA), turn on the revision control

system, set a list of constraints and

pack & place your design, that process

is saved as a branch in a new revision

control tree (see Figure 1).

Assume that after routing this

design, you’d like to make some

changes to the constraints you initially

set (but you don’t want to lose your

initial constraint settings). Simply go

back to the “Build Database” process

in the revision control tree, make your

constraint changes, and continue with

your design (see Figure 2).

As long as Revision Control is on,

branches will be added automatically

as you run processes in your design.

Going from one branch to another is

as simple as clicking the desired

branch. You can also add descriptive

comments to your revisions to keep

track of your progress. If you decide

any particular path is a “dead end” you

can delete it. The revision control

system can be toggled on or off at any

point in the design process.

Timing Checkpoints

Timing checkpoints are now avail-

able for all FPGA designs. These

checkpoints give you quick feedback

on the probability your design will

meet the timing you need. This

increases the efficiency of the design

cycle by reducing time spent compiling

designs.

New Device Support

ispLEVER v.3.0 includes support for

the latest Lattice FPGA and CPLD

products, including members of the

new ispXPGA and ispXPLD families.

Additionally, support for Lattice ORCA

products has been enhanced in

ispLEVER, completing the integration

of the ORCA Foundry toolset.

Improved Run Time

ispLEVER v.3.0 compiles FPGA

designs an average of 40% faster than

the v.2.0 release. Specific results will

depend on the design in question.

Updated Third-Party Tools

Lattice has included in ispLEVER

v.3.0 the latest synthesis and simula-

tion tools from our partners, Synplicity

and Mentor Graphics. ispLEVER gives

you a complete programmable logic

design package that takes you from

concept to programmed solution.

Choose Your Own Editor

Sometimes it’s the little things that

mean the most! Now you can use your

favorite text editor as the default

ispLEVER text editor.

Available Now

ispLEVER v.3.0 is available now.

Registered users of Lattice ispLEVER

software with valid maintenance

contracts received their updates in

January 2003. A service pack for

ispLEVER v.3.0, which includes

support for new devices, is now

available for download via ispUPDATE™

or at www.latticesemi.com.The

ispLEVER v.3.0 Starter software is

available for download at

www.latticesemi.com/products/

devtools/software/ispLEVER-starter/

index.cfm.

Next Generation ispLEVER v.3.0 Design Tools Maximize Design Efficiency

Figure 1 Figure 2

March 2003/Page 8 Bringing the Best Together www.latticesemi.com

While it only takes a matter of seconds

to program most Lattice devices, some

larger FPGA designs can take a bit

longer to download. In order to keep

device programming times to a

minimum, Lattice now offers a USB-

compatible ispDOWNLOAD cable.

The Lattice USB download cable

offers up to a 3x improvement in data

transfer speed compared to parallel

port cables (actual download speed

improvement will vary according to the

setup involved). Additionally, the

Lattice USB download cable includes

an INIT feedback pin to help verify

FPGA downloads.

Like all USB products, the Lattice

USB download cable is plug-and-play

ready. Lattice’s ispVM System v.13.0

or later includes the necessary drivers

and other software support for the

Lattice has expanded the rich feature

set available in its ispVM System

programming software. ispVM System

is loaded with features that handle

everything from a simple device

download, to chain programming, to

ATE programming vector generation.

The new ispVM System v.13.0

includes a new cable signal test

feature. This capability allows you to

test the signal integrity of your pro-

gramming setup/connections. The

interface is a simple software dialog

box that allows you to toggle various

pins connected to your board.

Existing features have also been

enhanced, such as an improved

mechanism for dealing with devices

that have duplicate device IDs.

ispVM System also includes drivers

for the new Lattice USB ispDOWN-

LOAD cable. ispVM System is now

available for PC, UNIX (Solaris 6, 7,

8), and Linux operating systems.

You can download a copy of ispVM

System v.13.0 today at

www.latticesemi.com.

Advances in ispVM System Programming Technology

Cable Signal Test Dialog Box

ispVM System Environment

New USB-Compatible ispDOWNLOAD Cable

USB download cable. The Lattice USB

download cable operates on the USB

1.0 standard, but is USB 2.0 compat-

ible.

The ordering part number for this

product is HW-USB-1A. Contact your

local Lattice sales representative for

complete details.

Spring 1999 / Page 9

www.latticesemi.com Bringing the Best Together March 2003/Page 9

Hot socketing in a system environment

is defined as plugging (or “socketing”)

the printed circuit board into a live

(hot) connector. During this process,

there is no defined sequence of when

the power, ground and I/O connec-

tions will occur. In order for a PCB to

be hot socketable, individual compo-

Lattice Non-volatile Technology Supports Hot Socketing

nents must support the hot socketing

environment. Many recently intro-

duced Lattice products are ideally

suited for this design environment.

For a device to function well in a hot

socketing environment, it is critical that

there are no abnormal current surges

or discontinuity on the I/O pins, and

The Lattice web site now features

several new animated demos utilizing

Flash technology. The demos are an

ideal way to quickly learn about the

features of Lattice’s latest products.

Users who don’t already have the

Flash plug-in necessary to view the

demos can download it from a link on

the Lattice site.

ispPAC Demos

The Power1208 Flash demo de-

scribes the need for power manage-

ment in circuit boards with multi-

voltage devices and how the

Power1208 device, with its integrated

programmable analog and digital

features, is able to offer total power

management.

The PAC-Designer demo shows

how power management designs can

be implemented on a Power1208

device.

sysHSI SERDES Demo

Line cards in today’s communication

systems are being aggressively

pushed to line rates at OC-192 or

10Gbps. Switch fabrics, memory,

framers, and processors have risen to

the challenge of processing bitstreams

at ‘wire speed.’ One area that remains

a potential bottleneck is the system

backplane. Traditionally, parallel

architectures were used to manage

data highways, or backplanes. How-

ever, at OC-192 rates these parallel

backplanes are inefficient due to skew,

crosstalk, and trace count issues.

Serial backplane technologies

transmit the clock embedded in the

data thereby eliminating clock to data

skew issues. This extends the data

transmission rate per PCB trace.

Through this increased rate serial

backplane technologies decrease the

number of I/O pins, PCB traces, and

connectors by factors up to and over

10X.

Lattice, a pioneer in the sysHSI

SERDES market, has met all the

challenges required for truly robust

SERDES capable of industry-best

performance across a variety of

applications. Our new sysHSI

SERDES flash demo highlights

Lattice’s flexible ORT82G5 high-speed

serial solution.

With 8 SERDES running at up to

3.7Gbps, more than 400K FPGA

system gates and operating bandwidth

of 3.7Gbps across 26 inches of FR-4,

no programmable SERDES can drive

as far and as fast as Lattice’s

ORT82G5! Our receive jitter exceeds

the XAUI spec at .65UI and power

consumption is less than 225mW per

channel at 3.125Gbps. With superior

speed, low power, excellent jitter

tolerance, and extended reach, Lattice

is bringing the best sysHSI SERDES

technology together in one easy-to-

use device. Lattice offers a compre-

hensive portfolio of SERDES-based

FPSCs for backplane applications

ranging from XAUI to SONET to 10Gb

Ethernet. If you have a high-speed

backplane challenge, we have an

answer.

Visit the Lattice website at

www.latticesemi.com for additional

information on these and other solu-

tions and check out the Lattice Flash

demos today!

New Flash Demos Available on Lattice Web Site

that no VCC/VCCO sequencing is

required during the power-up or

power-down process. The ispXPGA,

ispXPLD, ispMACH 4000 and

ispGDX2 families are well suited for

applications that require the hot

socketing capability. There is no VCC/

VCCO power-up or power-down

sequence requirement for these

families and the typical input or I/O

leakage current is in the µA range per

pin during power sequencing. Refer to

the Hot Socketing Characteristics

section of individual device data

sheets for specific information. In

addition, the instant-on feature of the

E2CMOS and ispXP™ technologies

used by these devices is ideal for

implementing functions that generate

the power-up sequencing control and

reset signals.

The ispXP (eXpanded in-system

Programmable) device families from

Lattice offer the non-volatility of E2

cells together with the infinite

reconfigurability of SRAM. This is

achieved by the one-to-one relation-

ship between SRAM memory and E2

cells, where SRAM is used to control

the functionality of the device during

normal operation, and E2 cells are

used to store information for SRAM

configuration. By combining the

strengths of E2 cells and SRAM, the

ispXP device families are able to

provide instant-on logic at power-up,

high security during reconfiguration,

and simplified system design with a

single-chip solution.

Technical note TN1041,

ispXP

Technology Power-up and Hot Socket-

ing,

addresses the power sequencing

characteristics of the ispXP devices.

I/O characteristics of the ispXPGA,

ispXPLD™, ispMACH 4000 and

ispGDX2 families during power

sequencing is also discussed. TN1041

is available on the Lattice web site at

www.latticesemi.com.

March 2003/Page 10 Bringing the Best Together www.latticesemi.com

Lattice Listens How to Contact Lattice Applications

Tel: 1-800-LATTICE or (408) 826-6002

e-mail: techsupport@latticesemi.com

http://www.latticesemi.com

Tel: +44 (0)117 934 1600

FAX: +44 (0)117 934 1601

e-mail: euro.lit@latticesemi.com

Technical Support

ResourceInformation Need

Software and Literature Download

European Literature Fulfillment

Is there a Lattice PLD that

supports low standby power

applications?

Lattice recently introduced the

ispMACH 4000Z device for low

standby power applications. The

ispMACH 4000Z family consists of 32,

64 and 128-macrocell devices. The

device specifies the industry’s lowest

standby current at 20µA when the

device I/O pins are in static state.

Which applications best take

advantage of the ispXPLD

5000MX device features?

sysCLOCK™ PLL, LVDS I/O and

sysMEM™ are three of the most

popular ispXPLD 5000MX device

features used in system designs.

sysCLOCK PLL gives the user the

ability to adjust the phase to optimize

setup/hold time and clock-to-output

time of the system design. The PLL

also supports the frequency range

from 10MHz to 320MHz with the ability

to multiply and divide the frequency

within the input and output frequency

ranges.

The ispXPLD 5000MX has a unique

LVDS I/O feature that supports the

LVDS standard with both 2.5V and

3.3V VCCO settings. This feature gives

the user the flexibility to run the LVDS

interface from either power supply.

A total of 16K bits of memory per

MFB (Multi-Function Block) provides

the ability to buffer data along with the

logic design in a single device. The

memory can be configured as Single

Port, Dual Port, FIFO or CAM.

What software do I need to work

with the ispPAC-POWR1208?

PAC-Designer version 2.0 is the

only software you need to

develop ispPAC-POWR1208 applica-

tions. In addition to providing the point-

and-click schematic-based interface

used with other ispPAC products,

PAC-Designer 2.0 provides the

following new features:

•LogiBuilder: An easy-to-use, menu-

driven system for building control

sequences with conditional tests and

programmable delays.

•Waveform Editor: Define test vectors

for simulation graphically through a

point-and-click interface

•Digital Simulator: Performs func-

tional logic simulation of completed

designs and allows the user to verify

a design’s behavior before testing it

in-system.

• Waveform Viewer: Provides a

graphic waveform-oriented display

of simulation results.

In addition to supporting the isp-

PAC-POWR1208, PAC-Designer 2.0

also supports all other members of

Lattice’s ispPAC family of program-

mable mixed-signal ICs.

The ORT82G5 device contains

eight high-speed SERDES with

programmable serial data rates.

What is the range of operation of

these SERDES? How is the rate

programmed per channel?

The ORT82G5 is made up of

backplane transceivers containing

eight channels, each operating at up

to 3.7Gbps with a full-duplex synchro-

nous interface with built-in clock

recovery (CDR). The SERDES portion

of the core contains two quad trans-

ceiver blocks for serial data transmis-

sion at a selectable data rate of

0.6Gbps to 3.7Gbps.

The 0.6Gbps to 3.7Gbps range per

channel is achieved as follows. The bit

rate is 10 times the reference clock

frequency in half-rate mode, and 20

times the frequency in full-rate mode.

Since the range of reference clock

frequencies is 60MHz to 185MHz, the

half rate range extends between

0.6Gbps and 1.85Gbps, while the full

rate range extends between 1.2Gbps

and 3.7Gbps.

The selection of full-rate or half-rate

for a given reference clock is set in the

transmit and receive control registers

on a per channel basis. Setting bit 0 of

any of the eight transmit control words

independently enables half-rate mode

in the transmit direction of that chan-

nel. Setting bit 0 of any of the eight

receive control words independently

enables half-rate mode in the receive

direction of that channel.

Lattice’s

SERDES Handbook

is a

valuable resource for further informa-

tion. It contains a product brief dis-

cussing the ORT82G5 evaluation

board and design kit, in addition to

applications and performance mea-

surements in a lab environment. The

SERDES Handbook

is available in

PDF format on the Lattice web site at

www.latticesemi.com.

Spring 1999 / Page 11

www.latticesemi.com Bringing the Best Together March 2003/Page 11

Lattice Literature

The following is a list of recently published documents, including descriptions and ordering numbers. On-line versions of

these technical publications are available on the Lattice web site at www.latticesemi.com. Some of these documents are

available on CD or in print. To order print versions, call your local Lattice representative or Lattice’s Literature Distribution

Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In

Europe, contact Lattice’s European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at

+44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.

Title Description

Introduction to Lattice’s new ispXP (eXpanded Programmability) technology

that combines the best features of E2 and SRAM technologies.

Overview of the the industry’s lowest power CPLD family.

Introduction to the industry’s first mixed-signal PLDs.

Order #

Web

Order #

Web

Title Description

I0151

I0152

✓

✓I0155

ispXP Product Brief

ispMACH 4000Z Product Brief

ispPAC Power Manager

Product Brief

3.3/2.5/1.8V in-system programmable SuperFAST high density PLDs.

In-system programmable power supply sequencing controller and monitor.

Industry’s first 1.8V in-system programmable SPLD in space-saving

5mm x 5mm QFN package.

—

✓

—

✓

Data Sheets

General Information

ispMACH 4000Z Family Data Sheet

ispPAC-POWR1208 Data Sheet

ispGAL22V10AC/B/C Data Sheet

✓

Order #

Web

Title Description

Shows how the ispGDX2 can be used in multiport applications.

Provides a method for implementing increased hysteresis and a few of

the design issues associated with successful implementation.

Describes the ispPAC-POWR1208-EV evalution board for quick configuration

and evaluation of the ispPAC-POWR1208 device on a fully-assembled PCB.

Illustrates how PAC-Designer’s LogiBuilder system can be used to develop

power supply control logic to be implemented in the ispPAC-POWR1208

device. An example design introduces the capabilities of LogiBuilder and

its Sequence Control instruction set.

Describes the function of the ispPAC-POWR1208’s MOSFET output drivers

which support soft-start switching capabilities that help to reduce power supply

transients resulting from large, uncontrolled current surges.

Explains how to use the ispPAC-POWR1208 to monitor positive and negative

power supplies that exceed the normal input range.

Describes several issues associated with controlling modular DC-to-DC

converters and presents example circuits for for interfacing the

ispPAC-POWR1208’s digital outputs to other devices.

Discusses the output pin modes and characteristics of the ispPAC-POWR1208

during programming and power up.

Demonstrates how the Power1208 can be interfaced to common MOSFETs

and some of the criteria for selecting suitable devices.

Presents several ispPAC-POWR 1208-compatible methods of sensing

electrical current in low-voltage positive power supply lines.

Step-by-step procedure for simulating ispPAC-POWR1208 designs

developed in the PAC-Designer LogiBuilder system. Describes the tools

necessary to edit a stimulus file and analyze the output.

—

✓

—

✓

—

✓

—

✓

—

✓

—

✓

—

✓

—

✓

—

✓

Application Notes

ispGDX2 Multiple Port Interface

Simulating Power Supply Sequences

for the ispPAC-POWR1208 Using

Pac-Designer LogiBuilder

Adding More Hysteresis to the

ispPAC-POWR1208 Analog

Comparators

ispPAC-POWR1208 Evaluation

Board ispPAC-POWR1208-EV

Implementing Power Supply

Sequencers with the

ispPAC-POWR1208 and

PAC-Designer

Using the ispPAC-POWR1208

MOSFET Driver Outputs

Extending the Input Range of

the ispPAC-POWR1208

Interfacing the ispPAC-POWR1208

with Modular DC-to-DC Converters

Powering Up and Programming

the ispPAC-POWR1208

Using Power MOSFETs with the

Lattice ispPAC-POWR1208

High-side Current Sensing

Techniques for the

ispPAC-POWR1208

March 2003/Page 12 Bringing the Best Together www.latticesemi.com

Order #: NL0103

Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), E2CMOS, In-System Programmable, In-System

Programmability, ISP, ispDOWNLOAD, ispGAL, ispGDX, ispGDX2, ispLEVER, ispMACH, ispPAC, ispUPDATE, ispVM, ispXP, ispXPGA, ispXPLD, LogiBuilder, MMI (logo),

ORCA, PAC-Designer, Silicon Forest, sysCLOCK, sysHSI, sysMEM, V Vantis (design), Vantis and Vantis (design) are either registered trademarks or trademarks of Lattice

Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP is a service mark of Lattice Semiconductor Corporation.

Synplicity and Synplify are registered trademarks of Synplicity, Inc. Mentor Graphics, LeonardoSpectrum and ModelSim are either registered trademarks or trademarks of

Mentor Graphics Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

LatticeNEWS

is a publication of Lattice Semiconductor Corporation, 5555 N.E. Moore Ct., Hillsboro, OR 97124 USA

Lattice Literature (Continued)

Order #

Web

Title Description

Explores the power-up characteristics of ispXP devices and the I/O

characteristics of the latest Lattice device families.

ispGDX2 pin locking recommendations in two areas: one associated

with sysIO banks and the other with routing architecture

—

✓

Technical Notes

ispXP Technology Power-up

and Hot Socketing

ispGDX2 Pin Locking

Recommendations

Order #

Web

Title Description

Presents an example circuit for the Power1208. —

—

✓

Circuit Solutions

Power-safe Programming

Circuit for the ispPAC-POWR1208

Lattice Semiconductor Japan partici-

pated in the Electronics Design and

Solution Fair (EDSF) January 30-31 in

Yokohama, Japan. This year’s event

was by far the most exciting, in terms

of the number of companies participat-

ing and the quality of exhibitions, since

the fair was established in 1993.

The exhibitions were categorized

into four major sections: design tools,

system LSI (FPGA/CPLD), design

support and PR. The FPGA/PLD

Design Conference was also a popular

venue and 13 sessions were pre-

sented during the two-day event.

Lattice’s booth was one of the most

popular. The 3.7Gbps SERDES demo

running in the booth was clearly an

overwhelming favorite. The new

ispPAC Power Manager was also

demonstrated. Participants were eager

to learn what this new device can do

for their multi-voltage PCB boards.

Lattice Japanese Country Manager,

John Charles says, “It’s difficult to

impress Japanese engineers. Lattice

presented the industry’s leading high-

speed SERDES performance. These

engineers were impressed!”

You can read more about EDSF at

www.edsfair.com.

Electronics Design and Solution Fair 2003 a Success