1
Features
•Industry-standard Architecture
– Emulates Many 24-pin PALs®
– Low-cost Easy-to-use Software Tools
•High-speed Electrically-erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
•Several Power Saving Options
•CMOS and TTL Compatible Inputs and Outputs
•Input and I/O Pull-up Resistors
•Advanced Flash Technology
– Reprogrammable
– 100% Tested
•High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
•Commercial and Industrial Temperature Ranges
•Dual-in-line and Surface Mount Packages in Standard Pinouts
•PCI-Compliant
•Green Package Options (Pb/Halide-free/RoHS Complant) Available
Block Diagram
Device ICC, Standby ICC, Active
ATF20V8B 50 mA 55 mA
ATF20V8BQ 35 mA 40 mA
ATF20V8BQL 5 mA 20 mA
High-
performance
EE PLD
ATF20V8B
ATF20V8BQ
ATF20V8BQL
Rev. 0407J–07/06
Pin Configurations
All Pinouts Top View
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bi-directional Buffers
OE Output Enable
* No Internal Connection
VCC +5V Supply
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
PLCC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
*
IN
IN
IN
I/O
I/O
I/O
*
I/O
I/O
I/O
4
3
2
1
28
27
26
12
13
14
15
16
17
18
IN
IN
GND
*
OE/IN
IN
I/O
IN
IN
CLK/IN
*
VCC
IN
I/O
ATF20V8B(Q)(L)
2
Description
The ATF20V8B is a high-performance CMOS (electrically-
erasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically-erasable Flash memory technol-
ogy. Speeds down to 7.5 ns and power dissipation as low
as 10 mA are offered. All speed ranges are specified over
the full 5V ± 10% range for industrial temperature ranges,
and 5V ± 5% for commercial temperature ranges.
Several low-power options allow selection of the best solu-
tion for various types of power-limited applications. Each of
these options significantly reduces total system power and
enhances system reliability.
The ATF20V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 20R8
family and most 24-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft-
ware, allow highly complex logic functions to be realized.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maxi-
mum output pin voltage is VCC + 0.75V DC which
may overshoot to 7.0V for pulses of less than 20
ns.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C
VCC Power Supply 5V ± 5% 5V ± 10%
ATF20V8B(Q)(L)
3
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL
Input or I/O Low
Leakage Current 0 ≤ VIN ≤ VIL(Max) -35 -100 µA
IIH
Input or I/O High
Leakage Current 3.5 ≤ VIN ≤ VCC 10 µA
ICC
Power Supply
Current, Standby
VCC = Max,
VIN = Max,
Outputs Open
B-7, -10 Com. 60 90 mA
Ind. 60 100 mA
B-15 Com. 60 80 mA
B-15 Ind. 60 90 mA
B-25 Com. 60 80 mA
B-25 Ind. 60 90 mA
BQ-10 Com. 35 55 mA
BQL-15 Com. 5 10 mA
BQL-15 Ind. 5 15 mA
BQL-25 Com. 510 mA
BQL-25 Ind. 515 mA
ICC2
Clocked Power
Supply Current
VCC = Max,
Outputs Open,
f = 15 MHz
B-7, -10 Com. 80 110 mA
Ind. 80 125 mA
B-15 Com. 60 90 mA
B-15 Ind. 60 105 mA
B-25 Com. 60 90 mA
B-25 Ind. 60 105 mA
BQ-10 Com. 40 55 mA
BQL-15 Com. 20 35 mA
BQL-15 Ind. 20 40 mA
BQL-25 Com. 20 35 mA
BQL-25 Ind. 20 40 mA
IOS(1) Output Short
Circuit Current VOUT = 0.5V -130 mA
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 VCC + 0.75 V
VOL Output Low Voltage VIN = VIH or VIL,
VCC = Min
IOL = 24 mA Com.,
Ind. 0.5 V
IOL = 16 mA 0.5 V
VOH Output High Voltage VIN = VIH or VIL,
VCC = Min IOH = -4.0 mA 2.4 V
ATF20V8B(Q)(L)
4
AC Waveforms(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
Note: 1. See ordering information for valid part numbers and speed grades.
2. Shaded -25 parts are obsolete with a last-time buy date of August 19, 1999.
3. Shaded -7 and -15 parts are obsolete with a last-time buy date of September 30, 2006.
AC Characteristics(1)
Symbol Parameter
-7 -10 -15 -25
Units
Min Max Min Max Min Max Min Max
tPD
Input or Feedback to
Non-Registered Output
8 outputs switching 37.5 3 10 315 325 ns
1 output switching 7ns
tCF Clock to Feedback 36810 ns
tCO Clock to Output 2527210 212 ns
tS
Input or Feedback
Setup Time 57.5 12 15 ns
tHHold Time 0 0 0 0 ns
tPClock Period 812 16 24 ns
tWClock Width 46812 ns
fMAX
External Feedback 1/(tS + tCO)100 68 45 37 MHz
Internal Feedback 1/(tS + tCF)125 74 50 40 MHz
No Feedback 1/(tP)125 83 62 41 MHz
tEA Input to Output Enable — Product Term 39310315 320 ns
tER Input to Output Disable —Product Term 29210215 220 ns
tPZX OE pin to Output Enable 26210215 220 ns
tPXZ OE pin to Output Disable 1.5 61.5101.5 15 1.5 20 ns
ATF20V8B(Q)(L)
5
Input Test Waveforms and
Measurement Levels
tR, tF < 5 ns (10% to 90%)
Output Test Loads
Commercial
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3. The clock must remain stable during tPR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ Max Units Conditions
CIN 58 pF V
IN = 0V
COUT 68 pF V
OUT = 0V
Parameter Description Typ Max Units
tPR Power-up Reset Time 600 1,000 ns
VRST Power-up Reset Voltage 3.8 4.5 V
ATF20V8B(Q)(L)
6
Input and I/O Pull-ups
All ATF20V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to VCC. This
ensures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).
Input Diagram I/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF20V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.
The ATF20V8B can be configured in one of three different
modes. Each mode makes the ATF20V8B look like a dif-
ferent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter-
mining factors would be the usage of register versus com-
binatorial outputs and dedicated outputs versus outputs
with output enable control.
The ATF20V8B universal architecture can be programmed
to emulate many 24-pin PAL devices. These architectural
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF20V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF20V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessi-
ble regardless of the state of the security fuse.
ATF20V8B(Q)(L)
7
Note: 1. Only applicable for version 3.4 or lower.
ATF20V8B Registered Mode
PAL Device Emulation/PAL Replacement. The registered
mode is used if one or more registers are required. Each
macrocell can be configured as either a registered or com-
binatorial output or I/O, or as an input. For a registered out-
put or I/O, the output is enabled by the OE pin, and the
register is clocked by the CLK pin. Eight product terms are
allocated to the sum term. For a combinatorial output or
I/O, the output enable is controlled by a product term, and
seven product terms are allocated to the sum term. When
the macrocell is configured as an input, the output enable is
permanently disabled.
Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:
20R8 20RP8
20R6 20RP6
20R4 20RP4
Registered Mode Operation
Compiler Mode Selection
Registered Complex Simple Auto Select
ABEL, Atmel-ABEL P20V8R P20V8C P20V8 P20V8
CUPL G20V8MS G20V8MA G20V8 G20V8A
LOG/iC GAL20V8_R(1) GAL20V8_C7(1) GAL20V8_C8(1) GAL20V8
OrCAD-PLD “Registered” “Complex” “Simple” GAL20V8
PLDesigner P20V8 P20V8 P20V8 P20V8
Tango-PLD G20V8 G20V8 G20V8 G20V8
ATF20V8B(Q)(L)
8
Registered Mode Logic Diagram
ATF20V8B(Q)(L)
9
ATF20V8B Complex Mode
PAL Device Emulation/PAL Replacement. In the complex
Mode, combinatorial output and I/O functions are possible.
Pins 1 and 11 are regular inputs to the array. Pins 13
through 18 have pin feedback paths back to the AND-array,
which makes full I/O capability possible. Pins 12 and 19
(outermost macrocells) are outputs only. They do not have
input capability. In this mode, each macrocell has seven
product terms going to the sum term and one product term
enabling the output.
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
20L8
20H8
20P8
Complex Mode Operation
ATF20V8B Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple
Mode, 8 product terms are allocated to the sum term. Pins
15 and 16 (center macrocells) are permanently configured
as combinatorial outputs. Other macrocells can be either
inputs or combinatorial outputs with pin feedback to the
AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combi-
natorial without OE control. The following simple PALs can
be emulated using this mode:
14L8 14H8 14P8
16L6 18H6 16P6
18L4 18H4 18P4
20L2 20H2 20P2
Simple Mode Option
ATF20V8B(Q)(L)
10
Complex Mode Logic Diagram
ATF20V8B(Q)(L)
11
Simple Mode Logic Diagram
ATF20V8B(Q)(L)
12
ATF20V8B(Q)(L)
13
ATF20V8B(Q)(L)
14
ATF20V8B(Q)(L)
15
Note: 1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
ATF20V8B Ordering Information
tPD (ns) tS (ns) tCO (ns) Ordering Code Package Operation Range
7.5 5 5 ATF20V8B-7JC
ATF20V8B-7PC
ATF20V8B-7SC
ATF20V8B-7XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
10 7.5 7 ATF20V8B-10JC
ATF20V8B-10PC
ATF20V8B-10SC
ATF20V8B-10XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF20V8B-10JI
ATF20V8B-10PI
ATF20V8B-10SI
ATF20V8B-10XI
28J
24P3
24S
24X
Industrial
(-40°C to 85°C)
15 12 10 ATF20V8B-15JC
ATF20V8B-15PC
ATF20V8B-15SC
ATF20V8B-15XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF20V8B-15JI
ATF20V8B-15PI
ATF20V8B-15SI
ATF20V8B-15XI
28J
24P3
24S
24X
Industrial
(-40°C to 85°C)
ATF20V8B Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns) tS (ns) tCO (ns) Ordering Code Package Operation Range
10 7.5 7 ATF20V8B-10JU
ATF20V8B-10PU
28J
24P3
Industrial
(-40°C to 85°C)
Package Type
28J 28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24S 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
ATF20V8B(Q)(L)
16
Note: 1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
Note: 1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
ATF20V8BQ and ATF20V8BQL Ordering Information
tPD (ns) tS (ns) tCO (ns) Ordering Code Package Operation Range
10 7.5 7 ATF20V8BQ-10JC
ATF20V8BQ-10PC
ATF20V8BQ-10XC
28J
24P3
24X
Commercial
(0°C to 70°C)
15 12 10 ATF20V8BQL-15JC
ATF20V8BQL-15PC
ATF20V8BQL-15SC
ATF20V8BQL-15XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
15 12 10 ATF20V8BQL-15JI
ATF20V8BQL-15PI
ATF20V8BQL-15SI
ATF20V8BQL-15XI
28J
24P3
24S
24X
Industrial
(-40°C to 85°C))
ATF20V8BQL Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns) tS (ns) tCO (ns) Ordering Code Package Operation Range
15 12 10 ATF20V8BQL-15JU
ATF20V8BQL-15PU
28J
24P3
Industrial
(-40°C to 85°C))
Package Type
28J 28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24S 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
ATF20V8B(Q)(L)
17
Packaging Information
28J – PLCC
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE DRAWING NO. REV.
B
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) 28J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 12.319 – 12.573
D1 11.430 – 11.582 Note 2
E 12.319 – 12.573
E1 11.430 – 11.582 Note 2
D2/E2 9.906 – 10.922
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
ATF20V8B(Q)(L)
18
24P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP) D
24P3
6/1/04
PIN
1
E1
A1
B
E
B1
C
L
SEATING PLANE
A
D
e
eB
eC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 5.334
A1 0.381 – –
D 31.623 – 32.131 Note 2
E 7.620 – 8.255
E1 6.096 – 7.112 Note 2
B 0.356 – 0.559
B1 1.270 – 1.651
L 2.921 – 3.810
C 0.203 – 0.356
eB – – 10.922
eC 0.000 – 1.524
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AF.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
ATF20V8B(Q)(L)
19
24S – SOIC
0º ~ 8º
PIN 1 ID
PIN 1
06/17/2002
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO. REV.
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) B
24S
R
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 2.65
A1 0.10 – 0.30
D 10.00 – 10.65
D1 7.40 – 7.60
E 15.20 – 15.60
B 0.33 – 0.51
L 0.40 – 1.27
L1 0.23 – 0.32
e 1.27 BSC
B
D
D1
e
EA
A1
L1
L
ATF20V8B(Q)(L)
20
24X – TSSOP
0.30(0.012)
0.19(0.007)
4.48(0.176)
4.30(0.169)
6.50(0.256)
6.25(0.246)
0.65(0.0256)BSC
7.90(0.311)
7.70(0.303)
0.15(0.006)
0.05(0.002)
0.20(0.008)
0.09(0.004)
0.75(0.030)
0.45(0.018)
0º ~ 8º
1.20(0.047)MAX
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
PIN 1
04/11/2001
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline
Package (TSSOP) A
24X
ATF20V8B(Q)(L)
21
Revision History
Revision Level – Release Date History
J – July 2006 Ordering Information tables updated to reflect obsolete parts.
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Fax: (33) 2-40-18-19-60
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Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
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Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
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Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
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