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©2005 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
September 8, 2005
FCBS0550
Smart Power Module (SPM)
Features
• UL Certified No.E209204(SPM27-BA package)
• 500V-5A 3-phase MOSFET inverter bridge including control
ICs for gate driving and protection
• Divided negative dc-link terminals for inverter current sensing
applications
• Single-grounded power supply due to built-in HVIC
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
Applications
• AC 200V three-phase inverter drive for small po wer a c moto r
drives
• Home appliances applications like refrigerator.
General Description
It is an advanced smart power module (SPM) that Fairchild has
newly developed and designed to provide very compact and
high performance ac motor drives mainly targeting low-power
inverter-driven application like refrigerator. It combines opti-
mized circuit protection and drive matched to low-loss MOS-
FETs. System reliability is further enhanced by the integrated
under-voltage lock-out and short-circuit protection. The high
speed built-in HVIC provides opto-coupler-less single-supply
MOSFET gate driving capability that further reduce the overall
size of the inverter system design. Each phase current of
inverter can be monitored separately due to the divided nega-
tive dc terminals.
Bottom ViewTop View
26.8mm
44mm
Bottom ViewTop View
26.8mm
44mm
Figure 1.
2www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Integrated Power Functions
• 500V-5A MOSFET inverter for three-phase DC/AC power conversion (Please refer to Fig. 3)
Integrated Drive, Protection and System Control Functions
• For inverter high-side MOSFETs: Gate drive circuit, High voltage isolated high-speed level shifting
Control circuit under-voltage (UV) protection
Note) Available bootstrap circuit example is given in Figs. 10 and 11.
• For inverter low-side MOSFETs: Gate drive circuit, Short circuit protection (SC)
Control supply circuit under-voltage (UV) protection
• Fault signaling: Corresponding to a UV fault (Low-side supply), SC fault
• Input interface: 3.3/5V CMOS/LSTTL compatible, Schmitt trigger input
Pin Configuration
Figure 2.
Top View
(1) V CC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) V FO
(21) NU
(22) NV
(23) NW
(27) P
(15) V B(V)
(16) VS(V)
(17) I N(WH)
(18) VCC(WH)
(19) V B(W)
(20) VS(W)
(24) U
(25) V
(26) W
Case Tem perature (T
C)
Dete cti n g Po i nt
Cer am ic S ubst rate
(7) CFOD
(8) CSC
(9) IN (UH)
(10) V CC(UH)
(11) V B(U)
(12) VS(U)
(13) IN(VH)
(14) VCC(VH)
(1) V CC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) V FO
(21) NU
(22) NV
(23) NW
(27) P
(15) V B(V)
(16) VS(V)
(17) I N(WH)
(18) VCC(WH)
(19) V B(W)
(20) VS(W)
U
V
(26) W
Case Tem perature (T
C)
Dete cti n g Po i nt
Cer am ic S ubst rate
(7) CFOD
(8) CSC
(9) IN (UH)
(10) V CC(UH)
(11) V B(U)
(12) VS(U)
(13) IN(VH)
(14) VCC(VH)
13.3
19.1
(1) V CC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) V FO
(21) NU
(22) NV
(23) NW
(27) P
(15) V B(V)
(16) VS(V)
(17) I N(WH)
(18) VCC(WH)
(19) V B(W)
(20) VS(W)
(24) U
(25) V
(26) W
Case Tem perature (T
C)
Dete cti n g Po i nt
Cer am ic S ubst rate
(7) CFOD
(8) CSC
(9) IN (UH)
(10) V CC(UH)
(11) V B(U)
(12) VS(U)
(13) IN(VH)
(14) VCC(VH)
(1) V CC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) V FO
(21) NU
(22) NV
(23) NW
(27) P
(15) V B(V)
(16) VS(V)
(17) I N(WH)
(18) VCC(WH)
(19) V B(W)
(20) VS(W)
U
V
(26) W
Case Tem perature (T
C)
Dete cti n g Po i nt
Cer am ic S ubst rate
(7) CFOD
(8) CSC
(9) IN (UH)
(10) V CC(UH)
(11) V B(U)
(12) VS(U)
(13) IN(VH)
(14) VCC(VH)
13.3
19.1
13.3
19.1
3www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Pin Descriptions
Pin Number Pin Name Pin Description
1V
CC(L) Low-side Common Bias Voltage for IC and MOSFETs Driving
2 COM Common Supply Ground
3IN
(UL) Signal Input for Low-side U Phase
4IN
(VL) Signal Input for Low-side V Phase
5IN
(WL) Signal Input for Low-side W Phase
6V
FO Fault Output
7C
FOD Capacitor for Fault Output Duration Time Selection
8C
SC Capacitor (Low-pass Filter) for Short-Current Detection Input
9IN
(UH) Signal Input for High-side U Phase
10 VCC(UH) High-side Bias Voltage for U Phase IC
11 VB(U) High-side Bias Voltage for U Phase MOSFET Driving
12 VS(U) High-side Bias Voltage Ground for U Phase MOSFET Driving
13 IN(VH) Signal Input for High-side V Phase
14 VCC(VH) High-side Bias Voltage for V Phase IC
15 VB(V) High-side Bias Voltage for V Phase MOSFET Driving
16 VS(V) High-side Bias Voltage Ground for V Phase MOSFET Driving
17 IN(WH) Signal Input for High-side W Phase
18 VCC(WH) High-side Bias Voltage for W Phase IC
19 VB(W) High-side Bias Voltage for W Phase MOSFET Driving
20 VS(W) High-side Bias Voltage Ground for W Phase MOSFET Driving
21 NUNegative DC–Link Input for U Phase
22 NVNegative DC–Link Input for V Phase
23 NWNegative DC–Link Input for W Phase
24 U Output for U Phase
25 V Output for V Phase
26 W Output for W Phase
27 P Positive DC–Link Input
4www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Internal Equivalent Circuit and Input/Output Pins
Note:
1. Inverter low-side is composed of three MOSFETs, and one control IC. It has gate driving and protection functions.
2. Inverter power side is comp osed of four inverter dc-link input terminals and three inverter output terminals.
3. Inverter high-side is composed of three MOSFETs and three drive ICs for each MOSFET.
Figure 3.
COM
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU (21)
NV (22)
NW (23)
U (24)
V (25)
W (26)
P (27)
(20) VS(W)
(19) VB(W)
(16) VS(V)
(15) VB(V)
(8) CSC
(7) CFOD
(6) VFO
(5) IN(WL)
(4) IN(VL)
(3) IN(UL)
(2) COM
(1) VCC(L)
VCC
VB
OUT
COM VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(18) VCC(WH)
(17) IN(WH)
(14) VCC(VH)
(13) IN(VH)
(12) VS(U)
(11) VB(U)
(10) VCC(UH)
(9) IN(UH)
VSL
5www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Absolute Maximum Ratings (TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Note:
1. The maximum junction temperature rating of the power chips integrated within the SPM is 150 °C(@TC ≤ 100°C). However, to insure safe operation of the SPM, the average
junction temperature should be limited to TJ(ave) ≤ 125°C (@TC ≤ 100°C)
Control Part
Total System
Thermal Resistan ce
Note:
2. For the measurement point of case temperature(TC), please refer to Figure 2.
Package Marking and Ordering Information
Symbol Parameter Conditions Rating Units
VPN Supply Voltage Applied between P- NU, NV, NW400 V
VPN(Surge) Supply Voltage (Surge) Applied between P- NU, NV, NW450 V
VDSS Drain-Source Voltage 500 V
± IDEach MOSFET Drain Current TC = 25°C, Peak Sinusoidal Current 5 A
± IDP Each MOSFET Drain Current (Peak) TC = 25°C, Under 1ms Pulse Width 7A
PCCollector Dissipation TC = 25°C per One Chip 25 W
TJOperating Junction Temperature (Note 1) -20 ~ 125 °C
Symbol Parameter Conditions Rating Units
VCC Control Supply Voltage Applied between VCC(UH), VCC(VH), VCC(WH), VCC(L) -
COM 20 V
VBS High-side Control Bias Volt-
age Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) -
VS(W)
20 V
VIN Input Signal Voltage Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL),
IN(WL) - COM -0.3~17 V
VFO Fault Output Supply Voltage Applied between VFO - COM -0.3~VCC+0.3 V
IFO Fault Output Current Sink Current at VFO Pin 5 mA
VSC Current Sensing Input Voltage Applied between CSC - COM -0.3~VCC+0.3 V
Symbol Parameter Conditions Rating Units
TSC Short Circuit Withstanding Time VCC = VBS = 13.5 ~ 16.5V, TJ =125°C, Non-
repetitive, VPN=400V, RShunt=0mΩ10 µs
TCModule Case Operation Temperature -20°C ≤ TJ ≤ 125°C, See Figure 2 -20 ~ 100 °C
TSTG Storage Temperature -40 ~ 125 °C
VISO Isolation Voltage 60Hz, Sinusoidal, AC 1 minute, Connection
Pins to ceramic substrate 2500 Vrms
Symbol Parameter Conditions Min. Typ. Max. Units
Rth(j-c) Junction to Case Thermal
Resistance Inverter MOSFET part (per 1/6 module) - - 4 °C/W
Device Marking Device Package Re el Size Tape Width Quantity
FCBS0550 FCBS0550 SPM27BA - - 10
6www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Electrical Characteristics (TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Note:
3. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally.
For the detailed information, please see Figure 4.
Figure 4. Switching Time Definition
Symbol Parameter Conditions Min. Typ. Max. Units
RDS(ON) Static Drain-Source On
Resistance VCC = VBS = 15V
VIN = 5V ID =2.5A, TJ = 25°C - 1.35 1.75 Ω
VSD Drain-Source Diode For-
ward Voltage VCC = VBS = 15V
VIN = 0V ID =2.5A, TJ = 25°C - - 1.20 V
HS tON Switching Times VPN = 300V, VCC = VBS = 15V
ID = 2.5A
VIN = 0V ↔ 5V, Inductive Load
(Note 3)
-0.51- µs
tC(ON) -0.16- µs
tOFF -0.72- µs
tC(OFF) -0.10- µs
trr -0.16- µs
LS tON VPN = 300V, VCC = VBS = 15V
ID = 2.5A
VIN = 0V ↔ 5V, Inductive Load
(Note 3)
-0.52- µs
tC(ON) -0.18- µs
tOFF -0.74- µs
tC(OFF) -0.10- µs
trr -0.16- µs
IDSS Drain - Source
Leakage Current VDS = VDSS - - 250 µA
tON tC(ON)
trr
Irr
10% of ID
100% of ID
90% of ID
100% of ID
10% of VDS
(a) T u rn-on
tOFF
tC(OFF)
(b) Turn-off
ID
VDS
VDS
ID
VIN VIN
10% of VDS
10% of ID
7www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Electrical Characteristics (TJ = 25°C, Unless Otherwise Specified)
Control Part
Note:
4. Short-circuit current protection is functioning only at the low-sides.
5. The fault-out pulse width tFOD depends on the capacitance value of CFOD accord ing to the following approximate equation : CFOD = 18.3 x 10 -6 x tFOD[F]
Recommended Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
IQCCL Quiescent VCC Supply
Current VCC = 15V
IN(UL, VL, WL) = 0V VCC(L) - COM - - 23 mA
IQCCH VCC = 15V
IN(UH, VH, WH) = 0V VCC(UH), VCC(VH),
VCC(WH) - COM - - 100 µA
IQBS Quiescent VBS Supply
Current VBS = 15V
IN(UH, VH, WH) = 0V VB(U) - VS(U), VB(V) -VS(V),
VB(W) - VS(W)
- - 500 µA
VFOH Fault Output Voltage VSC = 0V, V FO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V
VFOL VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 0.8 V
VSC(ref) Short Circuit Trip Level VCC = 15V (Note 4) 0.45 0.5 0.55 V
UVCCD Supply Circuit Under-
Voltage Protection Detection Level 10.7 11.9 13.0 V
UVCCR Reset Level 11.2 12.4 13.2 V
UVBSD Detection Level 10.1 11.3 12.5 V
UVBSR Reset Level 10.5 11.7 12.9 V
tFOD Fault-out Pulse Width CFOD = 33nF (Note 5) 1.0 1.8 - ms
VIN(ON) ON Threshold Voltage Applied between IN(UH), IN(VH), IN(WH), IN(UL),
IN(VL), IN(WL) - COM 2.9 - - V
VIN(OFF) OFF Threshold Voltage - - 0.8 V
Symbol Parameter Conditions Value Units
Min. Typ. Max.
VPN Supply Voltage Applied between P - NU, NV, NW- 300 400 V
VCC Control Supply Voltage Applied between VCC(UH), VCC(VH), VCC(WH),
VCC(L) - COM 13.5 15 16.5 V
VBS High-side Bias Voltage Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
13.0 15 18.5 V
dVCC/dt,
dVBS/dt Control supply variation -1 - 1 V/µs
tdead Blanking Time for Preventing
Arm-short For Each Input Signal 2 - - µs
fPWM PWM Input Signal -20°C ≤ TC ≤ 100°C, -20°C ≤ TJ ≤ 125°C - - 20 kHz
VSEN Voltage for Current Sensing Applied between NU, NV, NW - COM
(Including surge voltage) -4 4 V
8www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Mechanical Characteristics and Ratings
Figure 5. Flatness Measurement Position
Parameter Conditions Limits Units
Min. Typ. Max.
Mounting Torque Mounting Screw: - M3 Recommended 0.62N•m 0.51 0.62 0.72 N•m
Device Flatness Note Fig. 5 0 - +120 µm
Weight - 15.4 - g
( + )
( + )
( + )
( + )
9www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Time Charts of SPMs Protective Function
a1 : Control supply voltage rises: After the voltage rises UVCCR, the circuits start to operate when next input is applied.
a2 : Normal operation: MOSFET ON and carrying current.
a3 : Under voltage detection (UVCCD).
a4 : MOSFET OFF in spite of control input condition.
a5 : Fault output operation starts.
a6 : Under voltage reset (UVCCR).
a7 : Normal operation: MOSFET ON and carrying current.
Figure 6. Under-Voltage Protection (Low-side)
b1 : Control supply voltage rises: After the voltage reaches UVBSR, the circuits start to operate when next input is applied.
b2 : Normal operation: MOSFET ON and carrying current.
b3 : Under voltage detection (UVBSD).
b4 : MOSFET OFF in spite of control input condition, but there is no fault output signal.
b5 : Under voltage reset (UVBSR)
b6 : Normal operation: MOSFET ON and carrying current
Figure 7. Under-Voltage Protection (High-side)
Low-Side
Input Signal
Low-Side Output Current
Fault Output Signal
Low-Side Control
Supply Voltage
RESET
UVCCR
Protection
Circuit State SET RESET
UVCCD
a1 a3
a2 a4
a6
a5
a7
High-Side Input Signal
High-Side Output Current
Fault Output Signal
High-Side Control
Supply Voltage
RESET
UVBSR
Protection
Circuit State SET RESET
UVBSD
b1 b3
b2 b4 b6
b5
High-leve l (no fault output)
10 www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
(with the external shunt resistance and CR connection)
c1 : Normal operation: MOSFET ON and car rying current.
c2 : Short circuit current detection (SC trigger).
c3 : Hard MOSFET gate interrupt.
c4 : MOSFET turns OFF.
c5 : Fault output timer operation starts: The pulse width of the fault output signal is set by the external capacitor CFO.
c6 : Input “L” : MOSFET OFF state.
c7 : Input “H”: MOSFET ON state, but during the active period of fault output the MOSFET doesn’t turn ON.
c8 : MOSFET OFF state
Figure 8. Short-Circuit Current Protection (Low-side Operation only)
Low-Side Internal IGBT
Gate-Emitter Voltage
Low-Side
input Signal
Low-Side Output Current
Sensing Voltage
of the shunt
resistance
Fault Output Signal
SC Reference Voltage
CR circuit time
constant delay
SC
Protection
circuit state SET RESET
c6 c7
c3
c2
c1
c8
c4
c5
11 www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Note:
1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s
printed circui t board . The S PM inp ut sign al se ction i ntegrate s 3.3kΩ (typ.) pull-d own resisto r. Therefore, wh en usin g a n exte rnal f ilt ering re sistor, please pay attentio n to the si g-
nal voltage drop at input terminal.
2. The logic input is compatible with standard CMOS or LSTTL outputs.
Figure 9. Recommended CPU I/O Interface Circuit
Note:
1. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
2. The bootstrap resistor (RBS) should be 3 times greater than RE(H). The recommended value of RE(H) is 5.6Ω, but it can be increased up to 20Ω (maximum) for a s l ower dv/dt
of high-side.
3. The cer amic capacitor pl aced between VCC-COM should be over 1uF and mounted as close to the pins of the SPM as possible.
Fig. 10. Recommended Bootstrap Operation Circuit and Parameters
CPU
COM
5V-Line
1nF
Ω4.7k
,,
IN(UL) IN(VL) IN(WL)
,,
IN(UH) IN(VH) IN(WH)
VFO
Ω100
1nF
SPM
RPF=
CPF=
15V-Line
22uF 0.1uF
1000uF 1uF
One-Leg Diagram of SPM
Vcc
IN
COM
VB
HO
VS
Vcc
IN
COM
OUT
Inverter
Output
P
N
These Values depend on PWM Control Algorithm
DBS
RBS
RE(H)
VSL
12 www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Note:
1. To avoid malfunction, the wiring of each input should be as short as possible. (less than 2-3cm)
2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible.
3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resist ance. Plea se refer to Figure 9.
4. CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended.
5. VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin7) and COM(pin2 ). (Example : if CFOD = 33 nF, then tFO = 1.8ms
(typ.)) Please refer to the note 5 for calculation method.
6. Input signal is Hig h-Active type. Th ere is a 3.3kΩ resistor inside the IC to pul l dow n each inpu t signal line to GN D. Wh en em plo ying R C coupl ing ci rcui ts , set up such RC coup le
that input signal agree with turn-off/turn-on threshold voltage.
7. To prevent errors of the protection function, the wiring around RF and CSC should be as short as possible.
8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 1.5~2 µs.
9. Each capacitor should be mounted as close to the pins of the SPM as possible.
10. To prevent surge destruction, the wiring between the smoothing capacitor and the P&COM pins should be as short as possible. The use of a high frequency non-inductive
capacitor of around 0.1~0.22µF between the P&COM pins is recommended.
11. Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays.
12. CSPC15 should be over 1µF and mounted as close to the pins of the SPM as possible.
Fig. 11. Typical Application Circuit
Fault
15 V line
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CSP15 CSPC15
CFOD
5V lin e
RPF
CBPF
RS
M
Vdc
CDCS
Gating UH
Gating VH
Gating WH
Gating WL
Gating VL
Gating UL
CPF
C
P
U
RFU
RFV
RFW
RSU
RSV
RSW
CFU
CFV
CFW
W -Phase Current
V-Phase Current
U-Phase Current
RF
COM
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU (21)
NV (22)
NW (23)
U (24)
V (25)
W (26)
P (27)
(20) V S(W)
(19) V B(W)
(16) VS(V)
(15) V B(V)
(8) CSC
(7) C FOD
(6) VFO
(5) IN(WL)
(4) IN (VL)
(3) IN(UL)
(2) C OM
(1) VCC(L)
VCC
VB
OUT
COM VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(18) V CC(WH)
(17) IN(WH)
(14) V CC(VH)
(13) IN(VH)
(12) VS(U)
(11) V B(U)
(10) V CC(UH)
(9) IN(UH)
Input Signal for Short-
C ir c u it P r ote c tion
CSC
RE(UH)
VSL
RE(VH)
RE(WH)
13 www.fairchildsemi.com
FCBS0550 Rev. A
FCBS0550 Smart Power Module (SPM)
Detailed Package Outline Drawings
14 www.fairchildsemi.com
FCBS0550 Rev. A
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