{ | i i i Bi EAE ante e: (Sea | WS57C010F ADVANCE INFORMATION : . E INTEGRATION, INC. 1 Meg (128K x 8) BYTE-WIDE EPROM KEY FEATURES e Ultra-High Performance Fast Programming 55ns 15 Seconds Typical Simplified Upgrade Path e EPI Processing Vpp and PGM Are Dont Care During Latch-Up Immunity to 200 mA Normal Read Operation ESD Protection Exceeds 2000 Volts Expandable fo 6M Bits JEDEC Standard Pin Configuration Pin Compatible with WS27C0O10L 32 Pin Dip Package GENERAL DESCRIPTION The WS57CO010F is an ultra-high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory. It is organized as 128 K-words of 8 bits each. The 55 ns access time of the WS57CO10F enables it to operate in high performance systems. The Dont Care feature during read operations allows memory expansions up to 8M bits with no printed circuit board changes. High performance microprocessors such as the 80386 and 68020 require sub-70 ns memory access times to operate at or near full speed. The WS57CO10F enables such systems to incorporate operating systems and/or applications software into EPROM. This enhances system utility by freeing up valuable RAM space for data or other program store and eliminating disk accesses for the EPROM resident routines. The WS57COI10F pin configuration was established to enable memory upgrades to 8M bits without hardware changes to the printed circuit board. Pins 1 and 31 are dont care during normal read operation. This enables higher order addresses to be connected to these pins (see Figure 2). When higher density memories are required, the printed circuit board is ready to accept the higher density device with no hardware changes. The WS57CO10F is part of a three product megabit EPROM family. Other family members are the WS27CO10L and WS57C210F. The WS27CO10L is the standard speed version of the WS57CO10F. The WS57C210F is organized in a 64K x 16 configuration which is optimal for a word-wide system. The WS57CO10F is manufactured using WSI's advanced CMOS technology. PRODUCT SELECTION GUIDE WAFER SCALE. INTEGRATION 49 DEM 9539690 ooo0a3ze 1 Hb 13-29 PARAMETER WS57C010F-55 WS57CO10F-70 Address Access Time (Max) 55 ns 70 ns Chip Select Time (Max) 55 ns 70 ns Output Enable Time (Max) 20 ns 25 ns 3-83 ad a oa a ed cf ot oes WS57CO10F ABSOLUTE MAXIMUM RATINGS* Storage Temperature........... ~65C to +125C Voltage on Any Pin with Respect to Ground.............. -0.6V to +7V Vpp with Respect to Ground ....... -0.6V to +14V Voc Supply Voltage with Respect to Ground.............. -0.6V to +7V ESD Protection ............ 00.000 cuca >2000V 7--13-29 *Notice: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTICE: Specifications contained within the following tables are subject to change. READ OPERATION DC CHARACTERISTICS 0C < Ty < +70C; Voc (Comm'I/Military) = +5V + 10%. LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNITS lo Input Load Current Vin = 5.5V 10 nA lLo Output Leakage Current Vout = 5.5V 10 pA Ippy)) Vpp Load Current Vep < Voc 10 HA Isp TTL Veco Current Standby CE = Vin 2 mA Isg CMOS Vec Current Standby CE = Vy 500 pA loos Voc Current Active CE = OF = Vy, 60 mA Vit Input Low Voltage -0.1 +08 Vv Vin Input High Voltage 2.0 Voc +1 Vv Vor Output Low Voltage lo. = 16 mA 0.4 Vv Vou Output High Voltage loy = -4 mA 2.4 Vv Vppt) Vpp Read Voltage Veco = 5.0V + 0.25 -0.1 Veo +1 V AC CHARACTERISTICS occ < Ty < +70C SYMBOL | CHARACTERISTICS TEST MSSTOMOR SS | WSS7CONOF70 | units CONDITIONS MIN | MAX | MIN | MAX tacc Address to Output Delay CE = OF = WY. 55 70 ns tce CE to Output Delay OE = ViL 55 70 ns toe OE to Output Delay CE = Vi 20 25 ns top) OE High to Output Float CE = Vy 0 20 0 25 ns Output Hold From __ tou Addresses CE or OE CE = OF = Vy 0 0 ns Whichever Occurred First NOTES: 1. Vpp should be at a TTL level except during programming. The supply current would then be the sum of Ice and Ippy. The maximum current value is with Outputs Og to O7 unloaded. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the Point where data is no longer drivensee timing diagram. 3-84 A.C. WAVEFORMS INTEGRATION 9539690 g000234 & WS57CO10F 7-F6 -/2-29 Vin ADDRESSES Vit Vin OUTPUT Vow x ADDRESS VALID tee!) p} tog) y HIGH Z ton} - H toe!) ALLL, AWAY VALID OUTPUT HIGH Z h NOTES: 1. Typical values are for Tg = 25C and nominai supply voltages. 2. This parameter is only sampled and is not 100% tested. ___ 3. OE may be delayed up to tog -tog after the falling edge of CE without impact on tge. CAPACITANCE) T, = 25C, f = 1 MHz SYMBOL PARAMETER CONDITIONS TYP MAX UNITS Cin Input Capacitance Vin = OV 4 6 pF Cout Output Capacitance Vout = OV 8 12 pF Cypp Vpp Capacitance Vpp = OV 18 25 pF A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 2.01V 2.4 2.0 2.0 > TEST POINTS g 3.3 KQ 0.8 08 DEVICE 0.45 UNDER OUT TEST I C. = 30 pF ACC. testing inputs are driven at 2.4V for a Logic 1 and 0.45V for a Logic 0. Timing measurements are made ai 2.0V C, = 30 pF ; for a Logic 1" and 0.8V for a Logic 0. C, includes Jig Capacitance 3-85 ee De eee 2a Re i Hy bane Spy ~ . 945354640 3a eR WAF GRATION ooooeas 7 ff wens. WSS7COIOF- = =~ | DIP PIN CONFIGURATIONS 7-6E 13-25 8 Mbit | 4 Mbit | 2 Mbit | 27512 | 27256 WS57CO10F 27256 | 27512 | 2 Mbit | 4 Mbit | 8 Mbit Aig | XX/Vpp | XX/Vpp } *XVpp C1 32 F Veg Vee _ | Yee | Vec Arg Ais Ais Awpq2 317 xx/PGM XX/PGM| Aig Aig Ais Ais Aus Ass Vpp As 13 30 F xx Vec Vec Aq7 Ai7 Ai7 Aq2 Ai2 Ai2 A1z Ai2 An ds 2A, Au Ag Aus Aya Ay Ay Ay A; Ar Az 475 28D Ay Aig Ais Arg Aig Aig Ag Ag Ag Ag Ag [ A, 6 27 PVA Ag 8 Ag Ag Ag As As As As As As? 26Fa, Ag Ag Ag Ag Ag Ay Ag Ay Ag Ag Ads C) 2D Ay ] Ay |_ An An An An Ag Ag Ag Ag A3 A,d9 24D 0E J OE E/Vpp OE OE OE/Vpp Ap Ao Ag Ag Ag A, 10 23 Ay ] Agog Ato Aig Aig Ato Ay Ay Ay Ay Ay AQn 220cte -| CE cE CE CE CE Ag Ao Ao Ao Ao Ay C12 250, O7 O7 O07 O7 O7 Oo Oo Oo Oo Oo O13 20010, Og O06 O6 Og Og O, 0, 0; 0; 0; 1014 19010, Os Os Os Os Os Oo Oo Og Oo Oo 0, 1 15 18o, O4 O4 Og O4 O, GND | GND [| GND | GND | GND GND C116 7Ho, 03 03 03 03 03, NOTES: 1. Plastic Dip will be available in the second half of 1988. 2. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS57C010F pins. PIN NAMES Ao-Aig Addresses CE Chip Enable OE Output Enable Op-O7 Outputs PGM Program XX Don't Care (During Read) ORDERING INFORMATION OPERATING ws! % PART NUMBER is ee RAWing | TEMPERATURE | MANUFACTURING i RANGE PROCEDURE : WS57CO10F-55D 55 | 32 Pin CERDIP. 06" D4 Comm' Standard WS57CO10F-70D 70 | 32 Pin CERDIP, 06 D4 Comm Standard WS57CO10F-70DMB | 70 | 32 Pin CERDIP. 06 D4 Military MIL-STD-883C ; Be die tai oa ce 3-86