FINAL
Publication# 18508 Rev: CAmendment: /0
Issue Date: July 1998
Am79467
Subscriber Line Interface Circuit
DISTINCTIVE CHARACTERISTICS
■Optimized for long- loo p operation
■Programmable constant-current feed
■Programmable loop-current detector
■Programmable ground-key detector
■Low standby po wer
■On-hook transmission
■–24 V to –58 V battery operation
■On-chip relay driver
■Two-wire impedance set by single external
impedance
BLOCK DIAGRAM
Two-Wire
Interface
HPA
HPB
DA
DB
BGND
VBAT
A(TIP)
B(RING)
Ground-Key
Detector
Signal
Transmission
Power-Feed
Controller
Ring-Trip
Detector
VCC VEE AGND/DGND
RINGOUT
C1
C2
E0
E1
DET
RSN
VTX
RD
RDC
CAS
Ring Relay
Driver
Input Decoder
and Control
Off-Hook
Detector
2 Am79467 Data Sheet
FINAL
ORDERING INFORMATION
Standard Products
AMD stan dard products are av ailab le in s ev eral pac kages a nd operati ng ranges . The orde r number (Valid Combina tion) is f ormed
by a combination of the elements below.
Am79467 –1JC
PERFORMANCE GRADE
–1 = 52 dB Long. Balance
–2 = 63 dB Long. Balance
OPERATING CONDITIONS
C=Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
P = 22-Pin Plastic DIP (PD 022)
D = 22-Pin Ceramic DIP (CD 3022)
DEVICE NUMBER/DESCRIPTION
Am79467
Subscriber Line Interface Circuit
Note:
* Functionality of the device from 0
°
C to +70
°
C is guaranteed by production testing. Performance from
–
40
°
C to +85
°
C is
guaranteed by characterization and periodic sampling of production units.
Valid Combinations
Am79467 –1
–2
JC
PC
DC
Valid Combinations
V alid Combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations, to check on newly
released combinations, and to obtain additional
data on AMD’s standard military grade products.
SLIC Products 3
FINAL
CONNECTION DIAGRAMS
Top View
HPA
RD
DA
DB
A(TIP)
B(RING)
BGND
VCC
RINGOUT
CAS
VBAT
HPB
VTX
VEE
RSN
AGND/DGND
RDC
E0
C1
DET
C2
E1
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
22-Pin DIP
DBRINGOUT
NC
CAS
VBAT
E1
E0
DET
NC
RD
HPA
HPB
VTX
DA
NC
BGND
NC
B(RING)
A(TIP)
NC
4 3 2 1 282726
VCC
NC
AGND
8
9
10
11
25
24
23
22
21
20
19
12 13 14 15 16 17 18
C2
RDC
28-Pin PLCC
C1
RSN
VEE
Notes:
1. Pin 1 is marked for orientation.
2. NC = No connect
7
6
5
4 Am79467 Data Sheet
FINAL
PIN DESCRIPTIONS
Pin Names Type Description
AGND/D GND Gnd Analo g and Digital ground.
A(TIP) Output Output of A(TIP) power amplifier.
BGND Gnd Battery (power) ground.
B(RING) Output Output of B(RING) power amplifier.
C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB.
CAS Capacitor Anti-saturation pin for capacitor to filter reference voltage when operating in anti-
saturation region.
DA Input Ring-trip negative. Negative input to ring-trip comparator.
DB Input Ring-trip positive. Positive input to ring-trip comparator.
DET Output Switchhook detector. When enabled, a logic Low indicates the selected detector is
tripped. The detector is selected by the logic inputs (C2–C1, E1–E0). The output is
open-collector with a built-in 15 kΩ pull-up resistor.
E0 Input DET Enable. A logic High disables DET. A logic Low enables DET.
E1 Input Ground-Key Enable. A logic High selects the off-hook detector. A logic Low selects the
ground-key detector. TTL compatible.
HPA Capacitor High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.
HPB Capacitor High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.
NC — No connect. This pin not internally connected.
RD Resistor Detector resistor. Detector threshold set and filter pin.
RDC Resistor DC feed resistor. Connection point for the DC feed current programming network. The
other end of the network connects to the receiver summing node (RSN). Connection point
for the DC feed current programming network. The other end of the network connects to
the receiv er summing node (RSN). VRDC is negative for normal polarity and positive for
reverse polarity.
RINGOUT Output Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
RSN Input Receive Summing Node . The metallic c urrent (AC and DC) between A(TI P) and B(RING)
is equal to 1000 times the current into this pin. The networks that program receive gain,
two-wire impedance, and feed current all connect to this node.
VBAT Battery Battery supply and connection to substrate.
VCC Power +5 V power supply.
VEE Power –5 V power s upply.
VTX Output Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic
voltage. VTX also sources the two-wire input impedance programming network.
SLIC Products 5
FINAL
ABSOLUTE MAXIMUM RATINGS
Storage temperature . . . . . . . . . . . . –60°C to +150°C
VCC with respect to AGND/DGND . . . . . 0.5 V to +7 V
VEE with respect to A GND/DGND . . . . . 0.5 V to –7 V
VBAT with respect to AGND/DGND . . . 0.5 V to –70 V
BGND with respect to AGND/DGND . . . +3 V to –3 V
A(TIP) or B(RING) to BGND:
Continuous . . . . . . . . . . . . . . . . . . . VBAT to +2 V
10 ms (f = 0.1 Hz) . . . . . . . . .VBAT – 20 V to +5 V
1µs (f = 0.1 Hz). . . . . . . . . .VBAT – 40 V to +10 V
250 ns (f = 0.1 Hz). . . . . . . .VBAT – 70 V to +15 V
Current from A(TIP) or B(RING). . . . . . . . . . . . 70 mA
Current through relay driver. . . . . . . . . . . . . . . 50 mA
Ring relay supply voltage. . . . . . . .0 V to VBAT +75V
DA and DB inputs:
Voltage on ring-trip inputs . . . . . . . . . .VBAT to 0 V
Current into ring-trip inputs . . . . . . . . . . . . ±5mA
C2–C1, E0, E1, DET
Input voltage . . . . . . . . . . . . . . . . . . . . 0 V to VCC
Output voltage (DET not active) . . . . . 0 V to VCC
Output current (DET). . . . . . . . . . . . . . . . . . 5 mA
Power Dissipation (TA≤70°C):
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W
Pea k (t < 1 00 ms, tREP > 1 s). . . . . . . . . . . . . 4 W
Note: Thermal limiting circuitry on chip will shut down the
circuit at a junction temperature of about 165
°
C. The devi ce
should never be exposed to this temperature. Operation
above 145
°
C junction temperature may degrade device
reliability. See the SLIC Packaging Considerations for more
information.
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality
at or abo ve these limits is not impl ied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient temperature . . . . . . . . . . . . . .0°C to +70°C*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
VEE . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to –5.25 V
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . –24 V to –58 V
AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
BGND with respect to
AGND/DGND . . . . . . . . . . . –100 mV to +100 mV
Operat ing Ran ges def ine thos e limit s bet ween which device
functionality is guaranteed.
* Funct ionality of the de vice from 0
°
C to +70
°
C is g uarantee d
by production testing. Perfor mance from
–
40
°
C to + 85
°
C is
guaranteed by characterization and periodic sampling of
produ cti on uni ts.
6 Am79467 Data Sheet
FINAL
ELECTR ICAL CHARAC T ERISTICS
Description Test Conditions (See Note 1) Min Typ Max Unit Note
Transmission Performance
2-wire return loss 200 Hz to 500 Hz
500Hz to 1kHz
1.0 k Hz to 3.4 kHz
25
27
23 dB 1, 4
ZVTX, Analog output impedance 3 20 Ω4
VVTX, Analog output offset voltage 0°C to +70°C
–40°C to +85°C–35
–40 +35
+40 mV —
4
Overload level, 2- wire and 4-wire RL=600Ω3.1 Vpk 2
Overload level Load impedance > 20 kΩ3.1
THD, Tota l harmonic distortion 1. 0 kHz, 0 dBm –65 –54 dB 5
THD, on-hook 0 dBm, RL=900Ω, Battery = –51 V –35.5
Longitudinal Performance
Longitudinal to metallic
L-T, L-4 balance 200 Hz to 3.4 kHz –1 parts* 52
dB
Longitudinal to metallic
L-T, L-4 balance 200Hz to 1kHz: –2 parts*
0°C to +70°C
–40°C to +85°C63
55 —
4
1 kHz to 3.4 kHz: –2 parts*
0°C to +70°C
–40°C to +85°C58
55 —
4
Longitudinal signal generation 4-L 200 Hz to 4 kHz, normal polarity 45 55
Longitu dinal curre nt per p in (A or B) Activ e state 25 35 mArms
Longitudinal impedance (A or B) 0 Hz to 100 Hz 20 35 Ω/pin
Idle Channel Noise
C-message weighted noise 2-wire: 0°C to +70°C
–40°C to +85°C+7 +10
+12 dBrnC
—
4
4-wire: 0°C to +70°C
–40°C to +85°C+7 +10
+12 —
4
Psophometr ic weighted noise 2-wire: 0°C to +70°C
–40°C to +85°C–83 –80
–78 dBmp 4
4-wire: 0°C to +70°C
–40°C to +85°C–83 –80
–78
Receive Summing Node (RSN)
RSN DC vo ltage IRSN =0mA 0 V
4
RSN impedance 200 Hz to 3.4 kHz 10 20 Ω
RSN current to metallic
loop-current gain 300 Hz to 3.4 k Hz 0°C to +70°C
–40°C to +85°C988
980 1000
1000 1012
1020
Note:
* Performance Grade
SLIC Products 7
FINAL
ELECTR ICAL CHARAC T ERISTICS (continued)
Description Test Conditions (See Note 1) Min Typ Max Unit Note
Insertion Loss and Balance Return Signal
(2-Wire to 4-Wire, 4-Wire to 2-Wire, and 4-Wire to 4-Wire, See Test Circuits A and B)
Gain accuracy over temperature 0 dBm, 1 kHz 0°C to +70°C
–40°C to +85°C–0.15
–0.20 0
0+0.15
+0.20
dB
3
4
Gain accuracy over frequency 300 Hz to 3.4 kHz 0°C to +70°C
(relative to 1 kHz): –40 °C to +85°C–0.10
–0.15 +0.10
+0.15 3
4
Gain tracking +3 dBm to –55 dBm 0°C to +70°C
(relative to 0 dBm): –4 0 °C to +85°C–0.10
–0.15 +0.10
+0.15 3, 4
4
Group delay 0 dBm, 1 kHz 5.3 µs5
Line Characteristics
Long loops, Active state BAT = –50 V, RLDC = 2000 Ω21
mA
4
IL, Loop current accuracy IL in constant-current region 0.915ILIL1.085IL
IL, Accuracy, Standby state TA = 25°C0.8ILIL1.2IL
IL, Loop current Disconnect, RL=0 100 µA
VAB, Open Circuit voltage VBAT = –50 V 42.8 V
Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State
VCC
VEE
VBAT
50 Hz to 3.4 kHz
50 Hz to 3.4 kHz
50 Hz to 3.4 kHz
30
30
35
40
36
41 dB 5
Effective internal resistance CAS pin to GND 60 kΩ4
Off-Hook Detector
On-threshold RD=33kΩ11.3 17.3
mAOff-threshold RD=33kΩ9.85 14.7
Hysteresis RD=33kΩ03.2
Power Dissipation, Battery = –58 V
On-hook Open Circuit state 25
mWOn-hook Standby state 50
On-hook Active state RL=∞, VBAT = –50 V 145 300
Off-hook Active state RL=0Ω
RL=300Ω
RL=600Ω
1.5
1.4
1.2
1.8
1.6
1.4 W
ILVBAT 3 V–
RL1800+
--------------------------------=
8 Am79467 Data Sheet
FINAL
ELECTR ICAL CHARAC T ERISTICS (continued)
Description Test Conditions (See Note 1) Min Typ Max Unit Note
Supply Currents, Battery = –58 V
ICC, on-hook VCC supply current Open Circuit state
Standby state
Active state, VBAT =–50V
1.2
1.7
4.8
2.0
2.5
6.5
mA
IEE, on-hook VEE supply current Open Circuit state
Standby state
Active state, VBAT =–50V
0.5
0.9
1.9
1.3
1.6
3.0
IBAT, on-hook VBAT supply current Open Circuit state
Standby state
Active state, VBAT =–50V
0.3
0.7
2.6
1.2
1.6
4.5
Ground-Key Detector Thresholds
IA and IB delta to trigger the
ground-ke y dete cto r 81217
mAIA and IB delta to clear th e triggered
ground-ke y dete cto r 3712
Hysteresis 358
Ring-Trip Detector Input
Bias current –500 –100 nA
Offset voltage Source resistance = 0 to 2 MΩ–50 0 +50 mV
Input resistance Unbalanced
Balanced 1
3MΩ4
Input common mode range VBAT –2 V
Logic Inputs (C2–C1, E0, E1)
VIH, Input High voltage 2.0 V
VIL, I nput Low voltage 0.8
IIH, Input High current All inputs except E1 –75 40
µAInput High current Input E1 –75 45
IIL, I nput Low current –500
Logic Output (DET)
VOH, Output Low voltage IOUT = 0.8 mA, 15 kΩ to VCC 0.40 V
VOL, Output High voltage IOUT = –0.1 mA, 15 kΩ to VCC 2.4
Internal pull-up resistor 8 25 kΩ
Relay Driv er Output (RINGOUT)
On voltage IOL = 25 mA +0.2 +0.75 V
Off leakage VOH =+12V 10 µA
SLIC Products 9
FINAL
RELAY DRIVER SCHEMATIC
SWITCHING CHARA CTERISTICS
Symbol Parameter Test Conditions Temperature
Ranges Min Typ Max Unit Note
tgkde E1 Low to DET High (E0 = 1)
E1 Low to DET Low (E0 = 1) Ground-Key Detect state
RL open, RG connected
(See Figures E and F)
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
3.8
4.0
1.1
1.6
µs4
tgkdd E0 High to DET Low (E1 = 0) 0°C to +70°C
–40°C to +85°C1.1
1.6
tgkd0 E0 Low to DET High (E1 = 0) 0°C to +70°C
–40°C to +85°C3.8
4.0
tshde E1 High to DET Low (E0 = 1)
E1 High to DET High (E0 = 1) Switchhook Detect state
RL=600Ω, RG open
(See Figures E and F)
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
1.2
1.7
3.8
4.0
tshdd E0 High to DET Low (E1 = 1) 0°C to +70°C
–40°C to +85°C1.1
1.6
tshd0 E0 Low to DET High (E1 = 1) 0°C to +70°C
–40°C to +85°C3.8
4.0
RINGOUT
BGND
10 Am79467 Data Sheet
FINAL
SWITCHING WAVEFORMS
DET
tgkde
DET
tshdd
Note:
All delays measured at 1.4 V level.
E1
E1
E0
E1 to DET
E0 to DET
tshde tgkde tshde
tshd0 tgkdd tgkd0
SLIC Products 11
FINAL
Notes:
1. Unless otherwise noted, test conditions are BAT = –52 V, V
CC
=+5V, V
EE
=–5V, R
L
=600
Ω
, C
HP
=18nF,
R
DC1
=R
DC2
= 52.3 k
Ω
, C
DC
=0.68
µ
F, R
D
=33k
Ω
, no fuse resistors, D
1
= 1N400x, two-wire AC input impedance is a
600
Ω
resistance synthesized by the programming network shown below.
2. Overload level is defined when THD = 1%.
3. Balance return signal is the signal generated at V
TX
by V
RX
. This specification assumes the two-wire AC load impedance
matches the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
Note:
E0 = 1. For E0 = 0, DET = logic level High.
Table 1. SLIC Decoding
State E1 C1 C2 Two-Wire Status Detector Mode DET Output
0 0 0 0 Open Circuit No act ive detect or Logic level High
1 0 0 1 Active Ground-key detector Ground key
2 0 1 0 Ringing No active detector Logic level High
3 0 1 1 Standby Ground-key detector Ground key
4 1 0 0 Open Circuit No act ive detect or Logic level High
5 1 0 1 Active Loop-current detector Loop-current status
6 1 1 0 Ringing Ring-trip detector Ring-trip status
7 1 1 1 Standby Loop-current detector Loop-current status
VTX
RSN
RT1
RT2
CT1
RRX VRX
Where: R T1 =R
T2 =R
RX =300kΩ, CT1 =150pF*
* CT1 is not required w he n 23 dB tw o-wire return loss at hig he r voice frequenc ies
is acceptable. If CT1 is not used, RT1 and RT2 can be combined into one resistor.
If this SLIC is used with a DSLAC™ device, CT1 is not require d.
12 Am79467 Data Sheet
FINAL
Table 2. User-Programmable Components
Where ZT is connected between the VTX and RSN pins. The
fuse resis tor s are RF, and Z 2WIN is the desired 2-w ire A C input
impeda nce. When c om puti ng ZT, the internal current amplifier
pole and any external stray capacitance between VTX and
RSN must be taken into account.
Where ZRX is connected from VRX to the RSN pin and ZT is
defined above. This equation sets the receive gain to 0 dB
when the SLIC is terminated with an impedance equal to
Z2WIN.
Where RDC1, RDC2, and CDC form the network connected to
the RDC pin. RDC1 and RDC2 are approximately equal. ILOOP
is the desired loop current in the constant- cur rent regi on.
Where R D and CD form t he ne twor k co nne cte d from R D t o
–5 V a nd I T is t he t hr esho ld cu rren t be twe en on ho ok and
off hook.
Where CCAS is the regulator filter capacitor and fc is the
desired filter cut-off frequency.
ZT1000 Z2WIN 2RF
–()=
ZRX ZT
2
------=
RDC1 RDC2
+2500 V
ILOOP
------------------=
CDC 30 ms 1
RDC1
------------- 1
RDC2
-------------+
=
RD365
IT
---------,=C
D0.5 ms
RD
----------------=
CCAS 1
1.2 105
•()fc
-------------------------------=
SLIC Products 13
FINAL
DC FEED CHARACTERISTICS
RDC =104.6kΩ
VBAT =51.3V
RD=33kΩ
a. VA–VB (VAB) Voltage vs. Loop Current (Typical)
Notes:
1. Constant-current region:
2. Anti-sat (battery tracking) turn-on:
3. Open Circuit voltage:
4. Anti-sat region (I
L
>I
DET
):
5. Anti-sat region (I
L
<I
DET
):
6. Lo op-d ete ct (I
DET
) threshold:
7. Anti-sat transition region, off-hook to on-hook
8. Anti-sat transition region, on-hook to off-hook
IL2500
RDC
------------=
VAB 0.96 VBAT 3.65–=
VAB 1.025 VBAT 6.23–=
VAB 0.96 VBAT 3.65–2500
600
------------ILRDC
600
-----------
–+=
VAB 1.025 VBAT 6.23–I
LRDC
600
-----------
–=
IDET 365
RD
---------=
50
45
40
35
30
25
20
15
10
5
0
0 5 10 15 20 25 30
Loop Current (mA)
VAB (V)
357
8
42
1
6
14 Am79467 Data Sheet
FINAL
DC FEED CHARACTERISTICS (continued)
RDC = 104.6 kΩ
VBAT =51.3V
RD=33kΩb. Loop Current vs. Load Resistance (Typical)
30
25
20
15
10
5
00 1000 2000 3000 4000 5000 6000
Loop Current (mA)
Load Resistance (Ω)
A
B
IL
RSN
RDC
RDC1
RDC2 CDC
SLIC
RL
a
b
Feed current programmed by RDC1 and RDC2
c. Feed Programming
Figure 1. DC Feed Characteristics
SLIC Products 15
FINAL
TEST CIRCUITS
IL2-4 =20log(V
TX /V
AB)
A. Two- to Four-Wire Insertion Loss
VAB
RL
2
RL
2
A(TIP)
B(RING)
VTX
RSN
AGND
SLIC
VAB
A(TIP)
B(RING)
VTX
RSN
AGND
SLIC
RL
IL4-2 =20log(V
AB /V
RX)
BRS = 20 log (VTX /V
RX)
B. Four - to T w o-Wire Ins ertion Lo ss and Balance Return Signal
RT
RT
RRX RRX
VRX
VL
VAB
A(TIP)
B(RING)
VTX
RSN
AGND
SLIC
VL
S2 Open, S1 Closed:
L-T Long. Bal. = 20 log (VAB /V
L)
L-4 Long. Bal. = 20 log (VTX /V
L)
S2 Closed, S1 Open:
4-L Long. Sig. Gen. = 20 log (V L/V
RX)
C. Longitudinal Balanc e
RT
RRX
VRX
S2
RL
2
RL
2
S1
VL
C
Note:
Z
D
is the desired impedance (e.g., the
characteristic impedance of the line).
RL= 20 log (2 VM/V
S)
VM
A(TIP)
B(RING)
VTX
RSN
AGND
SLIC RT1
RRX
VS
RT2 CT1
ZD
R
RZIN
D. Two-Wire Return Loss Tes t Circuit
1
ωC<< RL
16 Am79467 Data Sheet
FINAL
TEST CIRCUITS (continued)
E. Loop-Detector Switching
VCC
A(TIP)
B(RING)
DET
E1
6.2 kΩ
RL= 600 Ω15 pF
A(TIP)
B(RING)
RG: 2 kΩ at VBAT =–48VRG
F. Ground-Key Switching
SLIC Products 17
FINAL
TEST CIRCUITS (continued)
BATTERY
GROUND
ANALOG
GROUND
DIGITAL
GROUND
VCC
VEE
RD
RD
VTX
AGND/
DGND
RSN RRX
RDC2
RDC1
CDC
RT
RDC
E0
C2
C1
+5 V –5V
VBAT
DET
D1
BGND
RINGOUT
HPB
CHP
A(TIP)
DB
DA
A(TIP)
B(RING)
CAS
CCAS
2.2 nF
2.2 nF
VTX
VRX
G. Am79467 Test Circuit
HPA
B(RING)
CBAT
BAT
E1
18 Am79467 Data Sheet
FINAL
REVISION SUMMARY
Revision A to Revision B
•Minor changes to the data sheet style and format were made to conform to AMD standards.
•Electrical Characteristics—Under Longitudinal P erformance, the specifications for Longitudinal to Metallic moved
from the Typ column to the Min column.
•Table 2—The equation on the second row was revised.
Revision B to Revision C
•Minor changes to the data sheet style and format were made to conform to AMD standards.
Trademarks
Copyright 1998 Advanced Micro Devices, All rights reserved.
AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc.
DSLAC and QSLAC are trademarks of Advanced Micro Dev ices, Inc.
Product names used in this public ation are for identification purposes only and may be trademar ks of their respective companies.
